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Removed namespace tlm in header files.

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This commit is contained in:
Lukas Steiner
2020-04-03 16:30:30 +02:00
parent 6c0ebb0e88
commit 2e255217e2
75 changed files with 237 additions and 246 deletions
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12
DRAMSys/library/src/common/TlmRecorder.h
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@@ -53,8 +53,6 @@
#include "DebugManager.h"
#include "utils.h"
using namespace tlm;
class TlmRecorder
{
public:
@@ -77,12 +75,12 @@ public:
this->traces = traces;
}
void recordPhase(tlm_generic_payload &trans, tlm_phase phase,
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase,
sc_time time);
void recordPower(double timeInSeconds, double averagePower);
void recordDebugMessage(std::string message, sc_time time);
void updateDataStrobe(const sc_time &begin, const sc_time &end,
tlm_generic_payload &trans);
tlm::tlm_generic_payload &trans);
void closeConnection();
private:
@@ -121,8 +119,8 @@ private:
void createTables(std::string pathToURI);
void setUpTransactionTerminatingPhases();
void introduceTransactionSystem(tlm_generic_payload &trans);
void removeTransactionFromSystem(tlm_generic_payload &trans);
void introduceTransactionSystem(tlm::tlm_generic_payload &trans);
void removeTransactionFromSystem(tlm::tlm_generic_payload &trans);
void commitRecordedDataToDB();
void insertGeneralInfo();
@@ -140,7 +138,7 @@ private:
unsigned int totalNumTransactions;
sc_time simulationTimeCoveredByRecording;
std::vector<tlm_phase> transactionTerminatingPhases;
std::vector<tlm::tlm_phase> transactionTerminatingPhases;
sqlite3 *db = NULL;
sqlite3_stmt *insertTransactionStatement, *insertRangeStatement,
*updateRangeStatement, *insertPhaseStatement, *updatePhaseStatement,

56
DRAMSys/library/src/common/dramExtensions.h
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@@ -41,8 +41,6 @@
#include <iostream>
#include <systemc.h>
using namespace tlm;
class Thread
{
public:
@@ -161,7 +159,7 @@ private:
};
class DramExtension : public tlm_extension<DramExtension>
class DramExtension : public tlm::tlm_extension<DramExtension>
{
public:
DramExtension();
@@ -172,29 +170,29 @@ public:
const BankGroup &bankgroup, const Bank &bank, const Row &row,
const Column &column, unsigned int burstlength, uint64_t payloadID);
virtual tlm_extension_base *clone() const;
virtual void copy_from(const tlm_extension_base &ext);
virtual tlm::tlm_extension_base *clone() const;
virtual void copy_from(const tlm::tlm_extension_base &ext);
static DramExtension &getExtension(const tlm_generic_payload *payload);
static DramExtension &getExtension(const tlm_generic_payload &payload);
static DramExtension &getExtension(const tlm::tlm_generic_payload *payload);
static DramExtension &getExtension(const tlm::tlm_generic_payload &payload);
// Used for convience, caller could also use getExtension(..) to access these field
static Thread getThread(const tlm_generic_payload *payload);
static Thread getThread(const tlm_generic_payload &payload);
static Channel getChannel(const tlm_generic_payload *payload);
static Channel getChannel(const tlm_generic_payload &payload);
static Rank getRank(const tlm_generic_payload *payload);
static Rank getRank(const tlm_generic_payload &payload);
static BankGroup getBankGroup(const tlm_generic_payload *payload);
static BankGroup getBankGroup(const tlm_generic_payload &payload);
static Bank getBank(const tlm_generic_payload *payload);
static Bank getBank(const tlm_generic_payload &payload);
static Row getRow(const tlm_generic_payload *payload);
static Row getRow(const tlm_generic_payload &payload);
static Column getColumn(const tlm_generic_payload *payload);
static Column getColumn(const tlm_generic_payload &payload);
static uint64_t getPayloadID(const tlm_generic_payload *payload);
static uint64_t getPayloadID(const tlm_generic_payload &payload);
static Thread getThread(const tlm::tlm_generic_payload *payload);
static Thread getThread(const tlm::tlm_generic_payload &payload);
static Channel getChannel(const tlm::tlm_generic_payload *payload);
static Channel getChannel(const tlm::tlm_generic_payload &payload);
static Rank getRank(const tlm::tlm_generic_payload *payload);
static Rank getRank(const tlm::tlm_generic_payload &payload);
static BankGroup getBankGroup(const tlm::tlm_generic_payload *payload);
static BankGroup getBankGroup(const tlm::tlm_generic_payload &payload);
static Bank getBank(const tlm::tlm_generic_payload *payload);
static Bank getBank(const tlm::tlm_generic_payload &payload);
static Row getRow(const tlm::tlm_generic_payload *payload);
static Row getRow(const tlm::tlm_generic_payload &payload);
static Column getColumn(const tlm::tlm_generic_payload *payload);
static Column getColumn(const tlm::tlm_generic_payload &payload);
static uint64_t getPayloadID(const tlm::tlm_generic_payload *payload);
static uint64_t getPayloadID(const tlm::tlm_generic_payload &payload);
Thread getThread() const;
Channel getChannel() const;
@@ -224,21 +222,21 @@ private:
// Used to indicate the time when a payload is created (in a traceplayer or in a core)
// Note that this time can be different from the time the payload enters the DRAM system
//(at that time the phase BEGIN_REQ is recorded), so timeOfGeneration =< time(BEGIN_REQ)
class GenerationExtension : public tlm_extension<GenerationExtension>
class GenerationExtension : public tlm::tlm_extension<GenerationExtension>
{
public:
GenerationExtension(sc_time timeOfGeneration)
: timeOfGeneration(timeOfGeneration) {}
virtual tlm_extension_base *clone() const;
virtual void copy_from(const tlm_extension_base &ext);
virtual tlm::tlm_extension_base *clone() const;
virtual void copy_from(const tlm::tlm_extension_base &ext);
static GenerationExtension
&getExtension(const tlm_generic_payload *payload);
&getExtension(const tlm::tlm_generic_payload *payload);
sc_time TimeOfGeneration() const
{
return timeOfGeneration;
}
static sc_time getTimeOfGeneration(const tlm_generic_payload *payload);
static sc_time getTimeOfGeneration(const tlm_generic_payload &payload);
static sc_time getTimeOfGeneration(const tlm::tlm_generic_payload *payload);
static sc_time getTimeOfGeneration(const tlm::tlm_generic_payload &payload);
private:
sc_time timeOfGeneration;

4
DRAMSys/library/src/configuration/memspec/MemSpec.h
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@@ -44,8 +44,6 @@
#include "../../controller/Command.h"
#include "../../common/utils.h"
using namespace tlm;
struct MemSpec
{
MemSpec();
@@ -54,7 +52,7 @@ struct MemSpec
virtual sc_time getRefreshIntervalAB() const = 0;
virtual sc_time getRefreshIntervalPB() const = 0;
virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const = 0;
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const = 0;
virtual TimeInterval getIntervalOnDataStrobe(Command) const = 0;
sc_time getCommandLength(Command) const;

2
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
View File

@@ -35,6 +35,8 @@
#include "MemSpecDDR3.h"
using namespace tlm;
sc_time MemSpecDDR3::getRefreshIntervalAB() const
{
return tREFI;

2
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
View File

@@ -81,7 +81,7 @@ struct MemSpecDDR3 final : public MemSpec
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;
virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override;
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
};

2
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
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@@ -35,6 +35,8 @@
#include "MemSpecDDR4.h"
using namespace tlm;
sc_time MemSpecDDR4::getRefreshIntervalAB() const
{
return tREFI;

2
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
View File

@@ -87,7 +87,7 @@ struct MemSpecDDR4 final : public MemSpec
virtual sc_time getRefreshIntervalPB() const override;
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override;
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
};

2
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
View File

@@ -35,6 +35,8 @@
#include "MemSpecGDDR5.h"
using namespace tlm;
sc_time MemSpecGDDR5::getRefreshIntervalAB() const
{
return tREFI;

2
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h
View File

@@ -83,7 +83,7 @@ struct MemSpecGDDR5 final : public MemSpec
virtual sc_time getRefreshIntervalPB() const override;
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override;
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
};

2
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
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@@ -35,6 +35,8 @@
#include "MemSpecGDDR5X.h"
using namespace tlm;
sc_time MemSpecGDDR5X::getRefreshIntervalAB() const
{
return tREFI;

2
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h
View File

@@ -83,7 +83,7 @@ struct MemSpecGDDR5X final : public MemSpec
virtual sc_time getRefreshIntervalPB() const override;
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override;
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
};

2
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
View File

@@ -35,6 +35,8 @@
#include "MemSpecGDDR6.h"
using namespace tlm;
sc_time MemSpecGDDR6::getRefreshIntervalAB() const
{
return tREFI;

2
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h
View File

@@ -86,7 +86,7 @@ struct MemSpecGDDR6 final : public MemSpec
virtual sc_time getRefreshIntervalPB() const override;
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override;
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
};

2
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
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@@ -35,6 +35,8 @@
#include "MemSpecHBM2.h"
using namespace tlm;
MemSpecHBM2::MemSpecHBM2()
{
commandLengthInCycles[Command::ACT] = 2;

2
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h
View File

@@ -85,7 +85,7 @@ struct MemSpecHBM2 final : public MemSpec
virtual sc_time getRefreshIntervalPB() const override;
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override;
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
};

2
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
View File

@@ -35,6 +35,8 @@
#include "MemSpecLPDDR4.h"
using namespace tlm;
MemSpecLPDDR4::MemSpecLPDDR4()
{
commandLengthInCycles[Command::ACT] = 4;

2
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h
View File

@@ -78,7 +78,7 @@ struct MemSpecLPDDR4 final : public MemSpec
virtual sc_time getRefreshIntervalPB() const override;
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override;
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
};

2
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -35,6 +35,8 @@
#include "MemSpecWideIO.h"
using namespace tlm;
sc_time MemSpecWideIO::getRefreshIntervalAB() const
{
return tREFI;

2
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h
View File

@@ -91,7 +91,7 @@ struct MemSpecWideIO final : public MemSpec
virtual sc_time getRefreshIntervalPB() const override;
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override;
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
};

2
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
View File

@@ -35,6 +35,8 @@
#include "MemSpecWideIO2.h"
using namespace tlm;
sc_time MemSpecWideIO2::getRefreshIntervalAB() const
{
return tREFI;

2
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h
View File

@@ -72,7 +72,7 @@ struct MemSpecWideIO2 final : public MemSpec
virtual sc_time getRefreshIntervalPB() const override;
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getExecutionTime(Command, const tlm_generic_payload &) const override;
virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command) const override;
};

2
DRAMSys/library/src/controller/BankMachine.cpp
View File

@@ -34,6 +34,8 @@
#include "BankMachine.h"
using namespace tlm;
BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, Bank bank)
: scheduler(scheduler), checker(checker), bank(bank)
{

6
DRAMSys/library/src/controller/BankMachine.h
View File

@@ -44,8 +44,6 @@
#include "scheduler/SchedulerIF.h"
#include "checker/CheckerIF.h"
using namespace tlm;
class SchedulerIF;
class CheckerIF;
@@ -60,7 +58,7 @@ class BankMachine
public:
virtual ~BankMachine() {}
virtual sc_time start() = 0;
std::pair<Command, tlm_generic_payload *> getNextCommand();
std::pair<Command, tlm::tlm_generic_payload *> getNextCommand();
void updateState(Command);
void block();
@@ -73,7 +71,7 @@ public:
protected:
BankMachine(SchedulerIF *, CheckerIF *, Bank);
tlm_generic_payload *currentPayload = nullptr;
tlm::tlm_generic_payload *currentPayload = nullptr;
SchedulerIF *scheduler;
CheckerIF *checker;
Command nextCommand;

1
DRAMSys/library/src/controller/Command.cpp
View File

@@ -38,6 +38,7 @@
#include "Command.h"
#include <systemc.h>
using namespace tlm;
using namespace DRAMPower;
std::string commandToString(Command command)

12
DRAMSys/library/src/controller/Command.h
View File

@@ -42,8 +42,6 @@
#include <tlm.h>
#include "../common/third_party/DRAMPower/src/MemCommand.h"
using namespace tlm;
// DO NOT CHANGE THE ORDER!
DECLARE_EXTENDED_PHASE(BEGIN_RD); // 5
DECLARE_EXTENDED_PHASE(BEGIN_WR); // 6
@@ -92,11 +90,11 @@ enum Command
};
std::string commandToString(Command);
tlm_phase commandToPhase(Command);
Command phaseToCommand(tlm_phase);
DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase);
bool phaseNeedsEnd(tlm_phase);
tlm_phase getEndPhase(tlm_phase);
tlm::tlm_phase commandToPhase(Command);
Command phaseToCommand(tlm::tlm_phase);
DRAMPower::MemCommand::cmds phaseToDRAMPowerCommand(tlm::tlm_phase);
bool phaseNeedsEnd(tlm::tlm_phase);
tlm::tlm_phase getEndPhase(tlm::tlm_phase);
unsigned numberOfCommands();
bool isBankCommand(Command);
bool isRankCommand(Command);

2
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -59,6 +59,8 @@
#include "powerdown/PowerDownManagerStaggered.h"
#include "powerdown/PowerDownManagerDummy.h"
using namespace tlm;
Controller::Controller(sc_module_name name) :
ControllerIF(name)
{

16
DRAMSys/library/src/controller/Controller.h
View File

@@ -53,8 +53,6 @@
#include "powerdown/PowerDownManagerIF.h"
#include "respqueue/RespQueueIF.h"
using namespace tlm;
class BankMachine;
class SchedulerIF;
class PowerDownManagerStaggered;
@@ -67,12 +65,12 @@ public:
virtual ~Controller();
protected:
virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &, tlm_phase &, sc_time &);
virtual tlm_sync_enum nb_transport_bw(tlm_generic_payload &, tlm_phase &, sc_time &);
virtual unsigned int transport_dbg(tlm_generic_payload &);
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &);
virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &);
virtual unsigned int transport_dbg(tlm::tlm_generic_payload &);
virtual void sendToFrontend(tlm_generic_payload *, tlm_phase);
virtual void sendToDram(Command, tlm_generic_payload *);
virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase);
virtual void sendToDram(Command, tlm::tlm_generic_payload *);
private:
unsigned totalNumberOfPayloads = 0;
@@ -89,9 +87,9 @@ private:
std::vector<RefreshManagerIF *> refreshManagers;
std::vector<PowerDownManagerIF *> powerDownManagers;
tlm_generic_payload *payloadToAcquire = nullptr;
tlm::tlm_generic_payload *payloadToAcquire = nullptr;
sc_time timeToAcquire = sc_max_time();
tlm_generic_payload *payloadToRelease = nullptr;
tlm::tlm_generic_payload *payloadToRelease = nullptr;
sc_time timeToRelease = sc_max_time();
void finishBeginReq();

8
DRAMSys/library/src/controller/ControllerIF.h
View File

@@ -7,8 +7,6 @@
#include <tlm_utils/simple_target_socket.h>
#include "../configuration/Configuration.h"
using namespace tlm;
// Utiliy class to pass around the DRAMSys, without having to propagate the template defintions
// throughout all classes
class ControllerIF : public sc_module
@@ -70,9 +68,9 @@ protected:
SC_HAS_PROCESS(ControllerIF);
// Virtual transport functions
virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &, tlm_phase &, sc_time &) = 0;
virtual unsigned int transport_dbg(tlm_generic_payload &) = 0;
virtual tlm_sync_enum nb_transport_bw(tlm_generic_payload &, tlm_phase &, sc_time &) = 0;
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) = 0;
virtual unsigned int transport_dbg(tlm::tlm_generic_payload &) = 0;
virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) = 0;
// Bandwidth related
class IdleTimeCollector

3
DRAMSys/library/src/controller/ControllerRecordable.cpp
View File

@@ -33,9 +33,10 @@
*/
#include "ControllerRecordable.h"
#include "../configuration/Configuration.h"
using namespace tlm;
tlm_sync_enum ControllerRecordable::nb_transport_fw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay)
{

14
DRAMSys/library/src/controller/ControllerRecordable.h
View File

@@ -45,15 +45,15 @@ public:
Controller(name), tlmRecorder(tlmRecorder) {}
private:
tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay) override;
tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans,
tlm_phase &phase, sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans,
tlm::tlm_phase &phase, sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans,
tlm::tlm_phase &phase, sc_time &delay) override;
void sendToFrontend(tlm_generic_payload *, tlm_phase) override;
void sendToDram(Command, tlm_generic_payload *) override;
void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase) override;
void sendToDram(Command, tlm::tlm_generic_payload *) override;
void recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay);
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay);
TlmRecorder *tlmRecorder;
};

6
DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h
View File

@@ -40,14 +40,12 @@
#include <vector>
#include "../Command.h"
using namespace tlm;
class CmdMuxIF
{
public:
virtual ~CmdMuxIF() {}
virtual std::pair<Command, tlm_generic_payload *>
selectCommand(std::vector<std::pair<Command, tlm_generic_payload *>> &) = 0;
virtual std::pair<Command, tlm::tlm_generic_payload *>
selectCommand(std::vector<std::pair<Command, tlm::tlm_generic_payload *>> &) = 0;
};
#endif // CMDMUXIF_H

2
DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp
View File

@@ -36,6 +36,8 @@
#include "../../common/dramExtensions.h"
using namespace tlm;
std::pair<Command, tlm_generic_payload *>
CmdMuxOldest::selectCommand(std::vector<std::pair<Command, tlm_generic_payload *>> &readyCommands)
{

4
DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h
View File

@@ -40,8 +40,8 @@
class CmdMuxOldest : public CmdMuxIF
{
public:
std::pair<Command, tlm_generic_payload *>
selectCommand(std::vector<std::pair<Command, tlm_generic_payload *>> &);
std::pair<Command, tlm::tlm_generic_payload *>
selectCommand(std::vector<std::pair<Command, tlm::tlm_generic_payload *>> &);
};
#endif // CMDMUXOLDEST_H

2
DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp
View File

@@ -36,6 +36,8 @@
#include "../../common/dramExtensions.h"
using namespace tlm;
std::pair<Command, tlm_generic_payload *>
CmdMuxStrict::selectCommand(std::vector<std::pair<Command, tlm_generic_payload *>> &readyCommands)
{

4
DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h
View File

@@ -40,8 +40,8 @@
class CmdMuxStrict : public CmdMuxIF
{
public:
std::pair<Command, tlm_generic_payload *>
selectCommand(std::vector<std::pair<Command, tlm_generic_payload *>> &);
std::pair<Command, tlm::tlm_generic_payload *>
selectCommand(std::vector<std::pair<Command, tlm::tlm_generic_payload *>> &);
private:
uint64_t nextPayloadID = 0;

2
DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp
View File

@@ -34,6 +34,8 @@
#include "PowerDownManagerDummy.h"
using namespace tlm;
std::pair<Command, tlm_generic_payload *> PowerDownManagerDummy::getNextCommand()
{
return std::pair<Command, tlm_generic_payload *>(Command::NOP, nullptr);

4
DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h
View File

@@ -37,8 +37,6 @@
#include "PowerDownManagerIF.h"
using namespace tlm;
class PowerDownManagerDummy final : public PowerDownManagerIF
{
public:
@@ -48,7 +46,7 @@ public:
virtual void triggerExit() override {}
virtual void triggerInterruption() override {}
virtual std::pair<Command, tlm_generic_payload *> getNextCommand() override;
virtual std::pair<Command, tlm::tlm_generic_payload *> getNextCommand() override;
virtual void updateState(Command) override {}
virtual sc_time start() override;
};

4
DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h
View File

@@ -40,8 +40,6 @@
#include <tlm.h>
#include "../Command.h"
using namespace tlm;
class PowerDownManagerIF
{
public:
@@ -51,7 +49,7 @@ public:
virtual void triggerExit() = 0;
virtual void triggerInterruption() = 0;
virtual std::pair<Command, tlm_generic_payload *> getNextCommand() = 0;
virtual std::pair<Command, tlm::tlm_generic_payload *> getNextCommand() = 0;
virtual void updateState(Command) = 0;
virtual sc_time start() = 0;
};

2
DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp
View File

@@ -35,6 +35,8 @@
#include "PowerDownManagerStaggered.h"
#include "../../common/utils.h"
using namespace tlm;
PowerDownManagerStaggered::PowerDownManagerStaggered(Rank rank, CheckerIF *checker)
: rank(rank), checker(checker)
{

6
DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h
View File

@@ -39,8 +39,6 @@
#include "../BankMachine.h"
#include "../checker/CheckerIF.h"
using namespace tlm;
class PowerDownManagerStaggered final : public PowerDownManagerIF
{
public:
@@ -50,13 +48,13 @@ public:
virtual void triggerExit() override;
virtual void triggerInterruption() override;
virtual std::pair<Command, tlm_generic_payload *> getNextCommand() override;
virtual std::pair<Command, tlm::tlm_generic_payload *> getNextCommand() override;
virtual void updateState(Command) override;
virtual sc_time start() override;
private:
enum class PdmState {Idle, ActivePdn, PrechargePdn, SelfRefresh, ExtraRefresh} state = PdmState::Idle;
tlm_generic_payload powerDownPayload;
tlm::tlm_generic_payload powerDownPayload;
Rank rank;
CheckerIF *checker;

2
DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.cpp
View File

@@ -37,6 +37,8 @@
#include "../../common/utils.h"
#include "../../common/dramExtensions.h"
using namespace tlm;
RefreshManagerBankwise::RefreshManagerBankwise(std::vector<BankMachine *> &bankMachines,
PowerDownManagerIF *powerDownManager, Rank rank, CheckerIF *checker)
: bankMachinesOnRank(bankMachines), powerDownManager(powerDownManager), rank(rank), checker(checker)

8
DRAMSys/library/src/controller/refresh/RefreshManagerBankwise.h
View File

@@ -43,23 +43,21 @@
#include <utility>
#include <list>
using namespace tlm;
class RefreshManagerBankwise final : public RefreshManagerIF
{
public:
RefreshManagerBankwise(std::vector<BankMachine *> &, PowerDownManagerIF *, Rank, CheckerIF *);
virtual std::pair<Command, tlm_generic_payload *> getNextCommand() override;
virtual std::pair<Command, tlm::tlm_generic_payload *> getNextCommand() override;
virtual sc_time start() override;
virtual void updateState(Command, tlm_generic_payload *) override;
virtual void updateState(Command, tlm::tlm_generic_payload *) override;
private:
enum class RmState {Regular, Pulledin} state = RmState::Regular;
const MemSpec *memSpec;
std::vector<BankMachine *> &bankMachinesOnRank;
PowerDownManagerIF *powerDownManager;
std::vector<tlm_generic_payload> refreshPayloads;
std::vector<tlm::tlm_generic_payload> refreshPayloads;
sc_time timeForNextTrigger = sc_max_time();
sc_time timeToSchedule = sc_max_time();
Rank rank;

2
DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp
View File

@@ -34,6 +34,8 @@
#include "RefreshManagerDummy.h"
using namespace tlm;
std::pair<Command, tlm_generic_payload *> RefreshManagerDummy::getNextCommand()
{
return std::pair<Command, tlm_generic_payload *>(Command::NOP, nullptr);

6
DRAMSys/library/src/controller/refresh/RefreshManagerDummy.h
View File

@@ -41,14 +41,12 @@
#include "RefreshManagerIF.h"
#include "../Command.h"
using namespace tlm;
class RefreshManagerDummy final : public RefreshManagerIF
{
public:
virtual std::pair<Command, tlm_generic_payload *> getNextCommand() override;
virtual std::pair<Command, tlm::tlm_generic_payload *> getNextCommand() override;
virtual sc_time start() override;
virtual void updateState(Command, tlm_generic_payload *) override {}
virtual void updateState(Command, tlm::tlm_generic_payload *) override {}
};
#endif // REFRESHMANAGERDUMMY_H

6
DRAMSys/library/src/controller/refresh/RefreshManagerIF.h
View File

@@ -40,16 +40,14 @@
#include <utility>
#include "../Command.h"
using namespace tlm;
class RefreshManagerIF
{
public:
virtual ~RefreshManagerIF() {}
virtual std::pair<Command, tlm_generic_payload *> getNextCommand() = 0;
virtual std::pair<Command, tlm::tlm_generic_payload *> getNextCommand() = 0;
virtual sc_time start() = 0;
virtual void updateState(Command, tlm_generic_payload *) = 0;
virtual void updateState(Command, tlm::tlm_generic_payload *) = 0;
};
#endif // REFRESHMANAGERIF_H

2
DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.cpp
View File

@@ -37,6 +37,8 @@
#include "../../configuration/Configuration.h"
#include "../../common/utils.h"
using namespace tlm;
RefreshManagerRankwise::RefreshManagerRankwise(std::vector<BankMachine *> &bankMachines,
PowerDownManagerIF *powerDownManager, Rank rank, CheckerIF *checker)
: bankMachinesOnRank(bankMachines), powerDownManager(powerDownManager), rank(rank), checker(checker)

8
DRAMSys/library/src/controller/refresh/RefreshManagerRankwise.h
View File

@@ -41,23 +41,21 @@
#include "../powerdown/PowerDownManagerIF.h"
#include "../checker/CheckerIF.h"
using namespace tlm;
class RefreshManagerRankwise final : public RefreshManagerIF
{
public:
RefreshManagerRankwise(std::vector<BankMachine *> &, PowerDownManagerIF *, Rank, CheckerIF *);
virtual std::pair<Command, tlm_generic_payload *> getNextCommand() override;
virtual std::pair<Command, tlm::tlm_generic_payload *> getNextCommand() override;
virtual sc_time start() override;
virtual void updateState(Command, tlm_generic_payload *) override;
virtual void updateState(Command, tlm::tlm_generic_payload *) override;
private:
enum class RmState {Regular, Pulledin} state = RmState::Regular;
const MemSpec *memSpec;
std::vector<BankMachine *> &bankMachinesOnRank;
PowerDownManagerIF *powerDownManager;
tlm_generic_payload refreshPayload;
tlm::tlm_generic_payload refreshPayload;
sc_time timeForNextTrigger = sc_max_time();
sc_time timeToSchedule = sc_max_time();
Rank rank;

2
DRAMSys/library/src/controller/respqueue/RespQueueFifo.cpp
View File

@@ -34,6 +34,8 @@
#include "RespQueueFifo.h"
using namespace tlm;
void RespQueueFifo::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd)
{
buffer.push({payload, strobeEnd});

8
DRAMSys/library/src/controller/respqueue/RespQueueFifo.h
View File

@@ -41,17 +41,15 @@
#include <utility>
#include <queue>
using namespace tlm;
class RespQueueFifo final : public RespQueueIF
{
public:
virtual void insertPayload(tlm_generic_payload *, sc_time) override;
virtual tlm_generic_payload *nextPayload() override;
virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) override;
virtual tlm::tlm_generic_payload *nextPayload() override;
virtual sc_time getTriggerTime() const override;
private:
std::queue<std::pair<tlm_generic_payload *, sc_time>> buffer;
std::queue<std::pair<tlm::tlm_generic_payload *, sc_time>> buffer;
};
#endif // RESPQUEUEFIFO_H

6
DRAMSys/library/src/controller/respqueue/RespQueueIF.h
View File

@@ -38,13 +38,11 @@
#include <systemc.h>
#include <tlm.h>
using namespace tlm;
class RespQueueIF
{
public:
virtual void insertPayload(tlm_generic_payload *, sc_time) = 0;
virtual tlm_generic_payload *nextPayload() = 0;
virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) = 0;
virtual tlm::tlm_generic_payload *nextPayload() = 0;
virtual sc_time getTriggerTime() const = 0;
};

2
DRAMSys/library/src/controller/respqueue/RespQueueReorder.cpp
View File

@@ -35,6 +35,8 @@
#include "RespQueueReorder.h"
#include "../../common/dramExtensions.h"
using namespace tlm;
void RespQueueReorder::insertPayload(tlm_generic_payload *payload, sc_time strobeEnd)
{
buffer[DramExtension::getPayloadID(payload)] = {payload, strobeEnd};

8
DRAMSys/library/src/controller/respqueue/RespQueueReorder.h
View File

@@ -40,19 +40,17 @@
#include "RespQueueIF.h"
#include <map>
using namespace tlm;
class RespQueueReorder final : public RespQueueIF
{
public:
virtual void insertPayload(tlm_generic_payload *, sc_time) override;
virtual tlm_generic_payload *nextPayload() override;
virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) override;
virtual tlm::tlm_generic_payload *nextPayload() override;
virtual sc_time getTriggerTime() const override;
private:
uint64_t currentPayloadID = 0;
// Muss die Zeit aller Payloads gespeichert werden?
std::map<uint64_t, std::pair<tlm_generic_payload *, sc_time>> buffer;
std::map<uint64_t, std::pair<tlm::tlm_generic_payload *, sc_time>> buffer;
};
#endif // RESPQUEUEREORDER_H

2
DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp
View File

@@ -34,6 +34,8 @@
#include "SchedulerFifo.h"
using namespace tlm;
SchedulerFifo::SchedulerFifo()
{
buffer = std::vector<std::deque<tlm_generic_payload *>>

10
DRAMSys/library/src/controller/scheduler/SchedulerFifo.h
View File

@@ -42,20 +42,18 @@
#include "../../common/dramExtensions.h"
#include "../BankMachine.h"
using namespace tlm;
class SchedulerFifo : public SchedulerIF
{
public:
SchedulerFifo();
virtual bool hasBufferSpace() override;
virtual void storeRequest(tlm_generic_payload *) override;
virtual void removeRequest(tlm_generic_payload *) override;
virtual tlm_generic_payload *getNextRequest(BankMachine *) override;
virtual void storeRequest(tlm::tlm_generic_payload *) override;
virtual void removeRequest(tlm::tlm_generic_payload *) override;
virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) override;
virtual bool hasFurtherRowHit(Bank, Row) override;
virtual bool hasFurtherRequest(Bank) override;
private:
std::vector<std::deque<tlm_generic_payload *>> buffer;
std::vector<std::deque<tlm::tlm_generic_payload *>> buffer;
unsigned requestBufferSize;
unsigned lastBankID;
};

2
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp
View File

@@ -36,6 +36,8 @@
#include <systemc.h>
using namespace tlm;
SchedulerFrFcfs::SchedulerFrFcfs()
{
buffer = std::vector<std::list<tlm_generic_payload *>>

10
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h
View File

@@ -42,20 +42,18 @@
#include "../../common/dramExtensions.h"
#include "../BankMachine.h"
using namespace tlm;
class SchedulerFrFcfs : public SchedulerIF
{
public:
SchedulerFrFcfs();
virtual bool hasBufferSpace() override;
virtual void storeRequest(tlm_generic_payload *) override;
virtual void removeRequest(tlm_generic_payload *) override;
virtual tlm_generic_payload *getNextRequest(BankMachine *) override;
virtual void storeRequest(tlm::tlm_generic_payload *) override;
virtual void removeRequest(tlm::tlm_generic_payload *) override;
virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) override;
virtual bool hasFurtherRowHit(Bank, Row) override;
virtual bool hasFurtherRequest(Bank) override;
private:
std::vector<std::list<tlm_generic_payload *>> buffer;
std::vector<std::list<tlm::tlm_generic_payload *>> buffer;
unsigned requestBufferSize;
unsigned lastBankID;
};

2
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp
View File

@@ -34,6 +34,8 @@
#include "SchedulerFrFcfsGrp.h"
using namespace tlm;
SchedulerFrFcfsGrp::SchedulerFrFcfsGrp()
{
buffer = std::vector<std::list<tlm_generic_payload *>>

12
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h
View File

@@ -43,22 +43,20 @@
#include "../../common/dramExtensions.h"
#include "../BankMachine.h"
using namespace tlm;
class SchedulerFrFcfsGrp : public SchedulerIF
{
public:
SchedulerFrFcfsGrp();
virtual bool hasBufferSpace() override;
virtual void storeRequest(tlm_generic_payload *) override;
virtual void removeRequest(tlm_generic_payload *) override;
virtual tlm_generic_payload *getNextRequest(BankMachine *) override;
virtual void storeRequest(tlm::tlm_generic_payload *) override;
virtual void removeRequest(tlm::tlm_generic_payload *) override;
virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) override;
virtual bool hasFurtherRowHit(Bank, Row) override;
virtual bool hasFurtherRequest(Bank) override;
private:
std::vector<std::list<tlm_generic_payload *>> buffer;
std::vector<std::list<tlm::tlm_generic_payload *>> buffer;
unsigned requestBufferSize;
tlm_command lastCommand = TLM_READ_COMMAND;
tlm::tlm_command lastCommand = tlm::TLM_READ_COMMAND;
unsigned lastBankID;
};

8
DRAMSys/library/src/controller/scheduler/SchedulerIF.h
View File

@@ -40,8 +40,6 @@
#include "../../common/DebugManager.h"
#include "../BankMachine.h"
using namespace tlm;
enum class BmState;
class BankMachine;
@@ -50,9 +48,9 @@ class SchedulerIF
public:
virtual ~SchedulerIF() {}
virtual bool hasBufferSpace() = 0;
virtual void storeRequest(tlm_generic_payload *) = 0;
virtual void removeRequest(tlm_generic_payload *) = 0;
virtual tlm_generic_payload *getNextRequest(BankMachine *) = 0;
virtual void storeRequest(tlm::tlm_generic_payload *) = 0;
virtual void removeRequest(tlm::tlm_generic_payload *) = 0;
virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) = 0;
virtual bool hasFurtherRowHit(Bank, Row) = 0;
virtual bool hasFurtherRequest(Bank) = 0;
};

2
DRAMSys/library/src/error/eccbaseclass.cpp
View File

@@ -1,5 +1,7 @@
#include "eccbaseclass.h"
using namespace tlm;
tlm::tlm_sync_enum ECCBaseClass::nb_transport_fw( int id,
tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_time &delay )
{

2
DRAMSys/library/src/error/eccbaseclass.h
View File

@@ -11,8 +11,6 @@
#include "../common/XmlAddressDecoder.h"
#include "../common/DebugManager.h"
using namespace tlm;
class ECCBaseClass : sc_module
{
public:

28
DRAMSys/library/src/simulation/Arbiter.h
View File

@@ -50,8 +50,6 @@
#include "../common/dramExtensions.h"
#include "../configuration/ConfigurationLoader.h"
using namespace tlm;
class Arbiter : public sc_module
{
public:
@@ -68,32 +66,32 @@ private:
// used to account for the request_accept_delay in the dram controllers
// This is a queue of new transactions. The phase of a new request is BEGIN_REQ.
std::vector<std::queue<tlm_generic_payload *>> pendingRequests;
std::vector<std::queue<tlm::tlm_generic_payload *>> pendingRequests;
// used to account for the response_accept_delay in the initiators (traceplayer, core etc.)
// This is a queue of responses comming from the memory side. The phase of these transactions is BEGIN_RESP.
std::map<unsigned int, std::queue<tlm_generic_payload *>> receivedResponses;
std::map<unsigned int, std::queue<tlm::tlm_generic_payload *>> receivedResponses;
// Initiated by initiator side
// This function is called when an arbiter's target socket receives a transaction from a device
tlm_sync_enum nb_transport_fw(int id, tlm_generic_payload &payload,
tlm_phase &phase, sc_time &fwDelay);
tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &fwDelay);
// Initiated by dram side
// This function is called when an arbiter's initiator socket receives a transaction from a memory controller
tlm_sync_enum nb_transport_bw(int channelId, tlm_generic_payload &payload,
tlm_phase &phase, sc_time &bwDelay);
tlm::tlm_sync_enum nb_transport_bw(int channelId, tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &bwDelay);
virtual unsigned int transport_dbg(int /*id*/, tlm_generic_payload &trans);
virtual unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans);
void peqCallback(tlm_generic_payload &payload, const tlm_phase &phase);
void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase);
void sendToChannel(unsigned int channelId, tlm_generic_payload &payload,
const tlm_phase &phase, const sc_time &delay);
void sendToChannel(unsigned int channelId, tlm::tlm_generic_payload &payload,
const tlm::tlm_phase &phase, const sc_time &delay);
void sendToInitiator(unsigned int id, tlm_generic_payload &payload,
const tlm_phase &phase, const sc_time &delay);
void sendToInitiator(unsigned int id, tlm::tlm_generic_payload &payload,
const tlm::tlm_phase &phase, const sc_time &delay);
void appendDramExtension(int socketId, tlm_generic_payload &payload);
void appendDramExtension(int socketId, tlm::tlm_generic_payload &payload);
std::vector<uint64_t> nextPayloadID;
bool addressIsValid(DecodedAddress &decodedAddress);

12
DRAMSys/library/src/simulation/IArbiter.h
View File

@@ -46,8 +46,6 @@
#include <tlm_utils/multi_passthrough_initiator_socket.h>
#include "../configuration/ConfigurationLoader.h"
using namespace tlm;
struct IArbiter : public sc_module
{
public:
@@ -77,18 +75,18 @@ public:
protected:
// Initiated by initiator side
// This function is called when an arbiter's target socket receives a transaction from a device
virtual tlm_sync_enum nb_transport_fw(int id, tlm_generic_payload &payload,
tlm_phase &phase, sc_time &fwDelay) = 0;
virtual tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &fwDelay) = 0;
// Initiated by dram side
// This function is called when an arbiter's initiator socket receives a transaction from a memory controller
virtual tlm_sync_enum nb_transport_bw(int channelId,
tlm_generic_payload &payload, tlm_phase &phase, sc_time &bwDelay) = 0;
virtual tlm::tlm_sync_enum nb_transport_bw(int channelId,
tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_time &bwDelay) = 0;
virtual unsigned int transport_dbg(int /*id*/,
tlm::tlm_generic_payload &trans) = 0;
void appendDramExtension(int socketId, tlm_generic_payload &payload)
void appendDramExtension(int socketId, tlm::tlm_generic_payload &payload)
{
// Append Generation Extension
GenerationExtension *genExtension = new GenerationExtension(clkAlign(

43
DRAMSys/library/src/simulation/ReorderBuffer.h
View File

@@ -40,10 +40,9 @@
#include <deque>
#include <systemc.h>
#include <tlm.h>
#include <set>
using namespace tlm;
struct ReorderBuffer: public sc_module {
public:
tlm_utils::simple_initiator_socket<ReorderBuffer> iSocket;
@@ -59,43 +58,43 @@ public:
private:
tlm_utils::peq_with_cb_and_phase<ReorderBuffer> payloadEventQueue;
deque<tlm_generic_payload *> pendingRequestsInOrder;
std::set<tlm_generic_payload *> receivedResponses;
deque<tlm::tlm_generic_payload *> pendingRequestsInOrder;
std::set<tlm::tlm_generic_payload *> receivedResponses;
bool responseIsPendingInInitator;
// Initiated by dram side
tlm_sync_enum nb_transport_bw(tlm_generic_payload &payload, tlm_phase &phase,
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase,
sc_time &bwDelay)
{
payloadEventQueue.notify(payload, phase, bwDelay);
return TLM_ACCEPTED;
return tlm::TLM_ACCEPTED;
}
// Initiated by initator side (players)
tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload, tlm_phase &phase,
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase,
sc_time &fwDelay)
{
if (phase == BEGIN_REQ) {
if (phase == tlm::BEGIN_REQ) {
payload.acquire();
} else if (phase == END_RESP) {
} else if (phase == tlm::END_RESP) {
payload.release();
}
payloadEventQueue.notify(payload, phase, fwDelay);
return TLM_ACCEPTED;
return tlm::TLM_ACCEPTED;
}
void peqCallback(tlm_generic_payload &payload, const tlm_phase &phase)
void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase)
{
//Phases initiated by initiator side
if (phase == BEGIN_REQ) {
if (phase == tlm::BEGIN_REQ) {
pendingRequestsInOrder.push_back(&payload);
sendToTarget(payload, phase, SC_ZERO_TIME );
}
else if (phase == END_RESP) {
else if (phase == tlm::END_RESP) {
responseIsPendingInInitator = false;
pendingRequestsInOrder.pop_front();
receivedResponses.erase(&payload);
@@ -103,10 +102,10 @@ private:
}
//Phases initiated by dram side
else if (phase == END_REQ) {
else if (phase == tlm::END_REQ) {
sendToInitiator(payload, phase, SC_ZERO_TIME);
} else if (phase == BEGIN_RESP) {
sendToTarget(payload, END_RESP, SC_ZERO_TIME);
} else if (phase == tlm::BEGIN_RESP) {
sendToTarget(payload, tlm::END_RESP, SC_ZERO_TIME);
receivedResponses.emplace(&payload);
sendNextResponse();
}
@@ -118,15 +117,15 @@ private:
}
}
void sendToTarget(tlm_generic_payload &payload, const tlm_phase &phase,
void sendToTarget(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase,
const sc_time &delay)
{
tlm_phase TPhase = phase;
tlm::tlm_phase TPhase = phase;
sc_time TDelay = delay;
iSocket->nb_transport_fw(payload, TPhase, TDelay);
}
void sendToInitiator(tlm_generic_payload &payload, const tlm_phase &phase,
void sendToInitiator(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase,
const sc_time &delay)
{
@@ -135,7 +134,7 @@ private:
(phase == BEGIN_RESP && pendingRequestsInOrder.front() == &payload
&& receivedResponses.count(&payload)));
tlm_phase TPhase = phase;
tlm::tlm_phase TPhase = phase;
sc_time TDelay = delay;
tSocket->nb_transport_bw(payload, TPhase, TDelay);
}
@@ -146,9 +145,9 @@ private:
//has been received
if (!responseIsPendingInInitator
&& receivedResponses.count(pendingRequestsInOrder.front())) {
tlm_generic_payload *payloadToSend = pendingRequestsInOrder.front();
tlm::tlm_generic_payload *payloadToSend = pendingRequestsInOrder.front();
responseIsPendingInInitator = true;
sendToInitiator(*payloadToSend, BEGIN_RESP, SC_ZERO_TIME);
sendToInitiator(*payloadToSend, tlm::BEGIN_RESP, SC_ZERO_TIME);
}
// else if(!responseIsPendingInInitator && receivedResponses.size()>0 && !receivedResponses.count(pendingRequestsInOrder.front())>0)
// {

18
DRAMSys/library/src/simulation/SimpleArbiter.h
View File

@@ -41,8 +41,6 @@
#include "../common/XmlAddressDecoder.h"
#include "../common/dramExtensions.h"
using namespace tlm;
// Annotated References [X,Y] --> Please refer to TLM AT Cheat Sheet on README
struct SimpleArbiter: public IArbiter {
@@ -70,8 +68,8 @@ protected:
TlmRecorder *tlmRecorder;
// Initiated by initiator side
// This function is called when an arbiter's target socket receives a transaction from a device
virtual tlm_sync_enum nb_transport_fw(int id, tlm_generic_payload &payload,
tlm_phase &phase, sc_time &fwDelay)
virtual tlm::tlm_sync_enum nb_transport_fw(int id, tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &fwDelay)
{
if (phase == BEGIN_REQ) {
payload.acquire();
@@ -98,13 +96,13 @@ protected:
// 4-Phase Handshake [1.1]
// 4-Phase Handshake [1.7]
return TLM_ACCEPTED;
return tlm::TLM_ACCEPTED;
}
// Initiated by dram side
// This function is called when an arbiter's initiator socket receives a transaction from a memory controller
virtual tlm_sync_enum nb_transport_bw(int /*channelId*/,
tlm_generic_payload &payload, tlm_phase &phase, sc_time &bwDelay)
virtual tlm::tlm_sync_enum nb_transport_bw(int /*channelId*/,
tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_time &bwDelay)
{
tlmRecorder->recordPhase(payload, phase, bwDelay + sc_time_stamp());
@@ -115,10 +113,10 @@ protected:
// Early Completion [3.1]
tlmRecorder->recordPhase(payload, END_RESP, bwDelay + sc_time_stamp());
tlmRecorder->recordArbiterPhase(payload, BEGIN_RESP, sc_time_stamp() + bwDelay);
return TLM_COMPLETED;
return tlm::TLM_COMPLETED;
}
// 4-Phase Handshake [1.3]
return TLM_ACCEPTED;
return tlm::TLM_ACCEPTED;
}
virtual unsigned int transport_dbg(int /*id*/, tlm::tlm_generic_payload &trans)
@@ -130,7 +128,7 @@ protected:
return iSocket[getISocketIndex(trans)]->transport_dbg(trans);
}
virtual unsigned int getISocketIndex(tlm_generic_payload &payload)
virtual unsigned int getISocketIndex(tlm::tlm_generic_payload &payload)
{
return DramExtension::getBank(payload).ID();
}

18
DRAMSys/library/src/simulation/StlPlayer.h
View File

@@ -43,8 +43,6 @@
#include "../common/XmlAddressDecoder.h"
#include "TracePlayer.h"
using namespace tlm;
template<bool relative>
class StlPlayer : public TracePlayer
{
@@ -113,11 +111,11 @@ public:
SC_REPORT_FATAL("StlPlayer",
("Malformed trace file. Command could not be found (line " + std::to_string(
lineCnt) + ").").c_str());
enum tlm_command cmd;
enum tlm::tlm_command cmd;
if (command == "read") {
cmd = TLM_READ_COMMAND;
cmd = tlm::TLM_READ_COMMAND;
} else if (command == "write") {
cmd = TLM_WRITE_COMMAND;
cmd = tlm::TLM_WRITE_COMMAND;
} else {
SC_REPORT_FATAL("StlPlayer",
(std::string("Corrupted tracefile, command ") + command +
@@ -133,7 +131,7 @@ public:
unsigned long long addr = std::stoull(address.c_str(), 0, 16);
// Get the data if necessary.
if (storageEnabled && cmd == TLM_WRITE_COMMAND)
if (storageEnabled && cmd == tlm::TLM_WRITE_COMMAND)
{
// The input trace file must provide the data to be stored into the memory.
iss >> dataStr;
@@ -155,7 +153,7 @@ public:
// Fill up the payload.
payload->set_address(addr);
payload->set_response_status(TLM_INCOMPLETE_RESPONSE);
payload->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
payload->set_dmi_allowed(false);
payload->set_byte_enable_length(0);
payload->set_streaming_width(burstlength);
@@ -167,13 +165,13 @@ public:
{
// Send the transaction directly or schedule it to be sent in the future.
if (sendingTime <= sc_time_stamp())
this->payloadEventQueue.notify(*payload, BEGIN_REQ, SC_ZERO_TIME);
this->payloadEventQueue.notify(*payload, tlm::BEGIN_REQ, SC_ZERO_TIME);
else
this->payloadEventQueue.notify(*payload, BEGIN_REQ,
this->payloadEventQueue.notify(*payload, tlm::BEGIN_REQ,
sendingTime - sc_time_stamp());
}
else
payloadEventQueue.notify(*payload, BEGIN_REQ, sendingTime);
payloadEventQueue.notify(*payload, tlm::BEGIN_REQ, sendingTime);
}
private:

8
DRAMSys/library/src/simulation/TraceGenerator.h
View File

@@ -40,8 +40,6 @@
#include "TracePlayer.h"
using namespace tlm;
struct TraceGenerator : public TracePlayer
{
public:
@@ -68,15 +66,15 @@ public:
char[16]; // TODO: column / burst breite
payload->set_address(0x0);
payload->set_response_status(TLM_INCOMPLETE_RESPONSE);
payload->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
payload->set_dmi_allowed(false);
payload->set_byte_enable_length(0);
payload->set_streaming_width(this->burstlenght);
payload->set_data_ptr(dataElement);
payload->set_data_length(16);
payload->set_command(TLM_READ_COMMAND);
payload->set_command(tlm::TLM_READ_COMMAND);
transCounter++;
this->payloadEventQueue.notify(*payload, BEGIN_REQ, SC_ZERO_TIME);
this->payloadEventQueue.notify(*payload, tlm::BEGIN_REQ, SC_ZERO_TIME);
}
private:

2
DRAMSys/library/src/simulation/TracePlayer.cpp
View File

@@ -38,6 +38,8 @@
#include "TracePlayer.h"
using namespace tlm;
TracePlayer::TracePlayer(sc_module_name name, TracePlayerListener *listener) :
sc_module(name),
payloadEventQueue(this, &TracePlayer::peqCallback),

8
DRAMSys/library/src/simulation/TracePlayer.h
View File

@@ -52,8 +52,6 @@
#include "../common/XmlAddressDecoder.h"
#include "TracePlayerListener.h"
using namespace tlm;
struct TracePlayer : public sc_module
{
public:
@@ -72,10 +70,10 @@ protected:
bool storageEnabled;
private:
tlm_sync_enum nb_transport_bw(tlm_generic_payload &payload, tlm_phase &phase,
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase,
sc_time &bwDelay);
void peqCallback(tlm_generic_payload &payload, const tlm_phase &phase);
void sendToTarget(tlm_generic_payload &payload, const tlm_phase &phase,
void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase);
void sendToTarget(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase,
const sc_time &delay);
MemoryManager memoryManager;
unsigned int transactionsSent = 0;

9
DRAMSys/library/src/simulation/dram/Dram.h
View File

@@ -47,9 +47,6 @@
#include "../../configuration/memspec/MemSpec.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
using namespace tlm;
using namespace DRAMPower;
class Dram : public sc_module
{
private:
@@ -68,10 +65,10 @@ protected:
libDRAMPower *DRAMPower;
virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload,
tlm_phase &phase, sc_time &delay);
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &delay);
virtual unsigned int transport_dbg(tlm_generic_payload &trans);
virtual unsigned int transport_dbg(tlm::tlm_generic_payload &trans);
public:
tlm_utils::simple_target_socket<Dram> tSocket;

2
DRAMSys/library/src/simulation/dram/DramDDR3.cpp
View File

@@ -40,6 +40,8 @@
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecDDR3.h"
using namespace DRAMPower;
DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
{
if (storeMode == StorageMode::ErrorModel)

2
DRAMSys/library/src/simulation/dram/DramDDR4.cpp
View File

@@ -40,6 +40,8 @@
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecDDR4.h"
using namespace DRAMPower;
DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
{
if (storeMode == StorageMode::ErrorModel)

8
DRAMSys/library/src/simulation/dram/DramRecordable.h
View File

@@ -42,8 +42,6 @@
#include "../../configuration/Configuration.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
using namespace tlm;
template<class BaseDram>
class DramRecordable final : public BaseDram
{
@@ -53,10 +51,10 @@ public:
~DramRecordable();
private:
virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload,
tlm_phase &phase, sc_time &delay) override;
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &delay) override;
void recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay);
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay);
TlmRecorder *tlmRecorder;

1
DRAMSys/library/src/simulation/dram/DramWideIO.cpp
View File

@@ -44,6 +44,7 @@
#include "../../configuration/memspec/MemSpecWideIO.h"
using namespace tlm;
using namespace DRAMPower;
DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
{

6
DRAMSys/library/src/simulation/dram/DramWideIO.h
View File

@@ -41,8 +41,6 @@
#include "Dram.h"
#include "../../error/errormodel.h"
using namespace tlm;
class DramWideIO : public Dram
{
public:
@@ -51,8 +49,8 @@ public:
virtual ~DramWideIO();
protected:
virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload,
tlm_phase &phase, sc_time &delay) override;
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &delay) override;
private:
std::vector<errorModel *> ememory;