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Added passing filters to select LPDDR5 burstLength dependent dependencies.

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This commit is contained in:
Iron Prando da Silva
2022-05-10 10:44:09 +02:00
parent 1fc4b238fe
commit 28a4f8a586
6 changed files with 135 additions and 111 deletions
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11
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h
View File

@@ -36,20 +36,27 @@
#pragma once
#include <QString>
#include <memory>
#include "StringMapper.h"
class DBPhaseEntryBase;
typedef bool (*PassFunction)(const DBPhaseEntryBase* thisPhase, const std::shared_ptr<DBPhaseEntryBase>& otherPhase);
#define PASSFUNCTIONDECL [](const DBPhaseEntryBase* thisPhase, const std::shared_ptr<DBPhaseEntryBase>& otherPhase)
class TimeDependency {
public:
TimeDependency() = default;
TimeDependency(size_t timeValue, QString phaseDep, DependencyType depType,
QString timeDepName)
QString timeDepName, PassFunction pass=nullptr)
: timeValue{timeValue}, phaseDep{phaseDep}, depType{depType},
timeDepName{timeDepName} {}
timeDepName{timeDepName}, passFunction{pass} {}
size_t timeValue;
StringMapper phaseDep;
DependencyType depType;
QString timeDepName;
PassFunction passFunction;
bool isPool() { return phaseDep.isPool(); }
};

2
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.cpp
View File

@@ -42,7 +42,7 @@ LPDDR5Configuration::LPDDR5Configuration(const TraceDB& tdb) {
}
QString LPDDR5Configuration::getQueryStr(const std::vector<QString>& commands) const {
QString queryStr = "SELECT Phases.*, Transactions.TBank, Transactions.TBankgroup, Transactions.TRank "
QString queryStr = "SELECT Phases.*, Transactions.TBank, Transactions.TBankgroup, Transactions.TRank, Transactions.BurstLength "
" FROM Phases "
" INNER JOIN Transactions "
" ON Phases.Transact=Transactions.ID "

4
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp
View File

@@ -44,12 +44,16 @@ LPDDR5DBPhaseEntry::LPDDR5DBPhaseEntry(const QSqlQuery& query) {
tBank = query.value(5).toLongLong();
tBankgroup = query.value(6).toLongLong();
tRank = query.value(7).toLongLong();
tBurstLength = query.value(8).toLongLong();
}
bool LPDDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const {
auto other = std::dynamic_pointer_cast<LPDDR5DBPhaseEntry>(otherPhase);
if (!other) return false;
if (dep.passFunction && !dep.passFunction(this, other)) return false;
bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS;
bool thisIsREFP2B = phaseName == StringMapper::Identifier::REFP2B;
bool otherIsREFP2B = dep.phaseDep == StringMapper::Identifier::REFP2B;

1
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h
View File

@@ -43,6 +43,7 @@ class LPDDR5DBPhaseEntry : public DBPhaseEntryBase {
size_t tBankgroup;
size_t tRank;
size_t tBurstLength;
size_t bankOffsetREFP2B;
bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const override;

227
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp
View File

@@ -142,6 +142,17 @@ const std::vector<QString> TimeDependenciesInfoLPDDR5::getPossiblePhases() {
DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
DependencyMap dmap;
auto passBurstLength16 = PASSFUNCTIONDECL {
auto other = std::dynamic_pointer_cast<LPDDR5DBPhaseEntry>(otherPhase);
if (!other) return false;
return other->tBurstLength == 16;
};
auto passBurstLength32 = PASSFUNCTIONDECL {
auto other = std::dynamic_pointer_cast<LPDDR5DBPhaseEntry>(otherPhase);
if (!other) return false;
return other->tBurstLength == 32;
};
dmap.emplace(
piecewise_construct,
forward_as_tuple("ACT"),
@@ -149,10 +160,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
initializer_list<TimeDependency>{
{tRCpb, "ACT", DependencyType::IntraBank, "tRCpb"},
{tRRD, "ACT", DependencyType::IntraRank, "tRRD"},
{BL_n_min_16 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb - tCK"},
{BL_n_min_32 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb - tCK"},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK"},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK"},
{BL_n_min_16 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb - tCK", passBurstLength16},
{BL_n_min_32 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb - tCK", passBurstLength32},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK", passBurstLength16},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK", passBurstLength32},
{tRPpb - tCK, "PREPB", DependencyType::IntraBank, "tRPpb - tCK"},
{tRPab - tCK, "PREAB", DependencyType::IntraRank, "tRPab - tCK"},
{tRFCab - tCK, "REFAB", DependencyType::IntraRank, "tRFCab - tCK"},
@@ -172,26 +183,26 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
{BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS"},
{BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS"},
{tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
{tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
{tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
{tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
{tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
{tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
{tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
{tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
{BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16},
{tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32},
{tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16},
{tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32},
{tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16},
{tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32},
{tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16},
{tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
@@ -203,26 +214,26 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
{BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS"},
{BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32},
{BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
@@ -234,10 +245,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRAS + tCK, "ACT", DependencyType::IntraBank, "tRAS + tCK"},
{BL_n_min_16 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_16 + tRBTP"},
{BL_n_min_32 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_32 + tRBTP"},
{tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR"},
{tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR"},
{BL_n_min_16 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_16 + tRBTP", passBurstLength16},
{BL_n_min_32 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_32 + tRBTP", passBurstLength32},
{tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16},
{tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32},
{tPPD, "PREPB", DependencyType::IntraRank, "tPPD"},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
@@ -250,26 +261,26 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
{BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS"},
{BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS"},
{tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
{tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
{tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
{tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
{tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
{tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
{tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
{tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
{BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16},
{tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32},
{tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16},
{tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32},
{tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L", passBurstLength16},
{tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L", passBurstLength32},
{tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S", passBurstLength16},
{tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S", passBurstLength32},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
@@ -281,26 +292,26 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
{BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS"},
{BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16"},
{BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32"},
{BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16"},
{BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32"},
{tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS"},
{tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS"},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32},
{tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL", passBurstLength32},
{tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL", passBurstLength16},
{tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL", passBurstLength32},
{BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16", passBurstLength16},
{BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32", passBurstLength32},
{BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16", passBurstLength16},
{BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32", passBurstLength32},
{tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS", passBurstLength16},
{tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS", passBurstLength32},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
)
@@ -312,10 +323,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRCpb + tCK, "ACT", DependencyType::IntraRank, "tRCpb + tCK"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP + tRPpb"},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP + tRPpb"},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32},
{tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"},
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
{tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"},
@@ -330,14 +341,14 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
forward_as_tuple(
initializer_list<TimeDependency>{
{tRAS + tCK, "ACT", DependencyType::IntraRank, "tRAS + tCK"},
{BL_n_min_16 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_16 + tRBTP"},
{BL_n_min_32 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_32 + tRBTP"},
{BL_n_min_16 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP"},
{BL_n_min_32 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP"},
{tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR"},
{tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR"},
{tWL + BL_n_min_16 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR"},
{tWL + BL_n_min_32 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR"},
{BL_n_min_16 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_16 + tRBTP", passBurstLength16},
{BL_n_min_32 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_32 + tRBTP", passBurstLength32},
{BL_n_min_16 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP", passBurstLength16},
{BL_n_min_32 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP", passBurstLength32},
{tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16},
{tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32},
{tWL + BL_n_min_16 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR", passBurstLength16},
{tWL + BL_n_min_32 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR", passBurstLength32},
{tPPD, "PREPB", DependencyType::IntraRank, "tPPD"},
{0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
}
@@ -351,10 +362,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
initializer_list<TimeDependency>{
{tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"},
{tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb"},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb"},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32},
{tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"},
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
{tRFCpb, "REFPB", DependencyType::IntraBank, "tRFCpb"},
@@ -372,10 +383,10 @@ DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
initializer_list<TimeDependency>{
{tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"},
{tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb"},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb"},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"},
{BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb", passBurstLength16},
{BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb", passBurstLength32},
{tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb", passBurstLength16},
{tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb", passBurstLength32},
{tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"},
{tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
{tRFCpb, "REFP2B", DependencyType::IntraBank, "tRFCpb"},

1
DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h
View File

@@ -36,6 +36,7 @@
#pragma once
#include "../dramtimedependenciesbase.h"
#include "businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h"
class TimeDependenciesInfoLPDDR5 final : public DRAMTimeDependenciesBase {
public: