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Removed sending of END_CMD phases in DRAM.

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This commit is contained in:
Lukas Steiner
2020-03-31 16:50:18 +02:00
parent e17a1b416e
commit 1b10c9ae02
9 changed files with 93 additions and 131 deletions
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48
DRAMSys/library/src/common/protocol.h
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@@ -39,31 +39,31 @@
#define PROTOCOL_H
// DO NOT CHANGE THE ORDER!
DECLARE_EXTENDED_PHASE(BEGIN_RD);
DECLARE_EXTENDED_PHASE(BEGIN_WR);
DECLARE_EXTENDED_PHASE(BEGIN_RDA);
DECLARE_EXTENDED_PHASE(BEGIN_WRA);
DECLARE_EXTENDED_PHASE(BEGIN_PRE);
DECLARE_EXTENDED_PHASE(BEGIN_ACT);
DECLARE_EXTENDED_PHASE(BEGIN_REFB);
DECLARE_EXTENDED_PHASE(BEGIN_PREA);
DECLARE_EXTENDED_PHASE(BEGIN_REFA);
DECLARE_EXTENDED_PHASE(BEGIN_PDNA);
DECLARE_EXTENDED_PHASE(END_PDNA);
DECLARE_EXTENDED_PHASE(BEGIN_PDNP);
DECLARE_EXTENDED_PHASE(END_PDNP);
DECLARE_EXTENDED_PHASE(BEGIN_SREF);
DECLARE_EXTENDED_PHASE(END_SREF);
DECLARE_EXTENDED_PHASE(BEGIN_RD); // 5
DECLARE_EXTENDED_PHASE(BEGIN_WR); // 6
DECLARE_EXTENDED_PHASE(BEGIN_RDA); // 7
DECLARE_EXTENDED_PHASE(BEGIN_WRA); // 8
DECLARE_EXTENDED_PHASE(BEGIN_PRE); // 9
DECLARE_EXTENDED_PHASE(BEGIN_ACT); // 10
DECLARE_EXTENDED_PHASE(BEGIN_REFB); // 11
DECLARE_EXTENDED_PHASE(BEGIN_PREA); // 12
DECLARE_EXTENDED_PHASE(BEGIN_REFA); // 13
DECLARE_EXTENDED_PHASE(BEGIN_PDNA); // 14
DECLARE_EXTENDED_PHASE(END_PDNA); // 15
DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 16
DECLARE_EXTENDED_PHASE(END_PDNP); // 17
DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 18
DECLARE_EXTENDED_PHASE(END_SREF); // 19
DECLARE_EXTENDED_PHASE(END_RD);
DECLARE_EXTENDED_PHASE(END_WR);
DECLARE_EXTENDED_PHASE(END_RDA);
DECLARE_EXTENDED_PHASE(END_WRA);
DECLARE_EXTENDED_PHASE(END_PRE);
DECLARE_EXTENDED_PHASE(END_ACT);
DECLARE_EXTENDED_PHASE(END_REFB);
DECLARE_EXTENDED_PHASE(END_PREA);
DECLARE_EXTENDED_PHASE(END_REFA);
DECLARE_EXTENDED_PHASE(END_RD); // 20
DECLARE_EXTENDED_PHASE(END_WR); // 21
DECLARE_EXTENDED_PHASE(END_RDA); // 22
DECLARE_EXTENDED_PHASE(END_WRA); // 23
DECLARE_EXTENDED_PHASE(END_PRE); // 24
DECLARE_EXTENDED_PHASE(END_ACT); // 25
DECLARE_EXTENDED_PHASE(END_REFB); // 26
DECLARE_EXTENDED_PHASE(END_PREA); // 27
DECLARE_EXTENDED_PHASE(END_REFA); // 28
#endif // PROTOCOL_H

33
DRAMSys/library/src/controller/Command.cpp
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@@ -90,6 +90,39 @@ tlm_phase commandToPhase(Command command)
return phaseOfCommand[command];
}
Command phaseToCommand(tlm_phase phase)
{
assert(phase >= 5 && phase <= 19);
static std::array<Command, 16> commandOfPhase =
{Command::RD,
Command::WR,
Command::RDA,
Command::WRA,
Command::PRE,
Command::ACT,
Command::REFB,
Command::PREA,
Command::REFA,
Command::PDEA,
Command::PDXA,
Command::PDEP,
Command::PDXP,
Command::SREFEN,
Command::SREFEX};
return commandOfPhase[phase - 5];
}
bool phaseNeedsEnd(tlm_phase phase)
{
return (phase >= 5 && phase <= 13);
}
tlm_phase getEndPhase(tlm_phase phase)
{
assert(phase >= 5 && phase <= 13);
return (phase + 15);
}
bool isBankCommand(Command command)
{
assert(command >= 0 && command <= 15);

3
DRAMSys/library/src/controller/Command.h
View File

@@ -66,6 +66,9 @@ enum Command
std::string commandToString(Command);
tlm_phase commandToPhase(Command);
Command phaseToCommand(tlm_phase);
bool phaseNeedsEnd(tlm_phase);
tlm_phase getEndPhase(tlm_phase);
unsigned numberOfCommands();
bool isBankCommand(Command);
bool isRankCommand(Command);

8
DRAMSys/library/src/controller/Controller.cpp
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@@ -373,7 +373,7 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans,
endRespEvent.notify(notificationDelay);
}
else
SC_REPORT_FATAL(0, "nb_transport_fw in controller was triggered with unknown phase");
SC_REPORT_FATAL("Controller", "nb_transport_fw in controller was triggered with unknown phase");
PRINTDEBUGMESSAGE(name(), "[fw] " + phaseNameToString(phase) + " notification in " +
notificationDelay.to_string());
@@ -382,11 +382,9 @@ tlm_sync_enum Controller::nb_transport_fw(tlm_generic_payload &trans,
}
tlm_sync_enum Controller::nb_transport_bw(tlm_generic_payload &,
tlm_phase &phase, sc_time &delay)
tlm_phase &, sc_time &)
{
PRINTDEBUGMESSAGE(name(), "[bw] " + phaseNameToString(phase) + " notification in " +
delay.to_string());
SC_REPORT_FATAL("Controller", "nb_transport_bw of controller must not be called");
return TLM_ACCEPTED;
}

47
DRAMSys/library/src/simulation/dram/Dram.cpp
View File

@@ -136,7 +136,7 @@ Dram::~Dram()
}
tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
tlm_phase &phase, sc_time &delay)
tlm_phase &phase, sc_time &)
{
unsigned int bank = DramExtension::getExtension(payload).getBank().ID();
@@ -144,21 +144,11 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
unsigned long long cycle = sc_time_stamp() / memSpec->tCK;
if (phase == BEGIN_PRE)
{
DRAMPower->doCommand(MemCommand::PRE, bank, cycle);
sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE, payload));
}
else if (phase == BEGIN_PREA)
{
DRAMPower->doCommand(MemCommand::PREA, bank, cycle);
sendToController(payload, END_PREA,
delay + memSpec->getExecutionTime(Command::PREA, payload));
}
else if (phase == BEGIN_ACT)
{
DRAMPower->doCommand(MemCommand::ACT, bank, cycle);
sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT, payload));
}
else if (phase == BEGIN_WR)
{
DRAMPower->doCommand(MemCommand::WR, bank, cycle);
@@ -168,7 +158,6 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
unsigned char *phyAddr = memory + payload.get_address();
memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length());
}
sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR, payload));
}
else if (phase == BEGIN_RD)
{
@@ -179,7 +168,6 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
unsigned char *phyAddr = memory + payload.get_address();
memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length());
}
sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD, payload));
}
else if (phase == BEGIN_WRA)
{
@@ -190,7 +178,6 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
unsigned char *phyAddr = memory + payload.get_address();
memcpy(phyAddr, payload.get_data_ptr(), payload.get_data_length());
}
sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA, payload));
}
else if (phase == BEGIN_RDA)
{
@@ -201,49 +188,25 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
unsigned char *phyAddr = memory + payload.get_address();
memcpy(payload.get_data_ptr(), phyAddr, payload.get_data_length());
}
sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA, payload));
}
else if (phase == BEGIN_REFA)
{
DRAMPower->doCommand(MemCommand::REF, bank, cycle);
sendToController(payload, END_REFA,
delay + memSpec->getExecutionTime(Command::REFA, payload));
}
else if (phase == BEGIN_REFB)
{
DRAMPower->doCommand(MemCommand::REFB, bank, cycle);
sendToController(payload, END_REFB,
delay + memSpec->getExecutionTime(Command::REFB, payload));
}
// Powerdown phases have to be started and ended by the controller, because they do not have a fixed length
else if (phase == BEGIN_PDNA)
{
DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle);
}
else if (phase == END_PDNA)
{
DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle);
}
else if (phase == BEGIN_PDNP)
{
DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle);
}
else if (phase == END_PDNP)
{
DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle);
}
else if (phase == BEGIN_SREF)
{
DRAMPower->doCommand(MemCommand::SREN, bank, cycle);
}
else if (phase == END_SREF)
{
DRAMPower->doCommand(MemCommand::SREX, bank, cycle);
}
else
{
SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase");
}
return TLM_ACCEPTED;
}
@@ -298,11 +261,3 @@ unsigned int Dram::transport_dbg(tlm_generic_payload &trans)
}
return 0;
}
void Dram::sendToController(tlm_generic_payload &payload, const tlm_phase &phase,
const sc_time &delay)
{
tlm_phase TPhase = phase;
sc_time TDelay = delay;
tSocket->nb_transport_bw(payload, TPhase, TDelay);
}

3
DRAMSys/library/src/simulation/dram/Dram.h
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@@ -74,9 +74,6 @@ protected:
virtual unsigned int transport_dbg(tlm_generic_payload &trans);
void sendToController(tlm_generic_payload &payload, const tlm_phase &phase,
const sc_time &delay);
public:
tlm_utils::simple_target_socket<Dram> tSocket;

38
DRAMSys/library/src/simulation/dram/DramRecordable.cpp
View File

@@ -83,35 +83,43 @@ template<class BaseDram>
tlm_sync_enum DramRecordable<BaseDram>::nb_transport_fw(tlm_generic_payload &payload,
tlm_phase &phase, sc_time &delay)
{
// Recording time used by the traceAnalyzer
recordPhase(payload, phase, delay);
return BaseDram::nb_transport_fw(payload, phase, delay);
}
template<class BaseDram>
void DramRecordable<BaseDram>::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay)
{
sc_time recTime = sc_time_stamp() + delay;
// These are terminating phases recorded by the DRAM. The execution
// time of the related command must be taken into consideration.
if (phase == END_PDNA)
recTime += this->memSpec->getCommandLength(Command::PDXA);
else if (phase == END_PDNP)
recTime += this->memSpec->getCommandLength(Command::PDXP);
else if (phase == END_SREF)
recTime += this->memSpec->getCommandLength(Command::SREFEX);
if (phase == END_PDNA || phase == END_PDNP || phase == END_SREF)
recTime += this->memSpec->getCommandLength(phaseToCommand(phase));
unsigned int thr __attribute__((unused)) = DramExtension::getExtension(payload).getThread().ID();
unsigned int ch __attribute__((unused)) = DramExtension::getExtension(payload).getChannel().ID();
unsigned int bg __attribute__((unused)) = DramExtension::getExtension(payload).getBankGroup().ID();
unsigned int bank __attribute__((unused)) = DramExtension::getExtension(payload).getBank().ID();
unsigned int row __attribute__((unused)) = DramExtension::getExtension(payload).getRow().ID();
unsigned int col __attribute__((unused)) = DramExtension::getExtension(payload).getColumn().ID();
unsigned int thr __attribute__((unused)) = DramExtension::getExtension(trans).getThread().ID();
unsigned int ch __attribute__((unused)) = DramExtension::getExtension(trans).getChannel().ID();
unsigned int bg __attribute__((unused)) = DramExtension::getExtension(trans).getBankGroup().ID();
unsigned int bank __attribute__((unused)) = DramExtension::getExtension(trans).getBank().ID();
unsigned int row __attribute__((unused)) = DramExtension::getExtension(trans).getRow().ID();
unsigned int col __attribute__((unused)) = DramExtension::getExtension(trans).getColumn().ID();
PRINTDEBUGMESSAGE(this->name(), "Recording " + phaseNameToString(phase) + " thread " +
to_string(thr) + " channel " + to_string(ch) + " bank group " + to_string(
bg) + " bank " + to_string(bank) + " row " + to_string(row) + " column " +
to_string(col) + " at " + recTime.to_string());
tlmRecorder->recordPhase(payload, phase, recTime);
tlmRecorder->recordPhase(trans, phase, recTime);
if (phaseNeedsEnd(phase))
{
recTime += this->memSpec->getExecutionTime(phaseToCommand(phase), trans);
tlmRecorder->recordPhase(trans, getEndPhase(phase), recTime);
}
return BaseDram::nb_transport_fw(payload, phase, delay);
}
// This Thread is only triggered when Power Simulation is enabled.
// It estimates the current average power which will be stored in the trace database for visualization purposes.
template<class BaseDram>

3
DRAMSys/library/src/simulation/dram/DramRecordable.h
View File

@@ -55,6 +55,9 @@ public:
private:
virtual tlm_sync_enum nb_transport_fw(tlm_generic_payload &payload,
tlm_phase &phase, sc_time &delay) override;
void recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay);
TlmRecorder *tlmRecorder;
libDRAMPower *DRAMPower;

41
DRAMSys/library/src/simulation/dram/DramWideIO.cpp
View File

@@ -171,7 +171,7 @@ DramWideIO::~DramWideIO()
}
tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
tlm_phase &phase, sc_time &delay)
tlm_phase &phase, sc_time &)
{
unsigned int bank = DramExtension::getExtension(payload).getBank().ID();
@@ -179,24 +179,15 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
unsigned long long cycle = sc_time_stamp() / memSpec->tCK;
if (phase == BEGIN_PRE)
{
DRAMPower->doCommand(MemCommand::PRE, bank, cycle);
sendToController(payload, END_PRE, delay + memSpec->getExecutionTime(Command::PRE, payload));
}
else if (phase == BEGIN_PREA)
{
DRAMPower->doCommand(MemCommand::PREA, bank, cycle);
sendToController(payload, END_PREA,
delay + memSpec->getExecutionTime(Command::PREA, payload));
}
else if (phase == BEGIN_ACT)
{
DRAMPower->doCommand(MemCommand::ACT, bank, cycle);
sendToController(payload, END_ACT, delay + memSpec->getExecutionTime(Command::ACT, payload));
unsigned int row = DramExtension::getExtension(payload).getRow().ID();
if (storeMode == StorageMode::ErrorModel)
ememory[bank]->activate(row);
ememory[bank]->activate(DramExtension::getExtension(payload).getRow().ID());
}
else if (phase == BEGIN_WR)
{
@@ -211,7 +202,6 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
{
ememory[bank]->store(payload);
}
sendToController(payload, END_WR, delay + memSpec->getExecutionTime(Command::WR, payload));
}
else if (phase == BEGIN_RD)
{
@@ -226,7 +216,6 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
{
ememory[bank]->load(payload);
}
sendToController(payload, END_RD, delay + memSpec->getExecutionTime(Command::RD, payload));
}
else if (phase == BEGIN_WRA)
{
@@ -241,7 +230,6 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
{
ememory[bank]->store(payload);
}
sendToController(payload, END_WRA, delay + memSpec->getExecutionTime(Command::WRA, payload));
}
else if (phase == BEGIN_RDA)
{
@@ -256,53 +244,30 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
{
ememory[bank]->load(payload);
}
sendToController(payload, END_RDA, delay + memSpec->getExecutionTime(Command::RDA, payload));
}
else if (phase == BEGIN_REFA)
{
DRAMPower->doCommand(MemCommand::REF, bank, cycle);
sendToController(payload, END_REFA,
delay + memSpec->getExecutionTime(Command::REFA, payload));
unsigned int row = DramExtension::getExtension(payload).getRow().ID();
if (storeMode == StorageMode::ErrorModel)
ememory[bank]->refresh(row);
ememory[bank]->refresh(DramExtension::getExtension(payload).getRow().ID());
}
else if (phase == BEGIN_REFB)
{
DRAMPower->doCommand(MemCommand::REFB, bank, cycle);
sendToController(payload, END_REFB,
delay + memSpec->getExecutionTime(Command::REFA, payload));
}
// Powerdown phases have to be started and ended by the controller, because they do not have a fixed length
else if (phase == BEGIN_PDNA)
{
DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle);
}
else if (phase == END_PDNA)
{
DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle);
}
else if (phase == BEGIN_PDNP)
{
DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle);
}
else if (phase == END_PDNP)
{
DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle);
}
else if (phase == BEGIN_SREF)
{
DRAMPower->doCommand(MemCommand::SREN, bank, cycle);
}
else if (phase == END_SREF)
{
DRAMPower->doCommand(MemCommand::SREX, bank, cycle);
}
else
{
SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase");
}
return TLM_ACCEPTED;
}