derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

memory specification config using json file

Browse Source
This commit is contained in:
scorrea
2020-04-28 16:15:42 +02:00
parent 6bfb8ab959
commit 1a1e8d34ee
23 changed files with 517 additions and 496 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
DRAMSys/library/resources/configs/amconfigs/congen_extended.xml
View File

@@ -1,7 +1,7 @@
<?xml version="1.0" ?>
<CONGEN>
<SOLUTION ID="0">
<XOR FIRST="13" SECOND="16"/>
<XOR FIRST="13" SECOND="16"/>
<BYTE_BIT>0</BYTE_BIT>
<BYTE_BIT>1</BYTE_BIT>
<BYTE_BIT>2</BYTE_BIT>
@@ -33,4 +33,4 @@
<ROW_BIT>28</ROW_BIT>
<ROW_BIT>29</ROW_BIT>
</SOLUTION>
</CONGEN>
</CONGEN>

20
DRAMSys/library/resources/configs/mcconfigs/fifo.xml
View File

@@ -1,20 +0,0 @@
<mcconfig>
<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
<PagePolicy value="Open" />
<!-- Fifo, FrFcfs, FrFcfsGrp -->
<Scheduler value="Fifo" />
<RequestBufferSize value="8" />
<!-- Oldest, Strict -->
<CmdMux value="Strict" />
<!-- Fifo, Reorder -->
<RespQueue value="Fifo" />
<!-- NoRefresh, Rankwise, Bankwise -->
<RefreshPolicy value="Rankwise" />
<!-- 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<RefreshMode value="1" />
<RefreshMaxPostponed value="8"/>
<RefreshMaxPulledin value="8"/>
<!-- NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownPolicy value="NoPowerDown" />
<PowerDownTimeout value="100" />
</mcconfig>

20
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.xml
View File

@@ -1,20 +0,0 @@
<mcconfig>
<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
<PagePolicy value="Open" />
<!-- Fifo, FrFcfs, FrFcfsGrp -->
<Scheduler value="FrFcfs" />
<RequestBufferSize value="8" />
<!-- Oldest, Strict -->
<CmdMux value="Oldest" />
<!-- Fifo, Reorder -->
<RespQueue value="Fifo" />
<!-- NoRefresh, Rankwise, Bankwise -->
<RefreshPolicy value="Rankwise" />
<!-- 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<RefreshMode value="1" />
<RefreshMaxPostponed value="8"/>
<RefreshMaxPulledin value="8"/>
<!-- NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownPolicy value="NoPowerDown" />
<PowerDownTimeout value="100" />
</mcconfig>

20
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_grp.xml
View File

@@ -1,20 +0,0 @@
<mcconfig>
<!-- Open, OpenAdaptive, Closed, ClosedAdaptive -->
<PagePolicy value="Open" />
<!-- Fifo, FrFcfs, FrFcfsGrp -->
<Scheduler value="FrFcfsGrp" />
<RequestBufferSize value="8" />
<!-- Oldest, Strict -->
<CmdMux value="Oldest" />
<!-- Fifo, Reorder -->
<RespQueue value="Fifo" />
<!-- NoRefresh, Rankwise, Bankwise -->
<RefreshPolicy value="Rankwise" />
<!-- 1: 1X, 2: 2X, 4: 4X (e.g., DDR4) -->
<RefreshMode value="1" />
<RefreshMaxPostponed value="8"/>
<RefreshMaxPulledin value="8"/>
<!-- NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownPolicy value="NoPowerDown" />
<PowerDownTimeout value="100" />
</mcconfig>

1
DRAMSys/library/resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json Normal file
View File

@@ -0,0 +1 @@
{"memspec": {"parameter": [{"@id": "memoryId", "@type": "string", "@value": "JEDEC_256Mb_WIDEIO_SDR-200_128bit"}, {"@id": "memoryType", "@type": "string", "@value": "WIDEIO_SDR"}], "memarchitecturespec": {"parameter": [{"@id": "width", "@type": "uint", "@value": "128"}, {"@id": "nbrOfBanks", "@type": "uint", "@value": "4"}, {"@id": "nbrOfRanks", "@type": "uint", "@value": "1"}, {"@id": "nbrOfColumns", "@type": "uint", "@value": "128"}, {"@id": "nbrOfRows", "@type": "uint", "@value": "4096"}, {"@id": "dataRate", "@type": "uint", "@value": "1"}, {"@id": "burstLength", "@type": "uint", "@value": "4"}]}, "memtimingspec": {"parameter": [{"@id": "clkMhz", "@type": "double", "@value": "200"}, {"@id": "RC", "@type": "uint", "@value": "12"}, {"@id": "RCD", "@type": "uint", "@value": "4"}, {"@id": "RL", "@type": "uint", "@value": "3"}, {"@id": "RP", "@type": "uint", "@value": "4"}, {"@id": "RFC", "@type": "uint", "@value": "18"}, {"@id": "RAS", "@type": "uint", "@value": "9"}, {"@id": "WL", "@type": "uint", "@value": "1"}, {"@id": "DQSCK", "@type": "uint", "@value": "1"}, {"@id": "AC", "@type": "uint", "@value": "1"}, {"@id": "WR", "@type": "uint", "@value": "3"}, {"@id": "XP", "@type": "uint", "@value": "2"}, {"@id": "XS", "@type": "uint", "@value": "20"}, {"@id": "REFI", "@type": "uint", "@value": "3120"}, {"@id": "TAW", "@type": "uint", "@value": "10"}, {"@id": "RRD", "@type": "uint", "@value": "2"}, {"@id": "CCD_R", "@type": "uint", "@value": "2"}, {"@id": "CCD_W", "@type": "uint", "@value": "1"}, {"@id": "WTR", "@type": "uint", "@value": "3"}, {"@id": "CKE", "@type": "uint", "@value": "3"}, {"@id": "CKESR", "@type": "uint", "@value": "3"}]}, "mempowerspec": {"parameter": [{"@id": "idd0", "@type": "double", "@value": "5.88"}, {"@id": "idd02", "@type": "double", "@value": "21.18"}, {"@id": "idd2p0", "@type": "double", "@value": "0.05"}, {"@id": "idd2p02", "@type": "double", "@value": "0.17"}, {"@id": "idd2p1", "@type": "double", "@value": "0.05"}, {"@id": "idd2p12", "@type": "double", "@value": "0.17"}, {"@id": "idd2n", "@type": "double", "@value": "0.13"}, {"@id": "idd2n2", "@type": "double", "@value": "4.04"}, {"@id": "idd3p0", "@type": "double", "@value": "0.25"}, {"@id": "idd3p02", "@type": "double", "@value": "1.49"}, {"@id": "idd3p1", "@type": "double", "@value": "0.25"}, {"@id": "idd3p12", "@type": "double", "@value": "1.49"}, {"@id": "idd3n", "@type": "double", "@value": "0.52"}, {"@id": "idd3n2", "@type": "double", "@value": "6.55"}, {"@id": "idd4r", "@type": "double", "@value": "1.41"}, {"@id": "idd4r2", "@type": "double", "@value": "85.73"}, {"@id": "idd4w", "@type": "double", "@value": "1.42"}, {"@id": "idd4w2", "@type": "double", "@value": "60.79"}, {"@id": "idd5", "@type": "double", "@value": "14.43"}, {"@id": "idd52", "@type": "double", "@value": "48.17"}, {"@id": "idd6", "@type": "double", "@value": "0.07"}, {"@id": "idd62", "@type": "double", "@value": "0.27"}, {"@id": "vdd", "@type": "double", "@value": "1.8"}, {"@id": "vdd2", "@type": "double", "@value": "1.2"}]}}}

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json Normal file
View File

@@ -0,0 +1 @@
{"memspec": {"parameter": [{"@id": "memoryId", "@type": "string", "@value": "MICRON_1Gb_DDR3-1066_16bit_G_2s"}, {"@id": "memoryType", "@type": "string", "@value": "DDR3"}], "memarchitecturespec": {"parameter": [{"@id": "width", "@type": "uint", "@value": "16"}, {"@id": "nbrOfBanks", "@type": "uint", "@value": "8"}, {"@id": "nbrOfRanks", "@type": "uint", "@value": "1"}, {"@id": "nbrOfColumns", "@type": "uint", "@value": "1024"}, {"@id": "nbrOfRows", "@type": "uint", "@value": "8192"}, {"@id": "dataRate", "@type": "uint", "@value": "2"}, {"@id": "burstLength", "@type": "uint", "@value": "8"}]}, "memtimingspec": {"parameter": [{"@id": "clkMhz", "@type": "double", "@value": "533"}, {"@id": "RC", "@type": "uint", "@value": "27"}, {"@id": "RCD", "@type": "uint", "@value": "7"}, {"@id": "RL", "@type": "uint", "@value": "7"}, {"@id": "RP", "@type": "uint", "@value": "7"}, {"@id": "RFC", "@type": "uint", "@value": "59"}, {"@id": "RAS", "@type": "uint", "@value": "20"}, {"@id": "WL", "@type": "uint", "@value": "6"}, {"@id": "AL", "@type": "uint", "@value": "0"}, {"@id": "DQSCK", "@type": "uint", "@value": "0"}, {"@id": "RTP", "@type": "uint", "@value": "4"}, {"@id": "WR", "@type": "uint", "@value": "8"}, {"@id": "XP", "@type": "uint", "@value": "4"}, {"@id": "XPDLL", "@type": "uint", "@value": "13"}, {"@id": "XS", "@type": "uint", "@value": "64"}, {"@id": "XSDLL", "@type": "uint", "@value": "512"}, {"@id": "REFI", "@type": "uint", "@value": "4160"}, {"@id": "CL", "@type": "uint", "@value": "7"}, {"@id": "FAW", "@type": "uint", "@value": "27"}, {"@id": "RRD", "@type": "uint", "@value": "6"}, {"@id": "CCD", "@type": "uint", "@value": "4"}, {"@id": "WTR", "@type": "uint", "@value": "4"}, {"@id": "CKE", "@type": "uint", "@value": "3"}, {"@id": "CKESR", "@type": "uint", "@value": "4"}]}, "mempowerspec": {"parameter": [{"@id": "idd0", "@type": "double", "@value": "70.22"}, {"@id": "idd2p0", "@type": "double", "@value": "9.07"}, {"@id": "idd2p1", "@type": "double", "@value": "18.90"}, {"@id": "idd2n", "@type": "double", "@value": "30.95"}, {"@id": "idd3p0", "@type": "double", "@value": "26.0"}, {"@id": "idd3p1", "@type": "double", "@value": "26.0"}, {"@id": "idd3n", "@type": "double", "@value": "39.0"}, {"@id": "idd4w", "@type": "double", "@value": "144.31"}, {"@id": "idd4r", "@type": "double", "@value": "128.59"}, {"@id": "idd5", "@type": "double", "@value": "150.64"}, {"@id": "idd6", "@type": "double", "@value": "6.02"}, {"@id": "vdd", "@type": "double", "@value": "1.5"}]}}}

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json Normal file
View File

@@ -0,0 +1 @@
{"memspec": {"parameter": [{"@id": "memoryId", "@type": "string", "@value": "MICRON_1Gb_DDR3-1066_16bit_G_3s"}, {"@id": "memoryType", "@type": "string", "@value": "DDR3"}], "memarchitecturespec": {"parameter": [{"@id": "width", "@type": "uint", "@value": "16"}, {"@id": "nbrOfBanks", "@type": "uint", "@value": "8"}, {"@id": "nbrOfRanks", "@type": "uint", "@value": "1"}, {"@id": "nbrOfColumns", "@type": "uint", "@value": "1024"}, {"@id": "nbrOfRows", "@type": "uint", "@value": "8192"}, {"@id": "dataRate", "@type": "uint", "@value": "2"}, {"@id": "burstLength", "@type": "uint", "@value": "8"}]}, "memtimingspec": {"parameter": [{"@id": "clkMhz", "@type": "double", "@value": "533"}, {"@id": "RC", "@type": "uint", "@value": "27"}, {"@id": "RCD", "@type": "uint", "@value": "7"}, {"@id": "RL", "@type": "uint", "@value": "7"}, {"@id": "RP", "@type": "uint", "@value": "7"}, {"@id": "RFC", "@type": "uint", "@value": "59"}, {"@id": "RAS", "@type": "uint", "@value": "20"}, {"@id": "WL", "@type": "uint", "@value": "6"}, {"@id": "AL", "@type": "uint", "@value": "0"}, {"@id": "DQSCK", "@type": "uint", "@value": "0"}, {"@id": "RTP", "@type": "uint", "@value": "4"}, {"@id": "WR", "@type": "uint", "@value": "8"}, {"@id": "XP", "@type": "uint", "@value": "4"}, {"@id": "XPDLL", "@type": "uint", "@value": "13"}, {"@id": "XS", "@type": "uint", "@value": "64"}, {"@id": "XSDLL", "@type": "uint", "@value": "512"}, {"@id": "REFI", "@type": "uint", "@value": "4160"}, {"@id": "CL", "@type": "uint", "@value": "7"}, {"@id": "FAW", "@type": "uint", "@value": "27"}, {"@id": "RRD", "@type": "uint", "@value": "6"}, {"@id": "CCD", "@type": "uint", "@value": "4"}, {"@id": "WTR", "@type": "uint", "@value": "4"}, {"@id": "CKE", "@type": "uint", "@value": "3"}, {"@id": "CKESR", "@type": "uint", "@value": "4"}]}, "mempowerspec": {"parameter": [{"@id": "idd0", "@type": "double", "@value": "71.81"}, {"@id": "idd2p0", "@type": "double", "@value": "10.04"}, {"@id": "idd2p1", "@type": "double", "@value": "20.93"}, {"@id": "idd2n", "@type": "double", "@value": "32.3"}, {"@id": "idd3p0", "@type": "double", "@value": "27.33"}, {"@id": "idd3p1", "@type": "double", "@value": "27.33"}, {"@id": "idd3n", "@type": "double", "@value": "41.0"}, {"@id": "idd4w", "@type": "double", "@value": "147.87"}, {"@id": "idd4r", "@type": "double", "@value": "132.39"}, {"@id": "idd5", "@type": "double", "@value": "153.76"}, {"@id": "idd6", "@type": "double", "@value": "6.68"}, {"@id": "vdd", "@type": "double", "@value": "1.5"}]}}}

0
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json Normal file
View File

1
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json Normal file
View File

@@ -0,0 +1 @@
{"memspec": {"parameter": [{"@id": "memoryId", "@type": "string", "@value": "MICRON_1Gb_DDR3-1066_8bit_G_3s"}, {"@id": "memoryType", "@type": "string", "@value": "DDR3"}], "memarchitecturespec": {"parameter": [{"@id": "width", "@type": "uint", "@value": "8"}, {"@id": "nbrOfBanks", "@type": "uint", "@value": "8"}, {"@id": "nbrOfRanks", "@type": "uint", "@value": "1"}, {"@id": "nbrOfColumns", "@type": "uint", "@value": "1024"}, {"@id": "nbrOfRows", "@type": "uint", "@value": "16384"}, {"@id": "dataRate", "@type": "uint", "@value": "2"}, {"@id": "burstLength", "@type": "uint", "@value": "8"}]}, "memtimingspec": {"parameter": [{"@id": "clkMhz", "@type": "double", "@value": "533"}, {"@id": "RC", "@type": "uint", "@value": "27"}, {"@id": "RCD", "@type": "uint", "@value": "7"}, {"@id": "RL", "@type": "uint", "@value": "7"}, {"@id": "RP", "@type": "uint", "@value": "7"}, {"@id": "RFC", "@type": "uint", "@value": "59"}, {"@id": "RAS", "@type": "uint", "@value": "20"}, {"@id": "WL", "@type": "uint", "@value": "6"}, {"@id": "AL", "@type": "uint", "@value": "0"}, {"@id": "DQSCK", "@type": "uint", "@value": "0"}, {"@id": "RTP", "@type": "uint", "@value": "4"}, {"@id": "WR", "@type": "uint", "@value": "8"}, {"@id": "XP", "@type": "uint", "@value": "4"}, {"@id": "XPDLL", "@type": "uint", "@value": "13"}, {"@id": "XS", "@type": "uint", "@value": "64"}, {"@id": "XSDLL", "@type": "uint", "@value": "512"}, {"@id": "REFI", "@type": "uint", "@value": "4160"}, {"@id": "CL", "@type": "uint", "@value": "7"}, {"@id": "FAW", "@type": "uint", "@value": "20"}, {"@id": "RRD", "@type": "uint", "@value": "4"}, {"@id": "CCD", "@type": "uint", "@value": "4"}, {"@id": "WTR", "@type": "uint", "@value": "4"}, {"@id": "CKE", "@type": "uint", "@value": "3"}, {"@id": "CKESR", "@type": "uint", "@value": "4"}]}, "mempowerspec": {"parameter": [{"@id": "idd0", "@type": "double", "@value": "57.45"}, {"@id": "idd2p0", "@type": "double", "@value": "10.04"}, {"@id": "idd2p1", "@type": "double", "@value": "20.93"}, {"@id": "idd2n", "@type": "double", "@value": "32.3"}, {"@id": "idd3p0", "@type": "double", "@value": "27.33"}, {"@id": "idd3p1", "@type": "double", "@value": "27.33"}, {"@id": "idd3n", "@type": "double", "@value": "36.45"}, {"@id": "idd4w", "@type": "double", "@value": "104.67"}, {"@id": "idd4r", "@type": "double", "@value": "99.59"}, {"@id": "idd5", "@type": "double", "@value": "153.76"}, {"@id": "idd6", "@type": "double", "@value": "6.68"}, {"@id": "vdd", "@type": "double", "@value": "1.5"}]}}}

51
DRAMSys/library/resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json Normal file
View File

@@ -0,0 +1,51 @@
{"memspec": {
"memoryId" : "MICRON_1Gb_DDR3-1600_8bit_G",
"memoryType" : "DDR3",
"memarchitecturespec": {
"width": 8,
"nbrOfBanks" : 8,
"nbrOfRanks": 1,
"nbrOfColumns" : 1024,
"nbrOfRows": 16384,
"dataRate": 2,
"burstLength": 8},
"memtimingspec": {
"clkMhz" : 800,
"RC" : 38,
"RCD" : 10,
"RL" : 10,
"RP": 10,
"RFC" : 88,
"RAS": 28,
"WL": 8,
"AL": 0,
"DQSCK": 0,
"RTP": 6,
"WR" : 12,
"XP" : 6,
"XPDLL" : 20,
"XS" : 96,
"XSDLL": 512,
"REFI" : 6240,
"CL" : 10,
"FAW" : 24,
"RRD" : 5,
"CCD" : 4,
"WTR" : 6,
"CKE" : 3,
"CKESR": 4},
"mempowerspec" : {
"idd0" : 70.0,
"idd2p0" : 12.0,
"idd2p1" : 30.0,
"idd2n" : 45.0,
"idd3p0" : 35.0,
"idd3p1" : 35.0,
"idd3n" : 45.0,
"idd4w" : 145.0,
"idd4r" : 140.0,
"idd5" :170.0,
"idd6" : 8.0,
"vdd" :1.5}}
}

1
DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json Normal file
View File

@@ -0,0 +1 @@
{"memspec": {"parameter": [{"@id": "memoryId", "@type": "string", "@value": "MICRON_2Gb_DDR3-1066_8bit_D"}, {"@id": "memoryType", "@type": "string", "@value": "DDR3"}], "memarchitecturespec": {"parameter": [{"@id": "width", "@type": "uint", "@value": "8"}, {"@id": "nbrOfBanks", "@type": "uint", "@value": "8"}, {"@id": "nbrOfRanks", "@type": "uint", "@value": "1"}, {"@id": "nbrOfColumns", "@type": "uint", "@value": "1024"}, {"@id": "nbrOfRows", "@type": "uint", "@value": "32768"}, {"@id": "dataRate", "@type": "uint", "@value": "2"}, {"@id": "burstLength", "@type": "uint", "@value": "8"}]}, "memtimingspec": {"parameter": [{"@id": "clkMhz", "@type": "double", "@value": "533"}, {"@id": "RC", "@type": "uint", "@value": "27"}, {"@id": "RCD", "@type": "uint", "@value": "7"}, {"@id": "RL", "@type": "uint", "@value": "7"}, {"@id": "RP", "@type": "uint", "@value": "7"}, {"@id": "RFC", "@type": "uint", "@value": "86"}, {"@id": "RAS", "@type": "uint", "@value": "20"}, {"@id": "WL", "@type": "uint", "@value": "6"}, {"@id": "AL", "@type": "uint", "@value": "0"}, {"@id": "DQSCK", "@type": "uint", "@value": "0"}, {"@id": "RTP", "@type": "uint", "@value": "4"}, {"@id": "WR", "@type": "uint", "@value": "8"}, {"@id": "XP", "@type": "uint", "@value": "4"}, {"@id": "XPDLL", "@type": "uint", "@value": "13"}, {"@id": "XS", "@type": "uint", "@value": "92"}, {"@id": "XSDLL", "@type": "uint", "@value": "512"}, {"@id": "REFI", "@type": "uint", "@value": "4160"}, {"@id": "CL", "@type": "uint", "@value": "7"}, {"@id": "FAW", "@type": "uint", "@value": "20"}, {"@id": "RRD", "@type": "uint", "@value": "4"}, {"@id": "CCD", "@type": "uint", "@value": "4"}, {"@id": "WTR", "@type": "uint", "@value": "4"}, {"@id": "CKE", "@type": "uint", "@value": "3"}, {"@id": "CKESR", "@type": "uint", "@value": "4"}]}, "mempowerspec": {"parameter": [{"@id": "idd0", "@type": "double", "@value": "75.0"}, {"@id": "idd2p0", "@type": "double", "@value": "12.0"}, {"@id": "idd2p1", "@type": "double", "@value": "25.0"}, {"@id": "idd2n", "@type": "double", "@value": "32.0"}, {"@id": "idd3p0", "@type": "double", "@value": "30.0"}, {"@id": "idd3p1", "@type": "double", "@value": "30.0"}, {"@id": "idd3n", "@type": "double", "@value": "35.0"}, {"@id": "idd4w", "@type": "double", "@value": "145.0"}, {"@id": "idd4r", "@type": "double", "@value": "140.0"}, {"@id": "idd5", "@type": "double", "@value": "190.0"}, {"@id": "idd6", "@type": "double", "@value": "12.0"}, {"@id": "vdd", "@type": "double", "@value": "1.5"}]}}}

1
DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json Normal file
View File

@@ -0,0 +1 @@
{"memspec": {"parameter": [{"@id": "memoryId", "@type": "string", "@value": "MICRON_2Gb_DDR3-1600_16bit_D_2s"}, {"@id": "memoryType", "@type": "string", "@value": "DDR3"}], "memarchitecturespec": {"parameter": [{"@id": "width", "@type": "uint", "@value": "16"}, {"@id": "nbrOfBanks", "@type": "uint", "@value": "8"}, {"@id": "nbrOfRanks", "@type": "uint", "@value": "1"}, {"@id": "nbrOfColumns", "@type": "uint", "@value": "1024"}, {"@id": "nbrOfRows", "@type": "uint", "@value": "16384"}, {"@id": "dataRate", "@type": "uint", "@value": "2"}, {"@id": "burstLength", "@type": "uint", "@value": "8"}]}, "memtimingspec": {"parameter": [{"@id": "clkMhz", "@type": "double", "@value": "800"}, {"@id": "RC", "@type": "uint", "@value": "38"}, {"@id": "RCD", "@type": "uint", "@value": "10"}, {"@id": "RL", "@type": "uint", "@value": "10"}, {"@id": "RP", "@type": "uint", "@value": "10"}, {"@id": "RFC", "@type": "uint", "@value": "128"}, {"@id": "RAS", "@type": "uint", "@value": "28"}, {"@id": "WL", "@type": "uint", "@value": "8"}, {"@id": "AL", "@type": "uint", "@value": "0"}, {"@id": "DQSCK", "@type": "uint", "@value": "0"}, {"@id": "RTP", "@type": "uint", "@value": "6"}, {"@id": "WR", "@type": "uint", "@value": "12"}, {"@id": "XP", "@type": "uint", "@value": "5"}, {"@id": "XPDLL", "@type": "uint", "@value": "20"}, {"@id": "XS", "@type": "uint", "@value": "136"}, {"@id": "XSDLL", "@type": "uint", "@value": "512"}, {"@id": "REFI", "@type": "uint", "@value": "4160"}, {"@id": "CL", "@type": "uint", "@value": "10"}, {"@id": "FAW", "@type": "uint", "@value": "32"}, {"@id": "RRD", "@type": "uint", "@value": "6"}, {"@id": "CCD", "@type": "uint", "@value": "4"}, {"@id": "WTR", "@type": "uint", "@value": "6"}, {"@id": "CKE", "@type": "uint", "@value": "3"}, {"@id": "CKESR", "@type": "uint", "@value": "4"}]}, "mempowerspec": {"parameter": [{"@id": "idd0", "@type": "double", "@value": "102.83"}, {"@id": "idd2p0", "@type": "double", "@value": "8.77"}, {"@id": "idd2p1", "@type": "double", "@value": "29.25"}, {"@id": "idd2n", "@type": "double", "@value": "36.89"}, {"@id": "idd3p0", "@type": "double", "@value": "38.75"}, {"@id": "idd3p1", "@type": "double", "@value": "38.75"}, {"@id": "idd3n", "@type": "double", "@value": "38.75"}, {"@id": "idd4w", "@type": "double", "@value": "260.04"}, {"@id": "idd4r", "@type": "double", "@value": "247.34"}, {"@id": "idd5", "@type": "double", "@value": "202.17"}, {"@id": "idd6", "@type": "double", "@value": "8.67"}, {"@id": "vdd", "@type": "double", "@value": "1.5"}]}}}

1
DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json Normal file
View File

@@ -0,0 +1 @@
{"memspec": {"parameter": [{"@id": "memoryId", "@type": "string", "@value": "MICRON_2Gb_LPDDR-333_16bit_A"}, {"@id": "memoryType", "@type": "string", "@value": "LPDDR"}], "memarchitecturespec": {"parameter": [{"@id": "width", "@type": "uint", "@value": "16"}, {"@id": "nbrOfBanks", "@type": "uint", "@value": "4"}, {"@id": "nbrOfRanks", "@type": "uint", "@value": "1"}, {"@id": "nbrOfColumns", "@type": "uint", "@value": "2048"}, {"@id": "nbrOfRows", "@type": "uint", "@value": "16384"}, {"@id": "dataRate", "@type": "uint", "@value": "2"}, {"@id": "burstLength", "@type": "uint", "@value": "8"}]}, "memtimingspec": {"parameter": [{"@id": "clkMhz", "@type": "double", "@value": "166"}, {"@id": "REFI", "@type": "uint", "@value": "2600"}, {"@id": "RFC", "@type": "uint", "@value": "12"}, {"@id": "RL", "@type": "uint", "@value": "3"}, {"@id": "WL", "@type": "uint", "@value": "3"}, {"@id": "CL", "@type": "uint", "@value": "3"}, {"@id": "AL", "@type": "uint", "@value": "0"}, {"@id": "RP", "@type": "uint", "@value": "3"}, {"@id": "RAS", "@type": "uint", "@value": "7"}, {"@id": "RCD", "@type": "uint", "@value": "3"}, {"@id": "RC", "@type": "uint", "@value": "10"}, {"@id": "RRD", "@type": "uint", "@value": "2"}, {"@id": "RTP", "@type": "uint", "@value": "3"}, {"@id": "WR", "@type": "uint", "@value": "3"}, {"@id": "CCD", "@type": "uint", "@value": "2"}, {"@id": "WTR", "@type": "uint", "@value": "1"}, {"@id": "DQSCK", "@type": "uint", "@value": "1"}, {"@id": "XP", "@type": "uint", "@value": "1"}, {"@id": "XPDLL", "@type": "uint", "@value": "1"}, {"@id": "XS", "@type": "uint", "@value": "19"}, {"@id": "XSDLL", "@type": "uint", "@value": "19"}, {"@id": "CKE", "@type": "uint", "@value": "1"}, {"@id": "CKESR", "@type": "uint", "@value": "2"}]}, "mempowerspec": {"parameter": [{"@id": "idd0", "@type": "double", "@value": "100.0"}, {"@id": "idd2p0", "@type": "double", "@value": "0.6"}, {"@id": "idd2p1", "@type": "double", "@value": "0.6"}, {"@id": "idd2n", "@type": "double", "@value": "15.0"}, {"@id": "idd3p0", "@type": "double", "@value": "3.6"}, {"@id": "idd3p1", "@type": "double", "@value": "3.6"}, {"@id": "idd3n", "@type": "double", "@value": "18.0"}, {"@id": "idd4r", "@type": "double", "@value": "115.0"}, {"@id": "idd4w", "@type": "double", "@value": "115.0"}, {"@id": "idd5", "@type": "double", "@value": "170.0"}, {"@id": "idd6", "@type": "double", "@value": "1.7"}, {"@id": "vdd", "@type": "double", "@value": "1.8"}]}}}

1
DRAMSys/library/resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json Normal file
View File

@@ -0,0 +1 @@
{"memspec": {"parameter": [{"@id": "memoryId", "@type": "string", "@value": "MICRON_2Gb_LPDDR2-1066-S4_16bit_A"}, {"@id": "memoryType", "@type": "string", "@value": "LPDDR2"}], "memarchitecturespec": {"parameter": [{"@id": "width", "@type": "uint", "@value": "16"}, {"@id": "nbrOfBanks", "@type": "uint", "@value": "8"}, {"@id": "nbrOfRanks", "@type": "uint", "@value": "1"}, {"@id": "nbrOfColumns", "@type": "uint", "@value": "1024"}, {"@id": "nbrOfRows", "@type": "uint", "@value": "16384"}, {"@id": "dataRate", "@type": "uint", "@value": "2"}, {"@id": "burstLength", "@type": "uint", "@value": "8"}]}, "memtimingspec": {"parameter": [{"@id": "clkMhz", "@type": "double", "@value": "533"}, {"@id": "REFI", "@type": "uint", "@value": "2080"}, {"@id": "RFC", "@type": "uint", "@value": "70"}, {"@id": "RL", "@type": "uint", "@value": "8"}, {"@id": "WL", "@type": "uint", "@value": "4"}, {"@id": "CL", "@type": "uint", "@value": "8"}, {"@id": "AL", "@type": "uint", "@value": "0"}, {"@id": "RP", "@type": "uint", "@value": "10"}, {"@id": "RAS", "@type": "uint", "@value": "23"}, {"@id": "RCD", "@type": "uint", "@value": "10"}, {"@id": "RC", "@type": "uint", "@value": "32"}, {"@id": "FAW", "@type": "uint", "@value": "27"}, {"@id": "RRD", "@type": "uint", "@value": "6"}, {"@id": "RTP", "@type": "uint", "@value": "4"}, {"@id": "WR", "@type": "uint", "@value": "10"}, {"@id": "CCD", "@type": "uint", "@value": "4"}, {"@id": "WTR", "@type": "uint", "@value": "4"}, {"@id": "DQSCK", "@type": "uint", "@value": "2"}, {"@id": "XP", "@type": "uint", "@value": "4"}, {"@id": "XPDLL", "@type": "uint", "@value": "4"}, {"@id": "XS", "@type": "uint", "@value": "75"}, {"@id": "XSDLL", "@type": "uint", "@value": "75"}, {"@id": "CKE", "@type": "uint", "@value": "3"}, {"@id": "CKESR", "@type": "uint", "@value": "8"}]}, "mempowerspec": {"parameter": [{"@id": "idd0", "@type": "double", "@value": "20.0"}, {"@id": "idd02", "@type": "double", "@value": "71.0"}, {"@id": "idd2p0", "@type": "double", "@value": "0.5"}, {"@id": "idd2p02", "@type": "double", "@value": "1.7"}, {"@id": "idd2p1", "@type": "double", "@value": "0.5"}, {"@id": "idd2p12", "@type": "double", "@value": "1.7"}, {"@id": "idd2n", "@type": "double", "@value": "1.7"}, {"@id": "idd2n2", "@type": "double", "@value": "22.0"}, {"@id": "idd3p0", "@type": "double", "@value": "1.2"}, {"@id": "idd3p02", "@type": "double", "@value": "4.12"}, {"@id": "idd3p1", "@type": "double", "@value": "1.2"}, {"@id": "idd3p12", "@type": "double", "@value": "4.12"}, {"@id": "idd3n", "@type": "double", "@value": "1.2"}, {"@id": "idd3n2", "@type": "double", "@value": "30.0"}, {"@id": "idd4r", "@type": "double", "@value": "5.0"}, {"@id": "idd4r2", "@type": "double", "@value": "226.0"}, {"@id": "idd4w", "@type": "double", "@value": "10.0"}, {"@id": "idd4w2", "@type": "double", "@value": "208.0"}, {"@id": "idd5", "@type": "double", "@value": "15.0"}, {"@id": "idd52", "@type": "double", "@value": "136.0"}, {"@id": "idd6", "@type": "double", "@value": "1.2"}, {"@id": "idd62", "@type": "double", "@value": "2.6"}, {"@id": "vdd", "@type": "double", "@value": "1.8"}, {"@id": "vdd2", "@type": "double", "@value": "1.2"}]}}}

1
DRAMSys/library/resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json Normal file
View File

@@ -0,0 +1 @@
{"memspec": {"parameter": [{"@id": "memoryId", "@type": "string", "@value": "SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit"}, {"@id": "memoryType", "@type": "string", "@value": "DDR3"}], "memarchitecturespec": {"parameter": [{"@id": "width", "@type": "uint", "@value": "16"}, {"@id": "nbrOfBanks", "@type": "uint", "@value": "8"}, {"@id": "nbrOfRanks", "@type": "uint", "@value": "1"}, {"@id": "nbrOfColumns", "@type": "uint", "@value": "1024"}, {"@id": "nbrOfRows", "@type": "uint", "@value": "32768"}, {"@id": "dataRate", "@type": "uint", "@value": "2"}, {"@id": "burstLength", "@type": "uint", "@value": "8"}]}, "memtimingspec": {"parameter": [{"@id": "clkMhz", "@type": "double", "@value": "533"}, {"@id": "RC", "@type": "uint", "@value": "27"}, {"@id": "RCD", "@type": "uint", "@value": "8"}, {"@id": "RL", "@type": "uint", "@value": "6"}, {"@id": "RP", "@type": "uint", "@value": "8"}, {"@id": "RFC", "@type": "uint", "@value": "160"}, {"@id": "RAS", "@type": "uint", "@value": "20"}, {"@id": "WL", "@type": "uint", "@value": "5"}, {"@id": "AL", "@type": "uint", "@value": "0"}, {"@id": "DQSCK", "@type": "uint", "@value": "0"}, {"@id": "RTP", "@type": "uint", "@value": "6"}, {"@id": "WR", "@type": "uint", "@value": "8"}, {"@id": "XP", "@type": "uint", "@value": "4"}, {"@id": "XPDLL", "@type": "uint", "@value": "13"}, {"@id": "XS", "@type": "uint", "@value": "64"}, {"@id": "XSDLL", "@type": "uint", "@value": "512"}, {"@id": "REFI", "@type": "uint", "@value": "4160"}, {"@id": "CL", "@type": "uint", "@value": "6"}, {"@id": "FAW", "@type": "uint", "@value": "27"}, {"@id": "RRD", "@type": "uint", "@value": "6"}, {"@id": "CCD", "@type": "uint", "@value": "4"}, {"@id": "WTR", "@type": "uint", "@value": "6"}, {"@id": "CKE", "@type": "uint", "@value": "6"}, {"@id": "CKESR", "@type": "uint", "@value": "5"}]}, "mempowerspec": {"parameter": [{"@id": "idd0", "@type": "double", "@value": "125.0"}, {"@id": "idd2p0", "@type": "double", "@value": "16.0"}, {"@id": "idd2p1", "@type": "double", "@value": "55.0"}, {"@id": "idd2n", "@type": "double", "@value": "34.0"}, {"@id": "idd3p0", "@type": "double", "@value": "70.0"}, {"@id": "idd3p1", "@type": "double", "@value": "70.0"}, {"@id": "idd3n", "@type": "double", "@value": "60.0"}, {"@id": "idd4w", "@type": "double", "@value": "402.0"}, {"@id": "idd4r", "@type": "double", "@value": "412.0"}, {"@id": "idd5", "@type": "double", "@value": "395.0"}, {"@id": "idd6", "@type": "double", "@value": "22.0"}, {"@id": "vdd", "@type": "double", "@value": "1.5"}]}}}

13
DRAMSys/library/resources/configs/memspecs/memspec.dtd
View File

@@ -1,13 +0,0 @@
<!ELEMENT memspec (parameter*,memarchitecturespec,memtimingspec,mempowerspec)>
<!ELEMENT parameter EMPTY>
<!ATTLIST parameter id CDATA #REQUIRED>
<!ATTLIST parameter type CDATA #REQUIRED>
<!ATTLIST parameter value CDATA #REQUIRED>
<!ATTLIST parameter unit CDATA #IMPLIED>
<!ELEMENT memarchitecturespec (parameter*)>
<!ELEMENT memtimingspec (parameter*)>
<!ELEMENT mempowerspec (parameter*)>

25
DRAMSys/library/resources/simulations/ddr3-example-mcconfigjson.xml
View File

@@ -1,25 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3-example"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifo.json"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="800">ddr3_example.stl</device>
</tracesetup>
</simulation>

6
DRAMSys/library/resources/simulations/ddr3-example.xml
View File

@@ -6,11 +6,11 @@
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.json"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml"></addressmapping>
<addressmapping src="congen_extended.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifo.xml"/>
<mcconfig src="fifo.json"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.

46
DRAMSys/library/src/common/utils.cpp
View File

@@ -42,6 +42,7 @@
#include "dramExtensions.h"
#include <sstream>
using namespace tinyxml2;
using namespace tlm;
@@ -96,6 +97,21 @@ unsigned int queryUIntParameter(XMLElement *node, std::string name)
return 0;
}
unsigned int uIntParameter(nlohmann::json obj, std::string name)
{
using json = nlohmann::json;
if (!obj.empty()){
if (obj.is_number_unsigned()){
return obj;
}
else throw std::invalid_argument("Expected type for '" + name + "': unsigned int");
}
else reportFatal("Query json", "Parameter '" + name + "' does not exist.");
}
bool parameterExists(tinyxml2::XMLElement *node, std::string name)
{
XMLElement *element;
@@ -127,6 +143,22 @@ double queryDoubleParameter(XMLElement *node, std::string name)
return 0;
}
double doubleParameter(nlohmann::json obj, std::string name)
{
if (!obj.empty()){
if (obj.is_number() & obj>0){
return obj;
}
else {
throw std::invalid_argument("Expected type for " + name + ": positive double");
}
}
else {reportFatal("Query json", "Parameter '" + name + "' does not exist.");
return 0;
}
}
bool queryBoolParameter(XMLElement *node, std::string name)
{
bool result = false;
@@ -160,6 +192,20 @@ std::string queryStringParameter(XMLElement *node, std::string name)
return 0;
}
std::string stringParameter(nlohmann::json obj)
{
if (!obj.empty()){
if (obj.is_string()){
return obj;
}
else throw std::invalid_argument("Expected type for parameter string");
}
else reportFatal("Query json", "Parameter does not exist.");
return 0;
}
std::string errorToString(XMLError error)
{
switch (error) {

6
DRAMSys/library/src/common/utils.h
View File

@@ -46,6 +46,7 @@
#include <iomanip>
#include "dramExtensions.h"
#include "third_party/tinyxml2/tinyxml2.h"
#include "../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
#define DEF_SINGLETON( NAME ) \
public: \
@@ -146,6 +147,11 @@ std::string queryStringParameter(tinyxml2::XMLElement *node, std::string name);
bool queryBoolParameter(tinyxml2::XMLElement *node, std::string name);
double queryDoubleParameter(tinyxml2::XMLElement *node, std::string name);
unsigned int uIntParameter(nlohmann::json obj, std::string name);
double doubleParameter(nlohmann::json obj, std::string name);
std::string stringParameter(nlohmann::json obj);
void setUpDummy(tlm::tlm_generic_payload &payload, Rank rank = Rank(0), Bank bank = Bank(0));
#endif // UTILS_H

769
DRAMSys/library/src/configuration/ConfigurationLoader.cpp
View File

@@ -103,15 +103,12 @@ void ConfigurationLoader::loadConfig(Configuration &config,
}
void ConfigurationLoader::loadConfigJson(Configuration &config,
json::object_t *configNode)
json::object_t *configNode)
{
json j = *configNode;
for (auto& x : j.items())
{
config.setParameter(x.key(), x.value());
}
for (auto& x : j.items()) {
config.setParameter(x.key(), x.value());
}
}
void ConfigurationLoader::loadConfigFromUri(Configuration &config,
@@ -135,17 +132,18 @@ void ConfigurationLoader::loadMCConfig(Configuration &config,
void ConfigurationLoader::loadMemSpec(Configuration &config, std::string memspecUri)
{
tinyxml2::XMLDocument doc;
config.memspecUri = memspecUri;
loadXML(memspecUri, doc);
XMLElement *memspec = doc.FirstChildElement("memspec");
json doc = json::parse(std::ifstream(memspecUri));
auto memspec = doc["memspec"].get_ptr<json::object_t*>();
loadMemSpec(config, memspec);
}
void ConfigurationLoader::loadMemSpec(Configuration &config,
XMLElement *memspec)
json::object_t *memspec)
{
std::string memoryType = queryStringParameter(memspec, "memoryType");
using json = nlohmann::json;
json j = *memspec;
auto memoryType = j["memoryType"];
if (memoryType == "DDR4")
{
Configuration::getInstance().memSpec = new MemSpecDDR4();
@@ -204,365 +202,368 @@ void ConfigurationLoader::loadMemSpec(Configuration &config,
reportFatal("ConfigurationLoader", "Unsupported DRAM type");
}
void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec)
void ConfigurationLoader::loadCommons(Configuration &config, json::object_t *jsonSpec)
{
MemSpec *memSpec = config.memSpec;
json j = *jsonSpec;
memSpec->memoryId = stringParameter(j["memoryId"]);
memSpec->memoryType = stringParameter(j["memoryType"]);
memSpec->memoryId = queryStringParameter(xmlSpec, "memoryId");
memSpec->memoryType = queryStringParameter(xmlSpec, "memoryType");
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->burstLength = queryUIntParameter(architecture, "burstLength");
memSpec->dataRate = queryUIntParameter(architecture, "dataRate");
memSpec->numberOfRows = queryUIntParameter(architecture, "nbrOfRows");
memSpec->numberOfColumns = queryUIntParameter(architecture, "nbrOfColumns");
memSpec->bitWidth = queryUIntParameter(architecture, "width");
memSpec->burstLength = uIntParameter( j["memarchitecturespec"]["burstLength"],"burstLength");
memSpec->dataRate = uIntParameter( j["memarchitecturespec"]["dataRate"],"dataRate");
memSpec->numberOfRows = uIntParameter( j["memarchitecturespec"]["nbrOfRows"],"nbrOfRows");
memSpec->numberOfColumns = uIntParameter( j["memarchitecturespec"]["nbrOfColumns"],"nbrOfColumns");
memSpec->bitWidth = uIntParameter( j["memarchitecturespec"]["width"],"width");
// Clock
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
memSpec->fCKMHz = queryDoubleParameter(timings, "clkMhz");
memSpec->fCKMHz = doubleParameter(j["memtimingspec"]["clkMhz"], "clkMhz");
memSpec->tCK = sc_time(1.0 / memSpec->fCKMHz, SC_US);
memSpec->burstDuration = memSpec->tCK * (memSpec->burstLength / memSpec->dataRate);
}
void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec)
void ConfigurationLoader::loadDDR3(Configuration &config, json::object_t *jsonSpec)
{
MemSpecDDR3 *memSpec = dynamic_cast<MemSpecDDR3 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->groupsPerRank = 1;
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
json j = *jsonSpec;
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = uIntParameter(j[arch]["nbrOfRanks"],"nbrOfRanks");
memSpec->banksPerRank = uIntParameter(j[arch]["nbrOfBanks"],"nbrOfBanks");
memSpec->groupsPerRank = 1;
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for DDR3
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR");
//memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC");
memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS");
memSpec->tCCD = memSpec->tCK * queryUIntParameter(timings, "CCD");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC");
memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP");
memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD");
memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR");
memSpec->tAL = memSpec->tCK * queryUIntParameter(timings, "AL");
memSpec->tXPDLL = memSpec->tCK * queryUIntParameter(timings, "XPDLL");
memSpec->tXSDLL = memSpec->tCK * queryUIntParameter(timings, "XSDLL");
std::string timings = "memtimingspec";
memSpec->tCKE = memSpec->tCK * uIntParameter(j[timings]["CKE"], "CKE");
memSpec->tCKESR = memSpec->tCK * uIntParameter(j[timings]["CKESR"], "CKESR");
memSpec->tRAS = memSpec->tCK * uIntParameter(j[timings]["RAS"], "RAS");
memSpec->tRC = memSpec->tCK * uIntParameter(j[timings]["RC"], "RC");
memSpec->tRCD = memSpec->tCK * uIntParameter(j[timings]["RCD"], "RCD");
memSpec->tRL = memSpec->tCK * uIntParameter(j[timings]["RL"], "RL");
memSpec->tRTP = memSpec->tCK * uIntParameter(j[timings]["RTP"], "RTP");
memSpec->tWL = memSpec->tCK * uIntParameter(j[timings]["WL"], "WL");
memSpec->tWR = memSpec->tCK * uIntParameter(j[timings]["WR"], "WR");
memSpec->tXP = memSpec->tCK * uIntParameter(j[timings]["XP"], "XP");
memSpec->tXS = memSpec->tCK * uIntParameter(j[timings]["XS"], "XS");
memSpec->tCCD = memSpec->tCK * uIntParameter(j[timings]["CCD"], "CCD");
memSpec->tFAW = memSpec->tCK * uIntParameter(j[timings]["FAW"], "FAW");
memSpec->tREFI = memSpec->tCK * uIntParameter(j[timings]["REFI"], "REFI");
memSpec->tRFC = memSpec->tCK * uIntParameter(j[timings]["RFC"], "RFC");
memSpec->tRP = memSpec->tCK * uIntParameter(j[timings]["RP"], "RP");
memSpec->tRRD = memSpec->tCK * uIntParameter(j[timings]["RRD"], "RRD");
memSpec->tWTR = memSpec->tCK * uIntParameter(j[timings]["WTR"], "WTR");
memSpec->tAL = memSpec->tCK * uIntParameter(j[timings]["AL"], "AL");
memSpec->tXPDLL = memSpec->tCK * uIntParameter(j[timings]["XPDLL"], "XPDLL");
memSpec->tXSDLL = memSpec->tCK * uIntParameter(j[timings]["XSDLL"], "XSDLL");
// Currents and voltages
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->vDD = queryDoubleParameter(powers, "vdd");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0");
memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1");
std::string power = "mempowerspec";
memSpec->iDD0 = doubleParameter(j[power]["idd0"], "idd0");
memSpec->iDD2N = doubleParameter(j[power]["idd2n"], "idd2n");
memSpec->iDD3N = doubleParameter(j[power]["idd3n"], "idd3n");
memSpec->iDD4R = doubleParameter(j[power]["idd4r"], "idd4r");
memSpec->iDD4W = doubleParameter(j[power]["idd4w"], "idd4w");
memSpec->iDD5 = doubleParameter(j[power]["idd5"], "idd5");
memSpec->iDD6 = doubleParameter(j[power]["idd6"], "idd6");
memSpec->vDD = doubleParameter(j[power]["vdd"], "vdd");
memSpec->iDD2P0 = doubleParameter(j[power]["idd2p0"], "idd2p0");
memSpec->iDD2P1 = doubleParameter(j[power]["idd2p1"], "idd2p1");
memSpec->iDD3P0 = doubleParameter(j[power]["idd3p0"], "idd3p0");
memSpec->iDD3P1 = doubleParameter(j[power]["idd3p1"], "idd3p1");
}
void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec)
void ConfigurationLoader::loadDDR4(Configuration &config, json::object_t *jsonSpec)
{
MemSpecDDR4 *memSpec = dynamic_cast<MemSpecDDR4 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
json j = *jsonSpec;
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups");
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = uIntParameter(j[arch]["nbrOfRanks"],"nbrOfRanks");
memSpec->banksPerRank = uIntParameter(j[arch]["nbrOfBanks"],"nbrOfBanks");
memSpec->groupsPerRank = uIntParameter(j[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for DDR4
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR");
//memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC");
memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS");
memSpec->tCCD_S = memSpec->tCK * queryUIntParameter(timings, "CCD_S");
memSpec->tCCD_L = memSpec->tCK * queryUIntParameter(timings, "CCD_L");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
std::string timings = "memtimingspec";
memSpec->tCKE = memSpec->tCK * uIntParameter(j[timings]["CKE"], "CKE");
memSpec->tCKESR = memSpec->tCK * uIntParameter(j[timings]["CKESR"], "CKESR");
memSpec->tRAS = memSpec->tCK * uIntParameter(j[timings]["RAS"], "RAS");
memSpec->tRC = memSpec->tCK * uIntParameter(j[timings]["RC"], "RC");
memSpec->tRCD = memSpec->tCK * uIntParameter(j[timings]["RCD"], "RCD");
memSpec->tRL = memSpec->tCK * uIntParameter(j[timings]["RL"], "RL");;
memSpec->tWL = memSpec->tCK * uIntParameter(j[timings]["WL"], "WL");
memSpec->tWR = memSpec->tCK * uIntParameter(j[timings]["WR"], "WR");
memSpec->tXP = memSpec->tCK * uIntParameter(j[timings]["XP"], "XP");
memSpec->tXS = memSpec->tCK * uIntParameter(j[timings]["XS"], "XS");
memSpec->tCCD_S = memSpec->tCK * uIntParameter(j[timings]["CCD_S"], "CCD_S");
memSpec->tCCD_L = memSpec->tCK * uIntParameter(j[timings]["CCD_L"], "CCD_L");
memSpec->tFAW = memSpec->tCK * uIntParameter(j[timings]["FAW"], "FAW");
unsigned refreshMode = Configuration::getInstance().refreshMode;
if (refreshMode == 1)
{
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC");
memSpec->tREFI = memSpec->tCK * uIntParameter(j[timings]["REFI"], "REFI");
memSpec->tRFC = memSpec->tCK * uIntParameter(j[timings]["RFC"], "RFC");
}
else if (refreshMode == 2)
{
memSpec->tREFI = memSpec->tCK * (queryUIntParameter(timings, "REFI") / 2);
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC2");
memSpec->tREFI = memSpec->tCK * (uIntParameter(j[timings]["REFI"], "REFI")/ 2);
memSpec->tRFC = memSpec->tCK * uIntParameter(j[timings]["RFC2"], "RFC2");
}
else if (refreshMode == 4)
{
memSpec->tREFI = memSpec->tCK * (queryUIntParameter(timings, "REFI") / 2);
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC4");
memSpec->tREFI = memSpec->tCK * (uIntParameter(j[timings]["REFI"], "REFI")/ 2);
memSpec->tRFC = memSpec->tCK * uIntParameter(j[timings]["RFC4"], "RFC4");
}
else
SC_REPORT_FATAL("ConfigurationLoader", "Refresh Mode not supported");
memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP");
memSpec->tRRD_S = memSpec->tCK * queryUIntParameter(timings, "RRD_S");
memSpec->tRRD_L = memSpec->tCK * queryUIntParameter(timings, "RRD_L");
memSpec->tWTR_S = memSpec->tCK * queryUIntParameter(timings, "WTR_S");
memSpec->tWTR_L = memSpec->tCK * queryUIntParameter(timings, "WTR_L");
memSpec->tAL = memSpec->tCK * queryUIntParameter(timings, "AL");
memSpec->tXPDLL = memSpec->tCK * queryUIntParameter(timings, "XPDLL");
memSpec->tXSDLL = memSpec->tCK * queryUIntParameter(timings, "XSDLL");
memSpec->tRP = memSpec->tCK * uIntParameter(j[timings]["RP"], "RP");
memSpec->tRRD_S = memSpec->tCK * uIntParameter(j[timings]["RRD_S"], "RRD_S");
memSpec->tRRD_L = memSpec->tCK * uIntParameter(j[timings]["RRD_L"], "RRD_L");
memSpec->tWTR_S = memSpec->tCK * uIntParameter(j[timings]["WTR_S"], "WTR_S");
memSpec->tWTR_L = memSpec->tCK * uIntParameter(j[timings]["WTR_L"], "WTR_L");
memSpec->tAL = memSpec->tCK * uIntParameter(j[timings]["AL"], "AL");
memSpec->tXPDLL = memSpec->tCK * uIntParameter(j[timings]["XPDLL"], "XPDLL");
memSpec->tXSDLL = memSpec->tCK * uIntParameter(j[timings]["XSDLL"], "XSDLL");
// Currents and voltages
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->vDD = queryDoubleParameter(powers, "vdd");
memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0");
memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1");
memSpec->iDD62 = queryDoubleParameter(powers, "idd62");
memSpec->vDD2 = queryDoubleParameter(powers, "vdd2");
std::string power = "mempowerspec";
memSpec->iDD0 = doubleParameter(j[power]["idd0"], "idd0");
memSpec->iDD2N = doubleParameter(j[power]["idd2n"], "idd2n");
memSpec->iDD3N = doubleParameter(j[power]["idd3n"], "idd3n");
memSpec->iDD4R = doubleParameter(j[power]["idd4r"], "idd4r");
memSpec->iDD4W = doubleParameter(j[power]["idd4w"], "idd4w");
memSpec->iDD5 = doubleParameter(j[power]["idd5"], "idd5");
memSpec->iDD6 = doubleParameter(j[power]["idd6"], "idd6");
memSpec->vDD = doubleParameter(j[power]["vdd"], "vdd");
memSpec->iDD02 = doubleParameter(j[power]["idd02"], "idd02");
memSpec->iDD2P0 = doubleParameter(j[power]["idd2p0"], "idd2p0");
memSpec->iDD2P1 = doubleParameter(j[power]["idd2p1"], "idd2p1");
memSpec->iDD3P0 = doubleParameter(j[power]["idd3p0"], "idd3p0");
memSpec->iDD3P1 = doubleParameter(j[power]["idd3p1"], "idd3p1");
memSpec->iDD62 = doubleParameter(j[power]["idd62"], "idd62");
memSpec->vDD2 = doubleParameter(j[power]["vdd2"], "vdd2");
}
void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec)
void ConfigurationLoader::loadLPDDR4(Configuration &config, json::object_t *jsonSpec)
{
MemSpecLPDDR4 *memSpec = dynamic_cast<MemSpecLPDDR4 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
json j = *jsonSpec;
// MemArchitecture:
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = uIntParameter(j[arch]["nbrOfRanks"],"nbrOfRanks");
memSpec->banksPerRank = uIntParameter(j[arch]["nbrOfBanks"],"nbrOfBanks");
memSpec->groupsPerRank = 1;
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for LPDDR4
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tREFIpb = memSpec->tCK * queryUIntParameter(timings, "REFIPB");
memSpec->tRFCab = memSpec->tCK * queryUIntParameter(timings, "RFCAB");
memSpec->tRFCpb = memSpec->tCK * queryUIntParameter(timings, "RFCPB");
memSpec->tRPab = memSpec->tCK * queryUIntParameter(timings, "RPAB");
memSpec->tRPpb = memSpec->tCK * queryUIntParameter(timings, "RPPB");
memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD");
memSpec->tCCD = memSpec->tCK * queryUIntParameter(timings, "CCD");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tRPST = memSpec->tCK * queryUIntParameter(timings, "RPST");
memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tDQSS = memSpec->tCK * queryUIntParameter(timings, "DQSS");
memSpec->tDQS2DQ = memSpec->tCK * queryUIntParameter(timings, "DQS2DQ");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tWPRE = memSpec->tCK * queryUIntParameter(timings, "WPRE");
memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tSR = memSpec->tCK * queryUIntParameter(timings, "SR");
memSpec->tXSR = memSpec->tCK * queryUIntParameter(timings, "XSR");
memSpec->tESCKE = memSpec->tCK * queryUIntParameter(timings, "ESCKE");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
memSpec->tCMDCKE = memSpec->tCK * queryUIntParameter(timings, "CMDCKE");
std::string timings = "memtimingspec";
memSpec->tREFI = memSpec->tCK * uIntParameter(j[timings]["REFI"], "REFI");
memSpec->tREFIpb = memSpec->tCK * uIntParameter(j[timings]["REFIPB"], "REFIPB");
memSpec->tRFCab = memSpec->tCK * uIntParameter(j[timings]["RFCAB"], "RFCAB");
memSpec->tRFCpb = memSpec->tCK * uIntParameter(j[timings]["RFCPB"], "RFCPB");
memSpec->tRPab = memSpec->tCK * uIntParameter(j[timings]["RPAB"], "RPAB");
memSpec->tRPpb = memSpec->tCK * uIntParameter(j[timings]["RPPB"], "RPPB");
memSpec->tPPD = memSpec->tCK * uIntParameter(j[timings]["PPD"], "PPD");
memSpec->tRAS = memSpec->tCK * uIntParameter(j[timings]["RAS"], "RAS");
memSpec->tRCD = memSpec->tCK * uIntParameter(j[timings]["RCD"], "RCD");
memSpec->tFAW = memSpec->tCK * uIntParameter(j[timings]["FAW"], "FAW");
memSpec->tRRD = memSpec->tCK * uIntParameter(j[timings]["RRD"], "RRD");
memSpec->tCCD = memSpec->tCK * uIntParameter(j[timings]["CCD"], "CCD");
memSpec->tRL = memSpec->tCK * uIntParameter(j[timings]["RL"], "RL");
memSpec->tRPST = memSpec->tCK * uIntParameter(j[timings]["RPST"], "RPST");
memSpec->tDQSCK = memSpec->tCK * uIntParameter(j[timings]["DQSCK"], "DQSCK");
memSpec->tRTP = memSpec->tCK * uIntParameter(j[timings]["RTP"], "RTP");
memSpec->tWL = memSpec->tCK * uIntParameter(j[timings]["WL"], "WL");
memSpec->tDQSS = memSpec->tCK * uIntParameter(j[timings]["DQSS"], "DQSS");
memSpec->tDQS2DQ = memSpec->tCK * uIntParameter(j[timings]["DQS2DQ"], "DQS2DQ");
memSpec->tWR = memSpec->tCK * uIntParameter(j[timings]["WR"], "WR");
memSpec->tWPRE = memSpec->tCK * uIntParameter(j[timings]["WPRE"], "WPRE");
memSpec->tWTR = memSpec->tCK * uIntParameter(j[timings]["WTR"], "WTR");
memSpec->tXP = memSpec->tCK * uIntParameter(j[timings]["XP"], "XP");
memSpec->tSR = memSpec->tCK * uIntParameter(j[timings]["SR"], "SR");
memSpec->tXSR = memSpec->tCK * uIntParameter(j[timings]["XSR"], "XSR");
memSpec->tESCKE = memSpec->tCK * uIntParameter(j[timings]["ESCKE"], "ESCKE");
memSpec->tCKE = memSpec->tCK * uIntParameter(j[timings]["CKE"], "CKE");
memSpec->tCMDCKE = memSpec->tCK * uIntParameter(j[timings]["CMDCKE"], "CMDCKE");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *xmlSpec)
void ConfigurationLoader::loadWideIO(Configuration &config, json::object_t *jsonSpec)
{
MemSpecWideIO *memSpec = dynamic_cast<MemSpecWideIO *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
json j = *jsonSpec;
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = uIntParameter(j[arch]["nbrOfRanks"], "nbrOfRanks");
memSpec->banksPerRank = uIntParameter(j[arch]["nbrOfBanks"], "nbrOfBanks");
memSpec->groupsPerRank = 1;
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for WideIO
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR");
memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK");
memSpec->tAC = memSpec->tCK * queryUIntParameter(timings, "AC");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC");
memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS");
memSpec->tCCD_R = memSpec->tCK * queryUIntParameter(timings, "CCD_R");
memSpec->tCCD_W = memSpec->tCK * queryUIntParameter(timings, "CCD_W");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC");
memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP");
memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD");
memSpec->tTAW = memSpec->tCK * queryUIntParameter(timings, "TAW");
memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR");
std::string timings = "memtimingspec";
memSpec->tCKE = memSpec->tCK * uIntParameter(j[timings]["CKE"], "CKE");
memSpec->tCKESR = memSpec->tCK * uIntParameter(j[timings]["CKESR"], "CKESR");
memSpec->tDQSCK = memSpec->tCK * uIntParameter(j[timings]["DQSCK"], "DQSCK");
memSpec->tAC = memSpec->tCK * uIntParameter(j[timings]["AC"], "AC");
memSpec->tRAS = memSpec->tCK * uIntParameter(j[timings]["RAS"], "RAS");
memSpec->tRC = memSpec->tCK * uIntParameter(j[timings]["RC"], "RC");
memSpec->tRCD = memSpec->tCK * uIntParameter(j[timings]["RCD"], "RCD");
memSpec->tRL = memSpec->tCK * uIntParameter(j[timings]["RL"], "RL");
memSpec->tWL = memSpec->tCK * uIntParameter(j[timings]["WL"], "WL");
memSpec->tWR = memSpec->tCK * uIntParameter(j[timings]["WR"], "WR");
memSpec->tXP = memSpec->tCK * uIntParameter(j[timings]["XP"], "XP");
memSpec->tXS = memSpec->tCK * uIntParameter(j[timings]["XS"], "XS");
memSpec->tCCD_R = memSpec->tCK * uIntParameter(j[timings]["CCD_R"], "CCD_R");
memSpec->tCCD_W = memSpec->tCK * uIntParameter(j[timings]["CCD_W"], "CCD_W");
memSpec->tREFI = memSpec->tCK * uIntParameter(j[timings]["REFI"], "REFI");
memSpec->tRFC = memSpec->tCK * uIntParameter(j[timings]["RFC"], "RFC");
memSpec->tRP = memSpec->tCK * uIntParameter(j[timings]["RP"], "RP");
memSpec->tRRD = memSpec->tCK * uIntParameter(j[timings]["RRD"], "RRD");
memSpec->tTAW = memSpec->tCK * uIntParameter(j[timings]["TAW"], "TAW");
memSpec->tWTR = memSpec->tCK * uIntParameter(j[timings]["WTR"], "WTR");
// Currents and voltages
XMLElement *powers = xmlSpec->FirstChildElement("mempowerspec");
memSpec->iDD0 = queryDoubleParameter(powers, "idd0");
memSpec->iDD2N = queryDoubleParameter(powers, "idd2n");
memSpec->iDD3N = queryDoubleParameter(powers, "idd3n");
memSpec->iDD4R = queryDoubleParameter(powers, "idd4r");
memSpec->iDD4W = queryDoubleParameter(powers, "idd4w");
memSpec->iDD5 = queryDoubleParameter(powers, "idd5");
memSpec->iDD6 = queryDoubleParameter(powers, "idd6");
memSpec->vDD = queryDoubleParameter(powers, "vdd");
memSpec->iDD02 = queryDoubleParameter(powers, "idd02");
memSpec->iDD2P0 = queryDoubleParameter(powers, "idd2p0");
memSpec->iDD2P02 = queryDoubleParameter(powers, "idd2p02");
memSpec->iDD2P1 = queryDoubleParameter(powers, "idd2p1");
memSpec->iDD2P12 = queryDoubleParameter(powers, "idd2p12");
memSpec->iDD2N2 = queryDoubleParameter(powers, "idd2n2");
memSpec->iDD3P0 = queryDoubleParameter(powers, "idd3p0");
memSpec->iDD3P02 = queryDoubleParameter(powers, "idd3p02");
memSpec->iDD3P1 = queryDoubleParameter(powers, "idd3p1");
memSpec->iDD3P12 = queryDoubleParameter(powers, "idd3p12");
memSpec->iDD3N2 = queryDoubleParameter(powers, "idd3n2");
memSpec->iDD4R2 = queryDoubleParameter(powers, "idd4r2");
memSpec->iDD4W2 = queryDoubleParameter(powers, "idd4w2");
memSpec->iDD52 = queryDoubleParameter(powers, "idd52");
memSpec->iDD62 = queryDoubleParameter(powers, "idd62");
memSpec->vDD2 = queryDoubleParameter(powers, "vdd2");
std::string power = "mempowerspec";
memSpec->iDD0 = doubleParameter(j[power]["idd0"], "idd0");
memSpec->iDD2N = doubleParameter(j[power]["idd2n"], "idd2n");
memSpec->iDD3N = doubleParameter(j[power]["idd3n"], "idd3n");
memSpec->iDD4R = doubleParameter(j[power]["idd4r"], "idd4r");
memSpec->iDD4W = doubleParameter(j[power]["idd4w"], "idd4w");
memSpec->iDD5 = doubleParameter(j[power]["idd5"], "idd5");
memSpec->iDD6 = doubleParameter(j[power]["idd6"], "idd6");
memSpec->vDD = doubleParameter(j[power]["vdd"], "vdd");
memSpec->iDD02 = doubleParameter(j[power]["idd02"], "idd02");
memSpec->iDD2P0 = doubleParameter(j[power]["idd2p0"], "idd2p0");
memSpec->iDD2P02 = doubleParameter(j[power]["idd2p02"], "idd2p02");
memSpec->iDD2P1 = doubleParameter(j[power]["idd2p1"], "idd2p1");
memSpec->iDD2P12 = doubleParameter(j[power]["idd2p12"], "idd2p12");
memSpec->iDD2N2 = doubleParameter(j[power]["idd2n2"], "idd2n2");
memSpec->iDD3P0 = doubleParameter(j[power]["idd3p0"], "idd3p0");
memSpec->iDD3P02 = doubleParameter(j[power]["idd3p02"], "idd3p02");
memSpec->iDD3P1 = doubleParameter(j[power]["idd3p1"], "idd3p1");
memSpec->iDD3P12 = doubleParameter(j[power]["idd3p12"], "idd3p12");
memSpec->iDD3N2 = doubleParameter(j[power]["idd3n2"], "idd3n2");
memSpec->iDD4R2 = doubleParameter(j[power]["idd4r2"], "idd4r2");
memSpec->iDD4W2 = doubleParameter(j[power]["idd4w2"], "idd4w2");
memSpec->iDD52 = doubleParameter(j[power]["idd52"], "idd52");
memSpec->iDD62 = doubleParameter(j[power]["idd62"], "idd62");
memSpec->vDD2 = doubleParameter(j[power]["vdd2"], "vdd2");
}
void ConfigurationLoader::loadWideIO2(Configuration &config, XMLElement *xmlSpec)
void ConfigurationLoader::loadWideIO2(Configuration &config, json::object_t *jsonSpec)
{
MemSpecWideIO2 *memSpec = dynamic_cast<MemSpecWideIO2 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
json j = *jsonSpec;
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = uIntParameter(j[arch]["nbrOfRanks"], "nbrOfRanks");
memSpec->banksPerRank = uIntParameter(j[arch]["nbrOfBanks"], "nbrOfBanks");
memSpec->groupsPerRank = 1;
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for WideIO
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK");
memSpec->tDQSS = memSpec->tCK * queryUIntParameter(timings, "DQSS");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tRCpb = memSpec->tCK * queryUIntParameter(timings, "RCPB");
memSpec->tRCab = memSpec->tCK * queryUIntParameter(timings, "RCAB");
memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR");
memSpec->tXSR = memSpec->tCK * queryUIntParameter(timings, "XSR");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tCCD = memSpec->tCK * queryUIntParameter(timings, "CCD");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tRCD = memSpec->tCK * queryUIntParameter(timings, "RCD");
memSpec->tRPpb = memSpec->tCK * queryUIntParameter(timings, "RPPB");
memSpec->tRPab = memSpec->tCK * queryUIntParameter(timings, "RPAB");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tWTR = memSpec->tCK * queryUIntParameter(timings, "WTR");
memSpec->tRRD = memSpec->tCK * queryUIntParameter(timings, "RRD");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tREFIpb = memSpec->tCK * queryUIntParameter(timings, "REFIPB");
memSpec->tRFCab = memSpec->tCK * queryUIntParameter(timings, "RFCAB");
memSpec->tRFCpb = memSpec->tCK * queryUIntParameter(timings, "RFCPB");
std::string timings = "memtimingspec";
memSpec->tDQSCK = memSpec->tCK * uIntParameter(j[timings]["DQSCK"], "DQSCK");
memSpec->tDQSS = memSpec->tCK * uIntParameter(j[timings]["DQSS"], "DQSS");
memSpec->tCKE = memSpec->tCK * uIntParameter(j[timings]["CKE"], "CKE");
memSpec->tRL = memSpec->tCK * uIntParameter(j[timings]["RL"], "RL");
memSpec->tWL = memSpec->tCK * uIntParameter(j[timings]["WL"], "WL");
memSpec->tRCpb = memSpec->tCK * uIntParameter(j[timings]["RCPB"], "RCPB");
memSpec->tRCab = memSpec->tCK * uIntParameter(j[timings]["RCAB"], "RCAB");
memSpec->tCKESR = memSpec->tCK * uIntParameter(j[timings]["CKESR"], "CKESR");
memSpec->tXSR = memSpec->tCK * uIntParameter(j[timings]["XSR"], "XSR");
memSpec->tXP = memSpec->tCK * uIntParameter(j[timings]["XP"], "XP");
memSpec->tCCD = memSpec->tCK * uIntParameter(j[timings]["CCD"], "CCD");
memSpec->tRTP = memSpec->tCK * uIntParameter(j[timings]["RTP"], "RTP");
memSpec->tRCD = memSpec->tCK * uIntParameter(j[timings]["RCD"], "RCD");
memSpec->tRPpb = memSpec->tCK * uIntParameter(j[timings]["RPPB"], "RPPB");
memSpec->tRPab = memSpec->tCK * uIntParameter(j[timings]["RPAB"], "RPAB");
memSpec->tRAS = memSpec->tCK * uIntParameter(j[timings]["RAS"], "RAS");
memSpec->tWR = memSpec->tCK * uIntParameter(j[timings]["WR"], "WR");
memSpec->tWTR = memSpec->tCK * uIntParameter(j[timings]["WTR"], "WTR");
memSpec->tRRD = memSpec->tCK * uIntParameter(j[timings]["RRD"], "RRD");
memSpec->tFAW = memSpec->tCK * uIntParameter(j[timings]["FAW"], "FAW");
memSpec->tREFI = memSpec->tCK * uIntParameter(j[timings]["REFI"], "REFI");
memSpec->tREFIpb = memSpec->tCK * uIntParameter(j[timings]["REFIPB"], "REFIPB");
memSpec->tRFCab = memSpec->tCK * uIntParameter(j[timings]["RFCAB"], "RFCAB");
memSpec->tRFCpb = memSpec->tCK * uIntParameter(j[timings]["RFCPB"], "RFCPB");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadHBM2(Configuration &config, XMLElement *xmlSpec)
void ConfigurationLoader::loadHBM2(Configuration &config, json::object_t *jsonSpec)
{
MemSpecHBM2 *memSpec = dynamic_cast<MemSpecHBM2 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
json j = *jsonSpec;
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups");
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = uIntParameter(j[arch]["nbrOfRanks"], "nbrOfRanks");
memSpec->banksPerRank = uIntParameter(j[arch]["nbrOfBanks"], "nbrOfBanks");
memSpec->groupsPerRank = uIntParameter(j[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for HBM2
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
memSpec->tDQSCK = memSpec->tCK * queryUIntParameter(timings, "DQSCK");
// memSpec->tDQSQ = memSpec->tCK * queryUIntParameter(timings, "DQSQ");
memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR");
memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL");
memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tPL = memSpec->tCK * queryUIntParameter(timings, "PL");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL");
memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS");
// memSpec->tCCDR = memSpec->tCK * queryUIntParameter(timings, "CCDR");
memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL");
memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS");
memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
std::string timings = "memtimingspec";
memSpec->tDQSCK = memSpec->tCK * uIntParameter(j[timings]["DQSCK"], "DQSCK");
memSpec->tRC = memSpec->tCK * uIntParameter(j[timings]["RC"], "RC");
memSpec->tRAS = memSpec->tCK * uIntParameter(j[timings]["RAS"], "RAS");
memSpec->tRCDRD = memSpec->tCK * uIntParameter(j[timings]["RCDRD"], "RCDRD");
memSpec->tRCDWR = memSpec->tCK * uIntParameter(j[timings]["RCDWR"], "RCDWR");
memSpec->tRRDL = memSpec->tCK * uIntParameter(j[timings]["RRDL"], "RRDL");
memSpec->tRRDS = memSpec->tCK * uIntParameter(j[timings]["RRDS"], "RRDS");
memSpec->tFAW = memSpec->tCK * uIntParameter(j[timings]["FAW"], "FAW");
memSpec->tRTP = memSpec->tCK * uIntParameter(j[timings]["RTP"], "RTP");
memSpec->tRP = memSpec->tCK * uIntParameter(j[timings]["RP"], "RP");
memSpec->tRL = memSpec->tCK * uIntParameter(j[timings]["RL"], "RL");
memSpec->tWL = memSpec->tCK * uIntParameter(j[timings]["WL"], "WL");
memSpec->tPL = memSpec->tCK * uIntParameter(j[timings]["PL"], "PL");
memSpec->tWR = memSpec->tCK * uIntParameter(j[timings]["WR"], "WR");
memSpec->tCCDL = memSpec->tCK * uIntParameter(j[timings]["CCDL"], "CCDL");
memSpec->tCCDS = memSpec->tCK * uIntParameter(j[timings]["CCDS"], "CCDS");
memSpec->tWTRL = memSpec->tCK * uIntParameter(j[timings]["WTRL"], "WTRL");
memSpec->tWTRS = memSpec->tCK * uIntParameter(j[timings]["WTRS"], "WTRS");
memSpec->tRTW = memSpec->tCK * uIntParameter(j[timings]["RTW"], "RTW");
memSpec->tXP = memSpec->tCK * uIntParameter(j[timings]["XP"], "XP");
memSpec->tCKE = memSpec->tCK * uIntParameter(j[timings]["CKE"], "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tRDPDE = memSpec->tRL + memSpec->tPL
+ (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->tCK;
@@ -573,192 +574,198 @@ void ConfigurationLoader::loadHBM2(Configuration &config, XMLElement *xmlSpec)
memSpec->tCKESR = memSpec->tCKE + memSpec->tCK;
memSpec->tRDSRE = memSpec->tRL + memSpec->tPL
+ (memSpec->burstLength / memSpec->dataRate + 1) * memSpec->tCK;
memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS");
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC");
memSpec->tRFCSB = memSpec->tCK * queryUIntParameter(timings, "RFCSB");
memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tREFISB = memSpec->tCK * queryUIntParameter(timings, "REFISB");
memSpec->tXS = memSpec->tCK * uIntParameter(j[timings]["XS"], "XS");
memSpec->tRFC = memSpec->tCK * uIntParameter(j[timings]["RFC"], "RFC");
memSpec->tRFCSB = memSpec->tCK * uIntParameter(j[timings]["RFCSB"], "RFCSB");
memSpec->tRREFD = memSpec->tCK * uIntParameter(j[timings]["RREFD"], "RREFD");
memSpec->tREFI = memSpec->tCK * uIntParameter(j[timings]["REFI"], "REFI");
memSpec->tREFISB = memSpec->tCK * uIntParameter(j[timings]["REFISB"], "REFISB");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadGDDR5(Configuration &config, XMLElement *xmlSpec)
void ConfigurationLoader::loadGDDR5(Configuration &config, json::object_t *jsonSpec)
{
MemSpecGDDR5 *memSpec = dynamic_cast<MemSpecGDDR5 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
json j = *jsonSpec;
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups");
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = uIntParameter(j[arch]["nbrOfRanks"], "nbrOfRanks");
memSpec->banksPerRank = uIntParameter(j[arch]["nbrOfBanks"], "nbrOfBanks");
memSpec->groupsPerRank = uIntParameter(j[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for GDDR5
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC");
memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS");
memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL");
memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS");
memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL");
memSpec->tCL = memSpec->tCK * queryUIntParameter(timings, "CL");
memSpec->tWCK2CKPIN = memSpec->tCK * queryUIntParameter(timings, "WCK2CKPIN");
memSpec->tWCK2CK = memSpec->tCK * queryUIntParameter(timings, "WCK2CK");
memSpec->tWCK2DQO = memSpec->tCK * queryUIntParameter(timings, "WCK2DQO");
memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tWCK2DQI = memSpec->tCK * queryUIntParameter(timings, "WCK2DQI");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS");
memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
std::string timings = "memtimingspec";
memSpec->tRP = memSpec->tCK * uIntParameter(j[timings]["RP"], "RP");
memSpec->tRAS = memSpec->tCK * uIntParameter(j[timings]["RAS"], "RAS");
memSpec->tRC = memSpec->tCK * uIntParameter(j[timings]["RC"], "RC");
memSpec->tRCDRD = memSpec->tCK * uIntParameter(j[timings]["RCDRD"], "RCDRD");
memSpec->tRCDWR = memSpec->tCK * uIntParameter(j[timings]["RCDWR"], "RCDWR");
memSpec->tRTP = memSpec->tCK * uIntParameter(j[timings]["RTP"], "RTP");
memSpec->tRRDS = memSpec->tCK * uIntParameter(j[timings]["RRDS"], "RRDS");
memSpec->tRRDL = memSpec->tCK * uIntParameter(j[timings]["RRDL"], "RRDL");
memSpec->tCCDS = memSpec->tCK * uIntParameter(j[timings]["CCDS"], "CCDS");
memSpec->tCCDL = memSpec->tCK * uIntParameter(j[timings]["CCDL"], "CCDL");
memSpec->tCL = memSpec->tCK * uIntParameter(j[timings]["CL"], "CL");
memSpec->tWCK2CKPIN = memSpec->tCK * uIntParameter(j[timings]["WCK2CKPIN"], "WCK2CKPIN");
memSpec->tWCK2CK = memSpec->tCK * uIntParameter(j[timings]["WCK2CK"], "WCK2CK");
memSpec->tWCK2DQO = memSpec->tCK * uIntParameter(j[timings]["WCK2DQO"], "WCK2DQO");
memSpec->tRTW = memSpec->tCK * uIntParameter(j[timings]["RTW"], "RTW");
memSpec->tWL = memSpec->tCK * uIntParameter(j[timings]["WL"], "WL");
memSpec->tWCK2DQI = memSpec->tCK * uIntParameter(j[timings]["WCK2DQI"], "WCK2DQI");
memSpec->tWR = memSpec->tCK * uIntParameter(j[timings]["WR"], "WR");
memSpec->tWTRS = memSpec->tCK * uIntParameter(j[timings]["WTRS"], "WTRS");
memSpec->tWTRL = memSpec->tCK * uIntParameter(j[timings]["WTRL"], "WTRL");
memSpec->tCKE = memSpec->tCK * uIntParameter(j[timings]["CKE"], "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tXPN = memSpec->tCK * queryUIntParameter(timings, "XPN");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tREFIPB = memSpec->tCK * queryUIntParameter(timings, "REFIPB");
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC");
memSpec->tRFCPB = memSpec->tCK * queryUIntParameter(timings, "RFCPB");
memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD");
memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
memSpec->t32AW = memSpec->tCK * queryUIntParameter(timings, "32AW");
memSpec->tXPN = memSpec->tCK * uIntParameter(j[timings]["XPN"], "XPN");
memSpec->tREFI = memSpec->tCK * uIntParameter(j[timings]["REFI"], "REFI");
memSpec->tREFIPB = memSpec->tCK * uIntParameter(j[timings]["REFIPB"], "REFIPB");
memSpec->tRFC = memSpec->tCK * uIntParameter(j[timings]["RFC"], "RFC");
memSpec->tRFCPB = memSpec->tCK * uIntParameter(j[timings]["RFCPB"], "RFCPB");
memSpec->tRREFD = memSpec->tCK * uIntParameter(j[timings]["RREFD"], "RREFD");
memSpec->tXS = memSpec->tCK * uIntParameter(j[timings]["XS"], "XS");
memSpec->tFAW = memSpec->tCK * uIntParameter(j[timings]["FAW"], "FAW");
memSpec->t32AW = memSpec->tCK * uIntParameter(j[timings]["32AW"], "32AW");
memSpec->tRDSRE = memSpec->tCL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD");
memSpec->tLK = memSpec->tCK * queryUIntParameter(timings, "LK");
memSpec->tPPD = memSpec->tCK * uIntParameter(j[timings]["PPD"], "PPD");
memSpec->tLK = memSpec->tCK * uIntParameter(j[timings]["LK"], "LK");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadGDDR5X(Configuration &config, XMLElement *xmlSpec)
void ConfigurationLoader::loadGDDR5X(Configuration &config, json::object_t *jsonSpec)
{
MemSpecGDDR5X *memSpec = dynamic_cast<MemSpecGDDR5X *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
json j = *jsonSpec;
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups");
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = uIntParameter(j[arch]["nbrOfRanks"], "nbrOfRanks");
memSpec->banksPerRank = uIntParameter(j[arch]["nbrOfBanks"], "nbrOfBanks");
memSpec->groupsPerRank = uIntParameter(j[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for GDDR5X
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC");
memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS");
memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL");
memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS");
memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tWCK2CKPIN = memSpec->tCK * queryUIntParameter(timings, "WCK2CKPIN");
memSpec->tWCK2CK = memSpec->tCK * queryUIntParameter(timings, "WCK2CK");
memSpec->tWCK2DQO = memSpec->tCK * queryUIntParameter(timings, "WCK2DQO");
memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tWCK2DQI = memSpec->tCK * queryUIntParameter(timings, "WCK2DQI");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS");
memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
std::string timings = "memtimingspec";
memSpec->tRP = memSpec->tCK * uIntParameter(j[timings]["RP"], "RP");
memSpec->tRAS = memSpec->tCK * uIntParameter(j[timings]["RAS"], "RAS");
memSpec->tRC = memSpec->tCK * uIntParameter(j[timings]["RC"], "RC");
memSpec->tRCDRD = memSpec->tCK * uIntParameter(j[timings]["RCDRD"], "RCDRD");
memSpec->tRCDWR = memSpec->tCK * uIntParameter(j[timings]["RCDWR"], "RCDWR");
memSpec->tRTP = memSpec->tCK * uIntParameter(j[timings]["RTP"], "RTP");
memSpec->tRRDS = memSpec->tCK * uIntParameter(j[timings]["RRDS"], "RRDS");
memSpec->tRRDL = memSpec->tCK * uIntParameter(j[timings]["RRDL"], "RRDL");
memSpec->tCCDS = memSpec->tCK * uIntParameter(j[timings]["CCDS"], "CCDS");
memSpec->tCCDL = memSpec->tCK * uIntParameter(j[timings]["CCDL"], "CCDL");
memSpec->tRL = memSpec->tCK * uIntParameter(j[timings]["RL"], "RL");
memSpec->tWCK2CKPIN = memSpec->tCK * uIntParameter(j[timings]["WCK2CKPIN"], "WCK2CKPIN");
memSpec->tWCK2CK = memSpec->tCK * uIntParameter(j[timings]["WCK2CK"], "WCK2CK");
memSpec->tWCK2DQO = memSpec->tCK * uIntParameter(j[timings]["WCK2DQO"], "WCK2DQO");
memSpec->tRTW = memSpec->tCK * uIntParameter(j[timings]["RTW"], "RTW");
memSpec->tWL = memSpec->tCK * uIntParameter(j[timings]["WL"], "WL");
memSpec->tWCK2DQI = memSpec->tCK * uIntParameter(j[timings]["WCK2DQI"], "WCK2DQI");
memSpec->tWR = memSpec->tCK * uIntParameter(j[timings]["WR"], "WR");
memSpec->tWTRS = memSpec->tCK * uIntParameter(j[timings]["WTRS"], "WTRS");
memSpec->tWTRL = memSpec->tCK * uIntParameter(j[timings]["WTRL"], "WTRL");
memSpec->tCKE = memSpec->tCK * uIntParameter(j[timings]["CKE"], "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tREFIPB = memSpec->tCK * queryUIntParameter(timings, "REFIPB");
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC");
memSpec->tRFCPB = memSpec->tCK * queryUIntParameter(timings, "RFCPB");
memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD");
memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
memSpec->t32AW = memSpec->tCK * queryUIntParameter(timings, "32AW");
memSpec->tXP = memSpec->tCK * uIntParameter(j[timings]["XP"], "XP");
memSpec->tREFI = memSpec->tCK * uIntParameter(j[timings]["REFI"], "REFI");
memSpec->tREFIPB = memSpec->tCK * uIntParameter(j[timings]["REFIPB"], "REFIPB");
memSpec->tRFC = memSpec->tCK * uIntParameter(j[timings]["RFC"], "RFC");
memSpec->tRFCPB = memSpec->tCK * uIntParameter(j[timings]["RFCPB"], "RFCPB");
memSpec->tRREFD = memSpec->tCK * uIntParameter(j[timings]["RREFD"], "RREFD");
memSpec->tXS = memSpec->tCK * uIntParameter(j[timings]["XS"], "XS");
memSpec->tFAW = memSpec->tCK * uIntParameter(j[timings]["FAW"], "FAW");
memSpec->t32AW = memSpec->tCK * uIntParameter(j[timings]["32AW"], "32AW");
memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD");
memSpec->tLK = memSpec->tCK * queryUIntParameter(timings, "LK");
memSpec->tPPD = memSpec->tCK * uIntParameter(j[timings]["PPD"], "PPD");
memSpec->tLK = memSpec->tCK * uIntParameter(j[timings]["LK"], "LK");
// Currents and voltages
// TODO: to be completed
}
void ConfigurationLoader::loadGDDR6(Configuration &config, XMLElement *xmlSpec)
void ConfigurationLoader::loadGDDR6(Configuration &config, json::object_t *jsonSpec)
{
MemSpecGDDR6 *memSpec = dynamic_cast<MemSpecGDDR6 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen");
json j = *jsonSpec;
// MemArchitecture
XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec");
memSpec->numberOfRanks = queryUIntParameter(architecture, "nbrOfRanks");
memSpec->banksPerRank = queryUIntParameter(architecture, "nbrOfBanks");
memSpec->groupsPerRank = queryUIntParameter(architecture, "nbrOfBankGroups");
std::string arch = "memarchitecturespec";
memSpec->numberOfRanks = uIntParameter(j[arch]["nbrOfRanks"], "nbrOfRanks");
memSpec->banksPerRank = uIntParameter(j[arch]["nbrOfBanks"], "nbrOfBanks");
memSpec->groupsPerRank = uIntParameter(j[arch]["nbrOfBankGroups"], "nbrOfBankGroups");
memSpec->banksPerGroup = memSpec->banksPerRank / memSpec->groupsPerRank;
memSpec->numberOfBanks = memSpec->banksPerRank * memSpec->numberOfRanks;
memSpec->numberOfBankGroups = memSpec->groupsPerRank * memSpec->numberOfRanks;
// MemTimings specific for GDDR6
XMLElement *timings = xmlSpec->FirstChildElement("memtimingspec");
memSpec->tRP = memSpec->tCK * queryUIntParameter(timings, "RP");
memSpec->tRAS = memSpec->tCK * queryUIntParameter(timings, "RAS");
memSpec->tRC = memSpec->tCK * queryUIntParameter(timings, "RC");
memSpec->tRCDRD = memSpec->tCK * queryUIntParameter(timings, "RCDRD");
memSpec->tRCDWR = memSpec->tCK * queryUIntParameter(timings, "RCDWR");
memSpec->tRTP = memSpec->tCK * queryUIntParameter(timings, "RTP");
memSpec->tRRDS = memSpec->tCK * queryUIntParameter(timings, "RRDS");
memSpec->tRRDL = memSpec->tCK * queryUIntParameter(timings, "RRDL");
memSpec->tCCDS = memSpec->tCK * queryUIntParameter(timings, "CCDS");
memSpec->tCCDL = memSpec->tCK * queryUIntParameter(timings, "CCDL");
memSpec->tRL = memSpec->tCK * queryUIntParameter(timings, "RL");
memSpec->tWCK2CKPIN = memSpec->tCK * queryUIntParameter(timings, "WCK2CKPIN");
memSpec->tWCK2CK = memSpec->tCK * queryUIntParameter(timings, "WCK2CK");
memSpec->tWCK2DQO = memSpec->tCK * queryUIntParameter(timings, "WCK2DQO");
memSpec->tRTW = memSpec->tCK * queryUIntParameter(timings, "RTW");
memSpec->tWL = memSpec->tCK * queryUIntParameter(timings, "WL");
memSpec->tWCK2DQI = memSpec->tCK * queryUIntParameter(timings, "WCK2DQI");
memSpec->tWR = memSpec->tCK * queryUIntParameter(timings, "WR");
memSpec->tWTRS = memSpec->tCK * queryUIntParameter(timings, "WTRS");
memSpec->tWTRL = memSpec->tCK * queryUIntParameter(timings, "WTRL");
memSpec->tCKE = memSpec->tCK * queryUIntParameter(timings, "CKE");
std::string timings = "memtimingspec";
memSpec->tRP = memSpec->tCK * uIntParameter(j[timings]["RP"], "RP");
memSpec->tRAS = memSpec->tCK * uIntParameter(j[timings]["RAS"], "RAS");
memSpec->tRC = memSpec->tCK * uIntParameter(j[timings]["RC"], "RC");
memSpec->tRCDRD = memSpec->tCK * uIntParameter(j[timings]["RCDRD"], "RCDRD");
memSpec->tRCDWR = memSpec->tCK * uIntParameter(j[timings]["RCDWR"], "RCDWR");
memSpec->tRTP = memSpec->tCK * uIntParameter(j[timings]["RTP"], "RTP");
memSpec->tRRDS = memSpec->tCK * uIntParameter(j[timings]["RRDS"], "RRDS");
memSpec->tRRDL = memSpec->tCK * uIntParameter(j[timings]["RRDL"], "RRDL");
memSpec->tCCDS = memSpec->tCK * uIntParameter(j[timings]["CCDS"], "CCDS");
memSpec->tCCDL = memSpec->tCK * uIntParameter(j[timings]["CCDL"], "CCDL");
memSpec->tRL = memSpec->tCK * uIntParameter(j[timings]["RL"], "RL");
memSpec->tWCK2CKPIN = memSpec->tCK * uIntParameter(j[timings]["WCK2CKPIN"], "WCK2CKPIN");
memSpec->tWCK2CK = memSpec->tCK * uIntParameter(j[timings]["WCK2CK"], "WCK2CK");
memSpec->tWCK2DQO = memSpec->tCK * uIntParameter(j[timings]["WCK2DQO"], "WCK2DQO");
memSpec->tRTW = memSpec->tCK * uIntParameter(j[timings]["RTW"], "RTW");
memSpec->tWL = memSpec->tCK * uIntParameter(j[timings]["WL"], "WL");
memSpec->tWCK2DQI = memSpec->tCK * uIntParameter(j[timings]["WCK2DQI"], "WCK2DQI");
memSpec->tWR = memSpec->tCK * uIntParameter(j[timings]["WR"], "WR");
memSpec->tWTRS = memSpec->tCK * uIntParameter(j[timings]["WTRS"], "WTRS");
memSpec->tWTRL = memSpec->tCK * uIntParameter(j[timings]["WTRL"], "WTRL");
memSpec->tCKE = memSpec->tCK * uIntParameter(j[timings]["CKE"], "CKE");
memSpec->tPD = memSpec->tCKE;
memSpec->tCKESR = memSpec->tCK * queryUIntParameter(timings, "CKESR");
memSpec->tXP = memSpec->tCK * queryUIntParameter(timings, "XP");
memSpec->tREFI = memSpec->tCK * queryUIntParameter(timings, "REFI");
memSpec->tREFIPB = memSpec->tCK * queryUIntParameter(timings, "REFIPB");
memSpec->tRFC = memSpec->tCK * queryUIntParameter(timings, "RFC");
memSpec->tRFCPB = memSpec->tCK * queryUIntParameter(timings, "RFCPB");
memSpec->tRREFD = memSpec->tCK * queryUIntParameter(timings, "RREFD");
memSpec->tXS = memSpec->tCK * queryUIntParameter(timings, "XS");
memSpec->tFAW = memSpec->tCK * queryUIntParameter(timings, "FAW");
memSpec->tCKESR = memSpec->tCK * uIntParameter(j[timings]["CKESR"], "CKESR");
memSpec->tXP = memSpec->tCK * uIntParameter(j[timings]["XP"], "XP");
memSpec->tREFI = memSpec->tCK * uIntParameter(j[timings]["REFI"], "REFI");
memSpec->tREFIPB = memSpec->tCK * uIntParameter(j[timings]["REFIPB"], "REFIPB");
memSpec->tRFC = memSpec->tCK * uIntParameter(j[timings]["RFC"], "RFC");
memSpec->tRFCPB = memSpec->tCK * uIntParameter(j[timings]["RFCPB"], "RFCPB");
memSpec->tRREFD = memSpec->tCK * uIntParameter(j[timings]["RREFD"], "RREFD");
memSpec->tXS = memSpec->tCK * uIntParameter(j[timings]["XS"], "XS");
memSpec->tFAW = memSpec->tCK * uIntParameter(j[timings]["FAW"], "FAW");
memSpec->tRDSRE = memSpec->tRL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQO + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tWRSRE = memSpec->tWL + memSpec->tWCK2CKPIN + memSpec->tWCK2CK
+ memSpec->tWCK2DQI + memSpec->burstLength / memSpec->dataRate * memSpec->tCK;
memSpec->tPPD = memSpec->tCK * queryUIntParameter(timings, "PPD");
memSpec->tLK = memSpec->tCK * queryUIntParameter(timings, "LK");
memSpec->tACTPDE = memSpec->tCK * queryUIntParameter(timings, "ACTPDE");
memSpec->tPREPDE = memSpec->tCK * queryUIntParameter(timings, "PREPDE");
memSpec->tREFPDE = memSpec->tCK * queryUIntParameter(timings, "REFPDE");
memSpec->tPPD = memSpec->tCK * uIntParameter(j[timings]["PPD"], "PPD");
memSpec->tLK = memSpec->tCK * uIntParameter(j[timings]["LK"], "LK");
memSpec->tACTPDE = memSpec->tCK * uIntParameter(j[timings]["ACTPDE"], "ACTPDE");
memSpec->tPREPDE = memSpec->tCK * uIntParameter(j[timings]["PREPDE"], "PREPDE");
memSpec->tREFPDE = memSpec->tCK * uIntParameter(j[timings]["REFPDE"], "REFPDE");
// Currents and voltages
// TODO: to be completed

22
DRAMSys/library/src/configuration/ConfigurationLoader.h
View File

@@ -57,7 +57,7 @@ public:
tinyxml2::XMLElement *simconfig);
static void loadMemSpec(Configuration &config, std::string memspecUri);
static void loadMemSpec(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadMemSpec(Configuration &config, nlohmann::json::object_t *memspec);
static void loadTemperatureSimConfig(Configuration &config,
std::string simconfigUri);
@@ -70,17 +70,17 @@ private:
static void loadConfigFromUri(Configuration &config, std::string uri,
std::string first_element);
// Loads common config of DRAMs
static void loadCommons(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadCommons(Configuration &config, nlohmann::json::object_t *memspec);
// Load specific config
static void loadDDR3(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadDDR4(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadLPDDR4(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadWideIO(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadWideIO2(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadHBM2(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadGDDR5(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadGDDR5X(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadGDDR6(Configuration &config, tinyxml2::XMLElement *memspec);
static void loadDDR3(Configuration &config, nlohmann::json::object_t *memspec);
static void loadDDR4(Configuration &config, nlohmann::json::object_t *memspec);
static void loadLPDDR4(Configuration &config, nlohmann::json::object_t *memspec);
static void loadWideIO(Configuration &config, nlohmann::json::object_t *memspec);
static void loadWideIO2(Configuration &config, nlohmann::json::object_t *memspec);
static void loadHBM2(Configuration &config, nlohmann::json::object_t *memspec);
static void loadGDDR5(Configuration &config, nlohmann::json::object_t *memspec);
static void loadGDDR5X(Configuration &config, nlohmann::json::object_t *memspec);
static void loadGDDR6(Configuration &config, nlohmann::json::object_t *memspec);
};

2
README.md
View File

@@ -211,7 +211,7 @@ The XML code below shows a typic configuration:
```
Some configuration fields reference other XML files which contain more
specialized chunks of the configuration like memory specification, address
mapping and memory configurations.
mapping and memory configurations
The XML configuration files are parsed by the program and the configuration
details extracted are assigned to the correspondent attributes of the internal