Merge branch 'develop' into 'feat/internal_length_conv2'

Rebase to current develop

See merge request ems/astdm/modeling.dram/dram.sys!358

DRAMSys/traceAnalyzer/CMakeLists.txt

@@ -76,6 +76,7 @@ add_executable(TraceAnalyzer
     data/tracedb.cpp
     presentation/tracenavigator.cpp
     presentation/util/colorgenerator.cpp
+    presentation/util/colorobject.cpp
     presentation/tracedrawing.cpp
     presentation/traceplotitem.cpp
     gototimedialog.cpp
@@ -94,9 +95,7 @@ add_executable(TraceAnalyzer
     selectmetrics.cpp
     presentation/util/testlight.cpp
     presentation/util/togglecollapsedaction.cpp
-    presentation/tracetesttreewidget.cpp
     businessObjects/pythoncaller.cpp
-    businessObjects/tracetestresults.cpp
     presentation/tracemetrictreewidget.cpp
     businessObjects/phases/phase.cpp
     businessObjects/phases/phasedependency.cpp
@@ -107,6 +106,42 @@ add_executable(TraceAnalyzer
     businessObjects/commentmodel.cpp
     businessObjects/traceplotlinemodel.cpp
     simulationdialog.cpp
+    businessObjects/dependencymodels.cpp
+
+    businessObjects/dramTimeDependencies/common/QStringComparator.cpp
+    businessObjects/dramTimeDependencies/common/StringMapper.cpp
+    businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.cpp
+    businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp
+    businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.cpp
+    businessObjects/dramTimeDependencies/configurations/configurationBase.cpp
+    
+    businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp
+    # businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp
+    businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp
+    businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp
+    
+    businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp
+    businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp
+    businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp
+
+    businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp
+    businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp
+    businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp
+
+    businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp
+    businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp
+    businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.cpp
+
+    businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp
+    businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp
+    businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp
+
+    businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp
+    businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp
+    businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.cpp
+
+    businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp
+    businessObjects/dramTimeDependencies/phasedependenciestracker.cpp
 
     selectmetrics.ui
     preferences.ui

DRAMSys/traceAnalyzer/businessObjects/configmodels.cpp

@@ -31,7 +31,6 @@
  *
  * Authors:
  *    Derek Christ
- *    Iron Prando da Silva
  */
 
 #include "configmodels.h"
@@ -283,142 +282,3 @@ QModelIndex MemSpecModel::parent(const QModelIndex &index) const
 
     return createIndex(parentNode->getRow(), 0, const_cast<Node *>(parentNode));
 }
-
-DependencyInfosModel::DependencyInfosModel(TraceDB &traceFile, QObject *parent) : QAbstractItemModel(parent)
-{
-    mDepInfosDepType = traceFile.getDependencyInfos(DependencyInfos::Type::DependencyType);
-    mDepInfosTimeDep = traceFile.getDependencyInfos(DependencyInfos::Type::TimeDependency);
-    mDepInfosDelPhase = traceFile.getDependencyInfos(DependencyInfos::Type::DelayedPhase);
-    mDepInfosDepPhase = traceFile.getDependencyInfos(DependencyInfos::Type::DependencyPhase);
-
-    if (traceFile.checkDependencyTableExists())
-    {
-        parseInfos();
-    }
-}
-
-int DependencyInfosModel::Node::getRow() const
-{
-    if (!parent)
-        return 0;
-
-    const auto &siblings = parent->children;
-    const auto siblingsIt = std::find_if(siblings.begin(), siblings.end(),
-                                         [this](const std::unique_ptr<Node> &node) { return node.get() == this; });
-
-    Q_ASSERT(siblingsIt != siblings.end());
-
-    return std::distance(siblings.begin(), siblingsIt);
-}
-
-void DependencyInfosModel::parseInfos()
-{
-
-    std::vector<std::pair<QString, DependencyInfos &>> infos = {{"Dependency Granularity", mDepInfosDepType},
-                                                                {"Time Dependencies", mDepInfosTimeDep},
-                                                                {"Delayed Phases", mDepInfosDelPhase},
-                                                                {"Dependency Phases", mDepInfosDepPhase}};
-
-    for (auto pair : infos)
-    {
-        std::unique_ptr<Node> node = std::unique_ptr<Node>(new Node({pair.first, ""}, rootNode.get()));
-
-        for (auto v : pair.second.getInfos())
-        {
-            QString value = QString::number(v.value) + " %";
-            node->children.push_back(std::move(std::unique_ptr<Node>(new Node({v.id, value}, node.get()))));
-        }
-
-        rootNode->children.push_back(std::move(node));
-    }
-}
-
-int DependencyInfosModel::rowCount(const QModelIndex &parent) const
-{
-    if (parent.column() > 0)
-        return 0;
-
-    const Node *parentNode;
-
-    if (!parent.isValid())
-        parentNode = rootNode.get();
-    else
-        parentNode = static_cast<const Node *>(parent.internalPointer());
-
-    return parentNode->childCount();
-}
-
-int DependencyInfosModel::columnCount(const QModelIndex &parent) const
-{
-    Q_UNUSED(parent)
-
-    return 2;
-}
-
-QVariant DependencyInfosModel::data(const QModelIndex &index, int role) const
-{
-    if (!index.isValid())
-        return QVariant();
-
-    if (role != Qt::DisplayRole && role != Qt::ToolTipRole)
-        return QVariant();
-
-    auto *node = static_cast<const Node *>(index.internalPointer());
-
-    if (index.column() == 0)
-        return QVariant(node->data.first);
-    else
-        return QVariant(node->data.second);
-}
-
-QVariant DependencyInfosModel::headerData(int section, Qt::Orientation orientation, int role) const
-{
-    if (role != Qt::DisplayRole)
-        return QVariant();
-
-    if (orientation == Qt::Horizontal)
-    {
-        switch (section)
-        {
-        case 0:
-            return "Field";
-        case 1:
-            return "Percentage";
-        default:
-            break;
-        }
-    }
-
-    return QVariant();
-}
-
-QModelIndex DependencyInfosModel::index(int row, int column, const QModelIndex &parent) const
-{
-    if (!hasIndex(row, column, parent))
-        return QModelIndex();
-
-    const Node *parentNode;
-
-    if (!parent.isValid())
-        parentNode = rootNode.get();
-    else
-        parentNode = static_cast<const Node *>(parent.internalPointer());
-
-    const Node *node = parentNode->children[row].get();
-
-    return createIndex(row, column, const_cast<Node *>(node));
-}
-
-QModelIndex DependencyInfosModel::parent(const QModelIndex &index) const
-{
-    if (!index.isValid())
-        return QModelIndex();
-
-    const Node *childNode = static_cast<const Node *>(index.internalPointer());
-    const Node *parentNode = childNode->parent;
-
-    if (!parentNode)
-        return QModelIndex();
-
-    return createIndex(parentNode->getRow(), 0, const_cast<Node *>(parentNode));
-}

DRAMSys/traceAnalyzer/businessObjects/configmodels.h

@@ -31,7 +31,6 @@
  *
  * Authors:
  *    Derek Christ
- *    Iron Prando da Silva
  */
 
 #ifndef CONFIGMODELS_H
@@ -126,59 +125,4 @@ private:
     std::unique_ptr<Node> rootNode = std::unique_ptr<Node>(new Node);
 };
 
-class DependencyInfosModel : public QAbstractItemModel
-{
-    Q_OBJECT
-public:
-    explicit DependencyInfosModel(TraceDB &traceFile, QObject *parent = nullptr);
-    ~DependencyInfosModel()
-    {
-    }
-
-protected:
-    int rowCount(const QModelIndex &parent = QModelIndex()) const override;
-    int columnCount(const QModelIndex &parent) const override;
-
-    QVariant data(const QModelIndex &index, int role = Qt::DisplayRole) const override;
-    QVariant headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const override;
-
-    QModelIndex index(int row, int column, const QModelIndex &parent) const override;
-    QModelIndex parent(const QModelIndex &index) const override;
-
-private:
-    DependencyInfos mDepInfosDepType;
-    DependencyInfos mDepInfosTimeDep;
-    DependencyInfos mDepInfosDelPhase;
-    DependencyInfos mDepInfosDepPhase;
-
-    void parseInfos();
-    struct Node
-    {
-        using NodeData = std::pair<QString, QString>;
-
-        Node()
-        {
-        }
-        Node(NodeData data, const Node *parent) : data(data), parent(parent)
-        {
-        }
-
-        /**
-         * Gets the row relative to its parent.
-         */
-        int getRow() const;
-        int childCount() const
-        {
-            return children.size();
-        }
-
-        NodeData data;
-
-        const Node *parent = nullptr;
-        std::vector<std::unique_ptr<Node>> children;
-    };
-
-    std::unique_ptr<Node> rootNode = std::unique_ptr<Node>(new Node);
-};
-
 #endif // CONFIGMODELS_H

DRAMSys/traceAnalyzer/businessObjects/dependencymodels.cpp

@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "dependencymodels.h"
+
+DependencyInfosModel::DependencyInfosModel(TraceDB &traceFile, QObject *parent) : QAbstractItemModel(parent)
+{
+    mDepInfosDepType = traceFile.getDependencyInfos(DependencyInfos::Type::DependencyType);
+    mDepInfosTimeDep = traceFile.getDependencyInfos(DependencyInfos::Type::TimeDependency);
+    mDepInfosDelPhase = traceFile.getDependencyInfos(DependencyInfos::Type::DelayedPhase);
+    mDepInfosDepPhase = traceFile.getDependencyInfos(DependencyInfos::Type::DependencyPhase);
+
+    if (traceFile.checkDependencyTableExists())
+    {
+        parseInfos();
+    }
+}
+
+int DependencyInfosModel::Node::getRow() const
+{
+    if (!parent)
+        return 0;
+
+    const auto &siblings = parent->children;
+    const auto siblingsIt = std::find_if(siblings.begin(), siblings.end(),
+                                         [this](const std::unique_ptr<Node> &node) { return node.get() == this; });
+
+    Q_ASSERT(siblingsIt != siblings.end());
+
+    return std::distance(siblings.begin(), siblingsIt);
+}
+
+void DependencyInfosModel::parseInfos()
+{
+
+    std::vector<std::pair<QString, DependencyInfos &>> infos = {{"Dependency Granularity", mDepInfosDepType},
+                                                                {"Time Dependencies", mDepInfosTimeDep},
+                                                                {"Delayed Phases", mDepInfosDelPhase},
+                                                                {"Dependency Phases", mDepInfosDepPhase}};
+
+    for (auto pair : infos)
+    {
+        std::unique_ptr<Node> node = std::unique_ptr<Node>(new Node({pair.first, ""}, rootNode.get()));
+
+        for (auto v : pair.second.getInfos())
+        {
+            QString value = QString::number(v.value) + " %";
+            node->children.push_back(std::move(std::unique_ptr<Node>(new Node({v.id, value}, node.get()))));
+        }
+
+        rootNode->children.push_back(std::move(node));
+    }
+}
+
+int DependencyInfosModel::rowCount(const QModelIndex &parent) const
+{
+    if (parent.column() > 0)
+        return 0;
+
+    const Node *parentNode;
+
+    if (!parent.isValid())
+        parentNode = rootNode.get();
+    else
+        parentNode = static_cast<const Node *>(parent.internalPointer());
+
+    return parentNode->childCount();
+}
+
+int DependencyInfosModel::columnCount(const QModelIndex &parent) const
+{
+    Q_UNUSED(parent)
+
+    return 2;
+}
+
+QVariant DependencyInfosModel::data(const QModelIndex &index, int role) const
+{
+    if (!index.isValid())
+        return QVariant();
+
+    if (role != Qt::DisplayRole && role != Qt::ToolTipRole)
+        return QVariant();
+
+    auto *node = static_cast<const Node *>(index.internalPointer());
+
+    if (index.column() == 0)
+        return QVariant(node->data.first);
+    else
+        return QVariant(node->data.second);
+}
+
+QVariant DependencyInfosModel::headerData(int section, Qt::Orientation orientation, int role) const
+{
+    if (role != Qt::DisplayRole)
+        return QVariant();
+
+    if (orientation == Qt::Horizontal)
+    {
+        switch (section)
+        {
+        case 0:
+            return "Field";
+        case 1:
+            return "Percentage";
+        default:
+            break;
+        }
+    }
+
+    return QVariant();
+}
+
+QModelIndex DependencyInfosModel::index(int row, int column, const QModelIndex &parent) const
+{
+    if (!hasIndex(row, column, parent))
+        return QModelIndex();
+
+    const Node *parentNode;
+
+    if (!parent.isValid())
+        parentNode = rootNode.get();
+    else
+        parentNode = static_cast<const Node *>(parent.internalPointer());
+
+    const Node *node = parentNode->children[row].get();
+
+    return createIndex(row, column, const_cast<Node *>(node));
+}
+
+QModelIndex DependencyInfosModel::parent(const QModelIndex &index) const
+{
+    if (!index.isValid())
+        return QModelIndex();
+
+    const Node *childNode = static_cast<const Node *>(index.internalPointer());
+    const Node *parentNode = childNode->parent;
+
+    if (!parentNode)
+        return QModelIndex();
+
+    return createIndex(parentNode->getRow(), 0, const_cast<Node *>(parentNode));
+}

DRAMSys/traceAnalyzer/businessObjects/dependencymodels.h

@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "../data/tracedb.h"
+#include "phases/dependencyinfos.h"
+
+#include <QAbstractTableModel>
+#include <QListWidget>
+#include <vector>
+#include <utility>
+
+class DependencyInfosModel : public QAbstractItemModel
+{
+    Q_OBJECT
+public:
+    explicit DependencyInfosModel(TraceDB &traceFile, QObject *parent = nullptr);
+    ~DependencyInfosModel()
+    {
+    }
+
+protected:
+    int rowCount(const QModelIndex &parent = QModelIndex()) const override;
+    int columnCount(const QModelIndex &parent) const override;
+
+    QVariant data(const QModelIndex &index, int role = Qt::DisplayRole) const override;
+    QVariant headerData(int section, Qt::Orientation orientation, int role = Qt::DisplayRole) const override;
+
+    QModelIndex index(int row, int column, const QModelIndex &parent) const override;
+    QModelIndex parent(const QModelIndex &index) const override;
+
+private:
+    DependencyInfos mDepInfosDepType;
+    DependencyInfos mDepInfosTimeDep;
+    DependencyInfos mDepInfosDelPhase;
+    DependencyInfos mDepInfosDepPhase;
+
+    void parseInfos();
+    struct Node
+    {
+        using NodeData = std::pair<QString, QString>;
+
+        Node()
+        {
+        }
+        Node(NodeData data, const Node *parent) : data(data), parent(parent)
+        {
+        }
+
+        /**
+         * Gets the row relative to its parent.
+         */
+        int getRow() const;
+        int childCount() const
+        {
+            return children.size();
+        }
+
+        NodeData data;
+
+        const Node *parent = nullptr;
+        std::vector<std::unique_ptr<Node>> children;
+    };
+
+    std::unique_ptr<Node> rootNode = std::unique_ptr<Node>(new Node);
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/README.md

@@ -0,0 +1,53 @@
+
+## Relevant classes
+```
+PhaseDependenciesTracker
+├── ConfigurationFactory
+│   └── ConfigurationBase
+│       ├── DBPhaseEntryBase
+│       └── DRAMTimeDependenciesBase
+│           ├── DependencyMap
+│           │   └── PhaseTimeDependencies
+│           └── PoolControllerMap
+└── DBDependencyEntry
+```
+
+#### PhaseDependenciesTracker
+Responsible for the whole execution. Instantiates a configuration class through the ConfigurationFactory, loads the selected phases into memory, calculates the time dependencies between phases and saves into the database file.
+
+#### ConfigurationFactory
+Creates a configuration object given its name.
+
+#### ConfigurationBase
+Interface and common functionality of configuration classes. These include creating DBPhaseEntryBase objects from the database for the given device and delegate methods.
+
+#### DBPhaseEntryBase
+Interfaces to device specific phase entries. Specificities include object data, construction and dependency logic.
+
+#### DRAMTimeDependenciesBase
+Interfaces to device's time dependencies descriptor class.
+
+#### DependencyMap
+A STL map using auxiliar objects. Maps phases to their PhaseTimeDependencies.
+
+#### PhaseTimeDependencies
+An auxiliar class with initializer list constructor. Contains a vector of TimeDependency objects and its maximum time value.
+
+#### PoolControllerMap
+Maps pool names to PoolController objects. Pools keep track of all potential dependencies of a given phase.
+
+#### DBDependencyEntry
+Contains the data to be written to the database.
+
+
+## Suggested steps for creating a device:
+1. Create a time dependencies class inheriting from the DRAMTimeDependenciesBase object.
+2. Create the phase entry object inheriting from DBPhaseEntryBase. The object must determine the relevant data to be used and how phases may be correlated.
+3. Create a configuration class for your object inheriting from ConfigurationBase. This will contain the dependencies maps and instantiate the specialized DBPhaseEntryBase object.
+4. Add the newly created device to the functions of the ConfigurationFactory class. The device name is taken from the database.
+
+#### Example
+For instance, we have the necessary objects for calculating DDR3 device dependencies implemented in the following files:
+1. deviceDependencies/specialized/TimeDependenciesInfoDDR3.(h/cpp)
+2. dbEntries/specialized/DDR3dbphaseentry.(h/cpp)
+3. configurations/specialized/DDR3Configuration.(h/cpp)

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/QStringComparator.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, Technische Universität Kaiserslautern
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,19 +30,15 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors:
- *    Janik Schlemminger
- *    Robert Gernhardt
- *    Matthias Jung
+ *    Iron Prando da Silva
  */
 
-#include "tracetestresults.h"
+#include "QStringComparator.h"
 
-
-bool TraceTestResults::hasPassedAllTests() const
-{
-    for (const TestResult &testResult : testResults) {
-        if (!testResult.hasPassed())
-            return false;
-    }
-    return true;
+bool QStringsComparator::operator()(const QString& s1, const QString& s2) const {
+    return s1.compare(s2) < 0;
 }
+
+bool QStringsComparator::compareQStrings(const QString& s1, const QString& s2) {
+    return s1.compare(s2) < 0;
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/QStringComparator.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include <QString>
+
+struct QStringsComparator {
+    bool operator()(const QString& s1, const QString& s2) const;
+    static bool compareQStrings(const QString& s1, const QString& s2);
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.cpp

@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "StringMapper.h"
+
+StringMapper::StringMapper(const QString& name) {
+    mIDEnum = getIDEnum(name);
+    mIDStr = name;
+    mIsPool = mAuxIsPool(mIDEnum);
+
+}
+
+QString StringMapper::getIDStr(StringMapper::Identifier id) {
+    static const std::map<StringMapper::Identifier, QString> enumToStr {
+        {StringMapper::Identifier::CMD_BUS, "CMD_BUS"},
+        {StringMapper::Identifier::RAS_BUS, "RAS_BUS"},
+        {StringMapper::Identifier::CAS_BUS, "CAS_BUS"},
+        {StringMapper::Identifier::NAW, "NAW"},
+        {StringMapper::Identifier::FAW, "FAW"},
+        {StringMapper::Identifier::_32AW, "32AW"},
+        {StringMapper::Identifier::FAW_LOGICAL, "FAW_LOGICAL"},
+        {StringMapper::Identifier::FAW_PHYSICAL, "FAW_PHYSICAL"},
+        {StringMapper::Identifier::REFAB, "REFAB"},
+        {StringMapper::Identifier::PREAB, "PREAB"},
+        {StringMapper::Identifier::PDEP, "PDEP"},
+        {StringMapper::Identifier::PDXP, "PDXP"},
+        {StringMapper::Identifier::SREFEN, "SREFEN"},
+        {StringMapper::Identifier::SREFEX, "SREFEX"},
+        {StringMapper::Identifier::PDEA, "PDEA"},
+        {StringMapper::Identifier::PDXA, "PDXA"},
+        {StringMapper::Identifier::SRPDEN, "SRPDEN"},
+        {StringMapper::Identifier::SRPDEX, "SRPDEX"},
+        {StringMapper::Identifier::ACT, "ACT"},
+        {StringMapper::Identifier::RD, "RD"},
+        {StringMapper::Identifier::WR, "WR"},
+        {StringMapper::Identifier::PREPB, "PREPB"},
+        {StringMapper::Identifier::RDA, "RDA"},
+        {StringMapper::Identifier::WRA, "WRA"},
+        {StringMapper::Identifier::REFPB, "REFPB"},
+        {StringMapper::Identifier::REFP2B, "REFP2B"},
+        {StringMapper::Identifier::PRESB, "PRESB"},
+        {StringMapper::Identifier::RFMAB, "RFMAB"},
+        {StringMapper::Identifier::REFSB, "REFSB"},
+        {StringMapper::Identifier::RFMSB, "RFMSB"},
+    };
+
+    auto it = enumToStr.find(id);
+    if (it != enumToStr.end()) return it->second;
+    else throw std::invalid_argument("The provided StringMapper::StringMapper::Identifier is not valid.");
+
+}
+
+StringMapper::Identifier StringMapper::getIDEnum(const QString& id) {
+    static const std::map<QString, StringMapper::Identifier, QStringsComparator> strToEnum {
+        {"CMD_BUS", StringMapper::Identifier::CMD_BUS},
+        {"RAS_BUS", StringMapper::Identifier::RAS_BUS},
+        {"CAS_BUS", StringMapper::Identifier::CAS_BUS},
+        {"NAW", StringMapper::Identifier::NAW},
+        {"FAW", StringMapper::Identifier::FAW},
+        {"32AW", StringMapper::Identifier::_32AW},
+        {"FAW_LOGICAL", StringMapper::Identifier::FAW_LOGICAL},
+        {"FAW_PHYSICAL", StringMapper::Identifier::FAW_PHYSICAL},
+        {"REFAB", StringMapper::Identifier::REFAB},
+        {"PREAB", StringMapper::Identifier::PREAB},
+        {"PDEP", StringMapper::Identifier::PDEP},
+        {"PDXP", StringMapper::Identifier::PDXP},
+        {"SREFEN", StringMapper::Identifier::SREFEN},
+        {"SREFEX", StringMapper::Identifier::SREFEX},
+        {"PDEA", StringMapper::Identifier::PDEA},
+        {"PDXA", StringMapper::Identifier::PDXA},
+        {"SRPDEN", StringMapper::Identifier::SRPDEN},
+        {"SRPDEX", StringMapper::Identifier::SRPDEX},
+        {"ACT", StringMapper::Identifier::ACT},
+        {"RD", StringMapper::Identifier::RD},
+        {"WR", StringMapper::Identifier::WR},
+        {"PREPB", StringMapper::Identifier::PREPB},
+        {"RDA", StringMapper::Identifier::RDA},
+        {"WRA", StringMapper::Identifier::WRA},
+        {"REFPB", StringMapper::Identifier::REFPB},
+        {"REFP2B", StringMapper::Identifier::REFP2B},
+        {"PRESB", StringMapper::Identifier::PRESB},
+        {"RFMAB", StringMapper::Identifier::RFMAB},
+        {"REFSB", StringMapper::Identifier::REFSB},
+        {"RFMSB", StringMapper::Identifier::RFMSB},
+    };
+
+    auto it = strToEnum.find(id);
+    if (it != strToEnum.end()) return it->second;
+    else throw std::invalid_argument("The provided StringMapper::Identifier '" + id.toStdString() + "' is not valid.");
+
+}
+
+bool StringMapper::mAuxIsPool(StringMapper::Identifier id) {
+    return id == StringMapper::Identifier::CMD_BUS
+            || id == StringMapper::Identifier::RAS_BUS
+            || id == StringMapper::Identifier::CAS_BUS
+            || id == StringMapper::Identifier::NAW
+            || id == StringMapper::Identifier::FAW
+            || id == StringMapper::Identifier::_32AW
+            || id == StringMapper::Identifier::FAW_LOGICAL
+            || id == StringMapper::Identifier::FAW_PHYSICAL;
+
+}
+
+bool StringMapper::operator==(const StringMapper& str2) const {
+    return mIDEnum == str2.mIDEnum;
+}
+
+bool StringMapper::operator!=(const StringMapper& str2) const {
+    return mIDEnum != str2.mIDEnum;
+}
+
+bool StringMapper::operator<(const StringMapper& str2) const {
+    return mIDEnum < str2.mIDEnum;
+}
+
+bool StringMapper::compare(const StringMapper& str1, const StringMapper& str2) {
+    return str1.getIDEnum() < str2.getIDEnum();
+}
+
+bool StringMapper::operator==(const StringMapper::Identifier& id) const {
+    return mIDEnum == id;
+}
+
+bool StringMapper::operator!=(const StringMapper::Identifier& id) const {
+    return mIDEnum != id;
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/StringMapper.h

@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include <map>
+#include "QStringComparator.h"
+
+class StringMapper {
+ public: 
+   enum Identifier {
+      None,
+      CMD_BUS,
+      RAS_BUS,
+      CAS_BUS,
+      NAW,
+      FAW,
+      _32AW,
+      FAW_LOGICAL,
+      FAW_PHYSICAL,
+      REFAB,
+      PREAB,
+      PDEP,
+      PDXP,
+      SREFEN,
+      SREFEX,
+      PDEA,
+      PDXA,
+      SRPDEN,
+      SRPDEX,
+      ACT,
+      RD,
+      WR,
+      PREPB,
+      RDA, 
+      WRA,
+      REFPB,
+      REFP2B,
+      PRESB,
+      RFMAB,
+      REFSB,
+      RFMSB
+   };
+
+ public:
+   StringMapper() = default;
+   StringMapper(const QString& id);
+   StringMapper(const char* str) : StringMapper(std::forward<QString>(str)) {}
+   ~StringMapper() = default;
+
+   Identifier getIDEnum() const { return mIDEnum; }
+   const QString getIDStr() const { return mIDStr; }
+
+   bool isPool() const { return mIsPool; }
+
+   static QString getIDStr(Identifier);
+   static Identifier getIDEnum(const QString&);
+
+   bool operator==(const StringMapper&) const;
+   bool operator!=(const StringMapper&) const;
+   bool operator<(const StringMapper&) const;
+   
+   bool operator==(const Identifier&) const;
+   bool operator!=(const Identifier&) const;
+
+   static bool compare(const StringMapper&, const StringMapper&);
+
+ protected:
+   Identifier mIDEnum = None;
+   QString mIDStr = "";
+   bool mIsPool = false;
+
+ protected:
+   static bool mAuxIsPool(Identifier);
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/common.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include <algorithm>
+#include <vector>
+#include <map>
+
+#include <QString>
+#include <QJsonDocument>
+#include <QJsonValue>
+#include <QJsonArray>
+#include <QJsonObject>
+
+#include "businessObjects/phases/phasedependency.h"
+#include "timedependency.h"
+
+struct PhaseTimeDependencies {
+    explicit PhaseTimeDependencies(std::initializer_list<TimeDependency> d) : dependencies(d) {}
+
+    std::vector<TimeDependency> dependencies;
+    size_t maxTime;
+};
+
+typedef std::map<StringMapper, PhaseTimeDependencies> DependencyMap;
+
+struct DBDependencyEntry {
+    size_t delayedPhaseID;
+    QString delayedPhaseName;
+    QString dependencyType;
+    QString timeDependency;
+    size_t dependencyPhaseID;
+    QString dependencyPhaseName;
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/common/timedependency.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include <QString>
+#include "StringMapper.h"
+
+class TimeDependency {
+public:
+    TimeDependency() = default;
+    TimeDependency(size_t timeValue, QString phaseDep, DependencyType depType, 
+                   QString timeDepName, bool considerIntraRank = false)
+    : timeValue{timeValue}, phaseDep{phaseDep}, depType{depType}, 
+      timeDepName{timeDepName} {}
+
+    size_t timeValue;
+    StringMapper phaseDep;
+    DependencyType depType;
+    QString timeDepName;
+
+    bool isPool() { return phaseDep.isPool(); }
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.cpp

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "configurationBase.h"
+
+const uint ConfigurationBase::getClk() const {
+    if (!mDeviceDeps) 
+        throw std::invalid_argument("Invalid DRAMTimeDependenciesBase object in 'ConfigurationBase::getClk'.");
+
+    return mDeviceDeps->getClk();
+}
+
+DependencyMap ConfigurationBase::getDependencies(std::vector<QString>& commands) const {
+    if (!mDeviceDeps) 
+        throw std::invalid_argument("Invalid DRAMTimeDependenciesBase object in 'ConfigurationBase::getDependencies'.");
+
+    return mDeviceDeps->getDependencies(commands);
+}
+
+PoolControllerMap ConfigurationBase::getPools() const {
+    if (!mDeviceDeps) 
+        throw std::invalid_argument("Invalid DRAMTimeDependenciesBase object in 'ConfigurationBase::getAWPools'.");
+
+    return mDeviceDeps->getPools();
+}
+
+const QString ConfigurationBase::getDeviceName(const TraceDB& tdb) {
+    return mGetMemspec(tdb)["memoryType"].toString();
+}
+
+const uint ConfigurationBase::mGetClk(const TraceDB& tdb) {
+    QSqlDatabase db = tdb.getDatabase();
+    QString query = "SELECT clk FROM GeneralInfo";
+    QSqlQuery sqlQuery = db.exec(query);
+
+    sqlQuery.next();
+    uint clock = sqlQuery.value(0).toLongLong();
+    sqlQuery.finish();
+
+    return clock;
+}
+
+const QJsonObject ConfigurationBase::mGetMemspec(const TraceDB& tdb) {
+    QSqlDatabase db = tdb.getDatabase();
+    QString query = "SELECT Memspec FROM GeneralInfo";
+    QSqlQuery sqlQuery = db.exec(query);
+
+    sqlQuery.next();
+    QString memSpecJson = sqlQuery.value(0).toString();
+    sqlQuery.finish();
+
+    QJsonDocument jsonDocument = QJsonDocument::fromJson(memSpecJson.toUtf8());
+
+    return jsonDocument.object()["memspec"].toObject();
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationBase.h

@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include <QSqlQuery>
+
+#include "businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.h"
+#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h"
+
+class ConfigurationBase {
+ public:
+    ConfigurationBase() {};
+    virtual ~ConfigurationBase() = default;
+
+    virtual std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const { return nullptr; }
+    
+    // Delegated methods
+    const uint getClk() const;
+    DependencyMap getDependencies(std::vector<QString>& commands) const;
+    PoolControllerMap getPools() const;
+
+    static const QString getDeviceName(const TraceDB& tdb);
+
+ protected:
+    std::shared_ptr<DRAMTimeDependenciesBase> mDeviceDeps = nullptr;
+
+    static const uint mGetClk(const TraceDB& tdb);
+    static const QJsonObject mGetMemspec(const TraceDB& tdb);
+
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.cpp

@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "configurationfactory.h"
+
+std::shared_ptr<ConfigurationBase> ConfigurationFactory::make(const TraceDB& tdb) {
+    const QString deviceName = ConfigurationBase::getDeviceName(tdb);
+    
+    if (deviceName == "DDR3") {
+        return std::make_shared<DDR3Configuration>(tdb);
+
+    } else if (deviceName == "DDR4") {
+        return std::make_shared<DDR4Configuration>(tdb);
+
+    } else if (deviceName == "HBM2") {
+        return std::make_shared<HBM2Configuration>(tdb);
+
+    } else if (deviceName == "LPDDR4") {
+        return std::make_shared<LPDDR4Configuration>(tdb);
+
+    } else if (deviceName == "DDR5") {
+        return std::make_shared<DDR5Configuration>(tdb);
+
+    } else if (deviceName == "LPDDR5") {
+        return std::make_shared<LPDDR5Configuration>(tdb);
+
+    } else {
+        // TODO maybe throw?
+        throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + '\'');
+
+    }
+
+}
+
+const std::vector<QString> ConfigurationFactory::possiblePhases(const TraceDB& tdb) {
+    const QString deviceName = ConfigurationBase::getDeviceName(tdb);
+    
+    if (deviceName == "DDR3") {
+        // return DDR3TimeDependencies::getPossiblePhases();
+        return TimeDependenciesInfoDDR3::getPossiblePhases();
+
+    } else if (deviceName == "DDR4") {
+        return TimeDependenciesInfoDDR4::getPossiblePhases();
+
+    } else if (deviceName == "HBM2") {
+        return TimeDependenciesInfoHBM2::getPossiblePhases();
+
+    } else if (deviceName == "LPDDR4") {
+        return TimeDependenciesInfoLPDDR4::getPossiblePhases();
+
+    } else if (deviceName == "DDR5") {
+        return TimeDependenciesInfoDDR5::getPossiblePhases();
+
+    } else if (deviceName == "LPDDR5") {
+        return TimeDependenciesInfoLPDDR5::getPossiblePhases();
+
+    } else {
+        // TODO maybe throw?
+        // throw std::invalid_argument("Could not find the device type '" + deviceName.toStdString() + '\'');
+        return {""};
+    }
+
+}
+
+bool ConfigurationFactory::deviceSupported(const TraceDB& tdb) {
+    uint clk; // Not used
+    const QString deviceName = ConfigurationBase::getDeviceName(tdb);
+
+    if (deviceName == "DDR3") {
+        return true;
+
+    } else if (deviceName == "DDR4") {
+        return true;
+
+    } else if (deviceName == "HBM2") {
+        return true;
+
+    } else if (deviceName == "LPDDR4") {
+        return true;
+
+    } else if (deviceName == "DDR5") {
+        return true;
+
+    } else if (deviceName == "LPDDR5") {
+        return true;
+
+    } else {
+        return false;
+    }
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/configurationfactory.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015, Technische Universität Kaiserslautern
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,42 +30,33 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors:
- *    Janik Schlemminger
- *    Robert Gernhardt
- *    Matthias Jung
+ *    Iron Prando da Silva
  */
 
-#ifndef TRACETESTTREEWIDGET_H
-#define TRACETESTTREEWIDGET_H
-#include <QTreeWidget>
-#include <businessObjects/tracetestresults.h>
+#pragma once
 
-class TraceTestTreeWidget: public QTreeWidget
-{
-    Q_OBJECT
+#include <memory>
+
+#include "configurationBase.h"
+
+#include "specialized/DDR3Configuration.h"
+#include "specialized/DDR4Configuration.h"
+#include "specialized/HBM2Configuration.h"
+#include "specialized/LPDDR4Configuration.h"
+#include "specialized/DDR5Configuration.h"
+#include "specialized/LPDDR5Configuration.h"
+
+#include "data/tracedb.h"
+
+class ConfigurationFactory {
 public:
-    TraceTestTreeWidget(QWidget *parent = 0);
-    void addTraceTestResult(const TraceTestResults &traceTestResult);
+    static std::shared_ptr<ConfigurationBase> make(const TraceDB& tdb);
 
-Q_SIGNALS:
-    void setMessage(QString message);
+    static const std::vector<QString> possiblePhases(const TraceDB& tdb);
+
+    static bool deviceSupported(const TraceDB& tdb);
 
 private:
-    class TestResultTreeItem : public QTreeWidgetItem
-    {
-    public:
-        TestResultTreeItem(QTreeWidgetItem *parent, const TestResult &testResult);
-        static constexpr int testResultTreeItemType = 1002;
-        QString getMessage()
-        {
-            return message;
-        }
-    private:
-        QString message;
-    };
-
-private Q_SLOTS:
-    void itemSelectionChanged();
+    ConfigurationFactory() = delete;
+    ~ConfigurationFactory() = delete;
 };
-
-#endif // TRACETESTTREEWIDGET_H

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.cpp

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "DDR3Configuration.h"
+
+DDR3Configuration::DDR3Configuration(const TraceDB& tdb) {
+    // mDeviceDeps = std::make_shared<DDR3TimeDependencies>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
+    mDeviceDeps = std::make_shared<TimeDependenciesInfoDDR3>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
+
+}
+
+std::shared_ptr<DBPhaseEntryBase> DDR3Configuration::makePhaseEntry(const QSqlQuery& query) const {
+    return std::make_shared<DDR3DBPhaseEntry>(query);
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR3Configuration.h

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/configurations/configurationBase.h"
+// #include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.h"
+#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.h"
+#include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h"
+
+class DDR3Configuration : public ConfigurationBase {
+ public:
+    DDR3Configuration(const TraceDB& tdb);
+
+    std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const override;
+
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.cpp

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "DDR4Configuration.h"
+
+DDR4Configuration::DDR4Configuration(const TraceDB& tdb) {
+    mDeviceDeps = std::make_shared<TimeDependenciesInfoDDR4>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
+
+}
+
+std::shared_ptr<DBPhaseEntryBase> DDR4Configuration::makePhaseEntry(const QSqlQuery& query) const {
+    return std::make_shared<DDR4DBPhaseEntry>(query);
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR4Configuration.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/configurations/configurationBase.h"
+#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.h"
+#include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h"
+
+class DDR4Configuration : public ConfigurationBase {
+ public:
+    DDR4Configuration(const TraceDB& tdb);
+
+    std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const override;
+
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.cpp

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "DDR5Configuration.h"
+#include <memory>
+
+DDR5Configuration::DDR5Configuration(const TraceDB& tdb) {
+    mDeviceDeps = std::make_shared<TimeDependenciesInfoDDR5>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
+
+}
+
+std::shared_ptr<DBPhaseEntryBase> DDR5Configuration::makePhaseEntry(const QSqlQuery& query) const {
+    auto phase = std::make_shared<DDR5DBPhaseEntry>(query);
+    
+    auto device = std::dynamic_pointer_cast<TimeDependenciesInfoDDR5>(mDeviceDeps);
+    device->rankIDToRankIDs(phase->tRank, phase->tLogicalRank, phase->tPhysicalRank, phase->tDIMMRank);
+    device->bankIDToBankInGroup(phase->tLogicalRank, phase->tBank, phase->tBankInGroup);
+
+    return phase;
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/DDR5Configuration.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/configurations/configurationBase.h"
+#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h"
+#include "businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h"
+
+class DDR5Configuration : public ConfigurationBase {
+ public:
+    DDR5Configuration(const TraceDB& tdb);
+
+    std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const override;
+
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.cpp

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "HBM2Configuration.h"
+
+HBM2Configuration::HBM2Configuration(const TraceDB& tdb) {
+    mDeviceDeps = std::make_shared<TimeDependenciesInfoHBM2>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
+
+}
+
+std::shared_ptr<DBPhaseEntryBase> HBM2Configuration::makePhaseEntry(const QSqlQuery& query) const {
+    return std::make_shared<HBM2DBPhaseEntry>(query);
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/HBM2Configuration.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/configurations/configurationBase.h"
+#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.h"
+#include "businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h"
+
+class HBM2Configuration : public ConfigurationBase {
+ public:
+    HBM2Configuration(const TraceDB& tdb);
+
+    std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const override;
+
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.cpp

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "LPDDR4Configuration.h"
+
+LPDDR4Configuration::LPDDR4Configuration(const TraceDB& tdb) {
+    // mDeviceDeps = std::make_shared<LPDDR4TimeDependencies>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
+    mDeviceDeps = std::make_shared<TimeDependenciesInfoLPDDR4>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
+
+}
+
+std::shared_ptr<DBPhaseEntryBase> LPDDR4Configuration::makePhaseEntry(const QSqlQuery& query) const {
+    return std::make_shared<LPDDR4DBPhaseEntry>(query);
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR4Configuration.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/configurations/configurationBase.h"
+#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.h"
+#include "businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h"
+
+class LPDDR4Configuration : public ConfigurationBase {
+ public:
+    LPDDR4Configuration(const TraceDB& tdb);
+
+    std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const override;
+
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.cpp

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "LPDDR5Configuration.h"
+#include <memory>
+
+LPDDR5Configuration::LPDDR5Configuration(const TraceDB& tdb) {
+    mDeviceDeps = std::make_shared<TimeDependenciesInfoLPDDR5>(std::forward<const QJsonObject>(mGetMemspec(tdb)), mGetClk(tdb));
+
+}
+
+std::shared_ptr<DBPhaseEntryBase> LPDDR5Configuration::makePhaseEntry(const QSqlQuery& query) const {
+    auto phase = std::make_shared<LPDDR5DBPhaseEntry>(query);
+    
+    auto device = std::dynamic_pointer_cast<TimeDependenciesInfoLPDDR5>(mDeviceDeps);
+    phase->bankOffsetREFP2B = device->getPer2BankOffset();
+
+    return phase;
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/configurations/specialized/LPDDR5Configuration.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/configurations/configurationBase.h"
+#include "businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h"
+#include "businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h"
+
+class LPDDR5Configuration : public ConfigurationBase {
+ public:
+    LPDDR5Configuration(const TraceDB& tdb);
+
+    std::shared_ptr<DBPhaseEntryBase> makePhaseEntry(const QSqlQuery&) const override;
+
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include <QSqlQuery>
+
+#include "businessObjects/phases/phasedependency.h"
+#include "businessObjects/dramTimeDependencies/common/common.h"
+
+class DBPhaseEntryBase {
+ public:
+    DBPhaseEntryBase() = default;
+    virtual ~DBPhaseEntryBase() = default;
+ 
+    virtual bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const { return false; }
+
+    size_t id;
+    StringMapper phaseName;
+    size_t phaseBegin;
+    size_t phaseEnd;
+    size_t transact;
+    size_t tBank;
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.cpp

@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "DDR3dbphaseentry.h"
+
+DDR3DBPhaseEntry::DDR3DBPhaseEntry(const QSqlQuery& query) {
+    id = query.value(0).toLongLong();
+    phaseName = StringMapper(query.value(1).toString());
+    phaseBegin = query.value(2).toLongLong();
+    phaseEnd = query.value(3).toLongLong();
+    transact = query.value(4).toLongLong();
+    tBank = query.value(5).toLongLong();
+    // tBankgroup = query.value(6).toLongLong();
+    tRank = query.value(7).toLongLong();
+}
+
+bool DDR3DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const {
+    auto other = std::dynamic_pointer_cast<DDR3DBPhaseEntry>(otherPhase);
+    if (!other) return false;
+
+    bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS;
+
+    bool const skipOnIntraBankAndDifferentBanks = {
+        dep.depType == DependencyType::IntraBank 
+        && tBank != other->tBank
+    };
+    bool const skipOnIntraRankAndDifferentRanks = {
+        dep.depType == DependencyType::IntraRank 
+        && tRank != other->tRank
+    };
+    bool const skipOnInterRankAndSameRank = {
+        dep.depType == DependencyType::InterRank
+        && tRank == other->tRank
+        && !isCmdPool
+    };
+    
+    return !(skipOnIntraBankAndDifferentBanks || skipOnIntraRankAndDifferentRanks || skipOnInterRankAndSameRank);
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR3dbphaseentry.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h"
+
+class DDR3DBPhaseEntry : public DBPhaseEntryBase {
+ public:
+    DDR3DBPhaseEntry(const QSqlQuery&);
+
+    // size_t tBankgroup;
+    size_t tRank;
+
+    bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const override;
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.cpp

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "DDR4dbphaseentry.h"
+
+DDR4DBPhaseEntry::DDR4DBPhaseEntry(const QSqlQuery& query) {
+    id = query.value(0).toLongLong();
+    phaseName = StringMapper(query.value(1).toString());
+    phaseBegin = query.value(2).toLongLong();
+    phaseEnd = query.value(3).toLongLong();
+    transact = query.value(4).toLongLong();
+    tBank = query.value(5).toLongLong();
+    tBankgroup = query.value(6).toLongLong();
+    tRank = query.value(7).toLongLong();
+}
+
+bool DDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const {
+    auto other = std::dynamic_pointer_cast<DDR4DBPhaseEntry>(otherPhase);
+    if (!other) return false;
+
+    bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS;
+
+    bool const skipOnIntraBankAndDifferentBanks = {
+        dep.depType == DependencyType::IntraBank 
+        && tBank != other->tBank
+    };
+    bool const skipOnIntraBankgroupAndDifferentBankgroup = {
+        dep.depType == DependencyType::IntraBankGroup
+        && tBankgroup != other->tBankgroup
+    };
+    bool const skipOnIntraRankAndDifferentRanks = {
+        dep.depType == DependencyType::IntraRank 
+        && tRank != other->tRank
+    };
+    bool const skipOnInterRankAndSameRank = {
+        dep.depType == DependencyType::InterRank
+        && tRank == other->tRank
+        && !isCmdPool
+    };
+    
+    return !(
+        skipOnIntraBankAndDifferentBanks
+        || skipOnIntraBankgroupAndDifferentBankgroup
+        || skipOnIntraRankAndDifferentRanks 
+        || skipOnInterRankAndSameRank
+    );
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR4dbphaseentry.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h"
+
+class DDR4DBPhaseEntry : public DBPhaseEntryBase {
+ public:
+    DDR4DBPhaseEntry(const QSqlQuery&);
+
+    size_t tBankgroup;
+    size_t tRank;
+
+    bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const override;
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.cpp

@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "DDR5dbphaseentry.h"
+
+DDR5DBPhaseEntry::DDR5DBPhaseEntry(const QSqlQuery& query) {
+    id = query.value(0).toLongLong();
+    phaseName = StringMapper(query.value(1).toString());
+    phaseBegin = query.value(2).toLongLong();
+    phaseEnd = query.value(3).toLongLong();
+    transact = query.value(4).toLongLong();
+    tBank = query.value(5).toLongLong();
+    tBankgroup = query.value(6).toLongLong();
+    tRank = query.value(7).toLongLong();
+}
+
+bool DDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const {
+    auto other = std::dynamic_pointer_cast<DDR5DBPhaseEntry>(otherPhase);
+    if (!other) return false;
+
+    bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS;
+
+    bool const skipOnIntraBankAndDifferentBanks = {
+        dep.depType == DependencyType::IntraBank 
+        && tBank != other->tBank
+    };
+    bool const skipOnIntraBankgroupAndDifferentBankgroup = {
+        dep.depType == DependencyType::IntraBankGroup
+        && tBankgroup != other->tBankgroup
+    };
+    bool const skipOnIntraBankInGroupAndDifferentBankInGroup = {
+        dep.depType == DependencyType::IntraBankInGroup
+        && tBankInGroup != other->tBankInGroup
+    };
+    bool const skipOnIntraLogRankAndDifferentRanks = {
+        dep.depType == DependencyType::IntraLogicalRank 
+        && tLogicalRank != other->tLogicalRank
+    };
+    bool const skipOnIntraPhysRankAndDifferentRanks = {
+        dep.depType == DependencyType::IntraPhysicalRank 
+        && tPhysicalRank != other->tPhysicalRank
+    };
+    bool const skipOnIntraDIMMRankAndDifferentRanks = {
+        dep.depType == DependencyType::IntraDIMMRank 
+        && tDIMMRank != other->tDIMMRank
+    };
+    bool const skipOnInterDIMMRankAndSameRank = {
+        dep.depType == DependencyType::InterDIMMRank
+        && tDIMMRank == other->tDIMMRank
+        && !isCmdPool
+    };
+    
+    return !(
+        skipOnIntraBankAndDifferentBanks
+        || skipOnIntraBankgroupAndDifferentBankgroup
+        || skipOnIntraBankInGroupAndDifferentBankInGroup
+        || skipOnIntraLogRankAndDifferentRanks
+        || skipOnIntraPhysRankAndDifferentRanks
+        || skipOnIntraDIMMRankAndDifferentRanks
+        || skipOnInterDIMMRankAndSameRank
+    );
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/DDR5dbphaseentry.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h"
+
+class DDR5DBPhaseEntry : public DBPhaseEntryBase {
+ public:
+    DDR5DBPhaseEntry(const QSqlQuery&);
+
+    size_t tBankgroup;
+    size_t tBankInGroup;
+    size_t tRank;
+
+    size_t tLogicalRank;
+    size_t tPhysicalRank;
+    size_t tDIMMRank;
+
+    bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const override;
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.cpp

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "HBM2dbphaseentry.h"
+
+HBM2DBPhaseEntry::HBM2DBPhaseEntry(const QSqlQuery& query) {
+    id = query.value(0).toLongLong();
+    phaseName = StringMapper(query.value(1).toString());
+    phaseBegin = query.value(2).toLongLong();
+    phaseEnd = query.value(3).toLongLong();
+    transact = query.value(4).toLongLong();
+    tBank = query.value(5).toLongLong();
+    tBankgroup = query.value(6).toLongLong();
+    tRank = query.value(7).toLongLong();
+}
+
+bool HBM2DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const {
+    auto other = std::dynamic_pointer_cast<HBM2DBPhaseEntry>(otherPhase);
+    if (!other) return false;
+
+    bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS;
+
+    bool const skipOnIntraBankAndDifferentBanks = {
+        dep.depType == DependencyType::IntraBank 
+        && tBank != other->tBank
+    };
+    bool const skipOnIntraBankgroupAndDifferentBankgroup = {
+        dep.depType == DependencyType::IntraBankGroup
+        && tBankgroup != other->tBankgroup
+    };
+    bool const skipOnIntraRankAndDifferentRanks = {
+        dep.depType == DependencyType::IntraRank 
+        && tRank != other->tRank
+    };
+    bool const skipOnInterRankAndSameRank = {
+        dep.depType == DependencyType::InterRank
+        && tRank == other->tRank
+        && !isCmdPool
+    };
+    
+    return !(
+        skipOnIntraBankAndDifferentBanks
+        || skipOnIntraBankgroupAndDifferentBankgroup
+        || skipOnIntraRankAndDifferentRanks 
+        || skipOnInterRankAndSameRank
+    );
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/HBM2dbphaseentry.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h"
+
+class HBM2DBPhaseEntry : public DBPhaseEntryBase {
+ public:
+    HBM2DBPhaseEntry(const QSqlQuery&);
+
+    size_t tBankgroup;
+    size_t tRank;
+
+    bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const override;
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.cpp

@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "LPDDR4dbphaseentry.h"
+
+LPDDR4DBPhaseEntry::LPDDR4DBPhaseEntry(const QSqlQuery& query) {
+    id = query.value(0).toLongLong();
+    phaseName = StringMapper(query.value(1).toString());
+    phaseBegin = query.value(2).toLongLong();
+    phaseEnd = query.value(3).toLongLong();
+    transact = query.value(4).toLongLong();
+    tBank = query.value(5).toLongLong();
+    // tBankgroup = query.value(6).toLongLong();
+    tRank = query.value(7).toLongLong();
+}
+
+bool LPDDR4DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const {
+    auto other = std::dynamic_pointer_cast<LPDDR4DBPhaseEntry>(otherPhase);
+    if (!other) return false;
+
+    bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS;
+
+    bool const skipOnIntraBankAndDifferentBanks = {
+        dep.depType == DependencyType::IntraBank 
+        && tBank != other->tBank
+    };
+    bool const skipOnIntraRankAndDifferentRanks = {
+        dep.depType == DependencyType::IntraRank 
+        && tRank != other->tRank
+    };
+    bool const skipOnInterRankAndSameRank = {
+        dep.depType == DependencyType::InterRank
+        && tRank == other->tRank
+        && !isCmdPool
+    };
+    
+    return !(skipOnIntraBankAndDifferentBanks || skipOnIntraRankAndDifferentRanks || skipOnInterRankAndSameRank);
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR4dbphaseentry.h

@@ -0,0 +1,49 @@
+
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h"
+
+class LPDDR4DBPhaseEntry : public DBPhaseEntryBase {
+ public:
+    LPDDR4DBPhaseEntry(const QSqlQuery&);
+
+    // size_t tBankgroup;
+    size_t tRank;
+
+    bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const override;
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.cpp

@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "LPDDR5dbphaseentry.h"
+
+LPDDR5DBPhaseEntry::LPDDR5DBPhaseEntry(const QSqlQuery& query) {
+    id = query.value(0).toLongLong();
+    phaseName = StringMapper(query.value(1).toString());
+    phaseBegin = query.value(2).toLongLong();
+    phaseEnd = query.value(3).toLongLong();
+    transact = query.value(4).toLongLong();
+    tBank = query.value(5).toLongLong();
+    tBankgroup = query.value(6).toLongLong();
+    tRank = query.value(7).toLongLong();
+}
+
+bool LPDDR5DBPhaseEntry::potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const {
+    auto other = std::dynamic_pointer_cast<LPDDR5DBPhaseEntry>(otherPhase);
+    if (!other) return false;
+
+    bool isCmdPool = dep.phaseDep == StringMapper::Identifier::CMD_BUS;
+    bool thisIsREFP2B = phaseName == StringMapper::Identifier::REFP2B;
+    bool otherIsREFP2B = dep.phaseDep == StringMapper::Identifier::REFP2B;
+
+    bool const skipOnIntraBankAndNoBankDep = {
+        dep.depType == DependencyType::IntraBank 
+        && 
+        (
+            ( // If phase is not REFP2B or both are REFP2B, intra bank dependency must occur in the same bank
+                (!thisIsREFP2B || (thisIsREFP2B && otherIsREFP2B))
+                && tBank != other->tBank
+            ) 
+            || 
+            ( // If phase is REFP2B, "intra bank" dependency must occur in the same bank or in the offset bank
+                (thisIsREFP2B && !otherIsREFP2B)
+                && 
+                (
+                    tBank != other->tBank
+                    && tBank != (other->tBank - bankOffsetREFP2B)
+                )
+            )
+        )
+    };
+    bool const skipOnIntraBankgroupAndDifferentBankgroup = {
+        dep.depType == DependencyType::IntraBankGroup
+        && tBankgroup != other->tBankgroup
+    };
+    bool const skipOnIntraRankAndDifferentRanks = {
+        dep.depType == DependencyType::IntraRank 
+        && tRank != other->tRank
+    };
+    bool const skipOnInterRankAndSameRank = {
+        dep.depType == DependencyType::InterRank
+        && tRank == other->tRank
+        && !isCmdPool
+    };
+    
+    return !(
+        skipOnIntraBankAndNoBankDep
+        || skipOnIntraBankgroupAndDifferentBankgroup
+        || skipOnIntraRankAndDifferentRanks 
+        || skipOnInterRankAndSameRank
+    );
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/dbEntries/specialized/LPDDR5dbphaseentry.h

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/dbEntries/dbphaseentryBase.h"
+
+class LPDDR5DBPhaseEntry : public DBPhaseEntryBase {
+ public:
+    LPDDR5DBPhaseEntry(const QSqlQuery&);
+
+    size_t tBankgroup;
+    size_t tRank;
+    size_t bankOffsetREFP2B;
+
+    bool potentialDependency(const TimeDependency& dep, const std::shared_ptr<DBPhaseEntryBase> otherPhase) const override;
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.cpp

@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "dramtimedependenciesbase.h"
+
+#include <QJsonDocument>
+
+DRAMTimeDependenciesBase::DRAMTimeDependenciesBase(const QJsonObject& memspec, const uint inTCK) {
+    mMemspecJson = memspec;
+    tCK = inTCK;
+
+}
+
+DependencyMap
+DRAMTimeDependenciesBase::getDependencies(std::vector<QString>& dependencyFilter) const {
+    DependencyMap dependenciesMap;
+
+    std::vector<StringMapper> dependencyFilterStrMapper(dependencyFilter.begin(), dependencyFilter.end());
+    std::sort(
+        dependencyFilterStrMapper.begin(), 
+        dependencyFilterStrMapper.end()
+    );
+    
+    dependenciesMap = mSpecializedGetDependencies();
+    
+    mFilterDependencyMap(dependenciesMap, dependencyFilterStrMapper);
+
+    auto it = dependenciesMap.begin();
+    while (it != dependenciesMap.end()) {
+        mFilterDependencyList(it->second.dependencies, dependencyFilterStrMapper);
+        it->second.maxTime = mFindVectorMaximum(it->second.dependencies);
+
+        ++it;
+    }
+
+    return dependenciesMap;
+}
+
+PoolControllerMap DRAMTimeDependenciesBase::getPools() const {
+    return PoolControllerMap(mPools);
+}
+
+void DRAMTimeDependenciesBase::mFilterDependencyList(std::vector<TimeDependency>& dependencyList, const std::vector<StringMapper>& dependencyFilter) const {
+    std::vector<TimeDependency> newDepList(dependencyList.size());
+    
+    // TODO - probably there is a smarter way to filter these values,
+    // although the lists are not to be greater than 20-50 elements
+
+    std::copy_if(
+        dependencyList.begin(),
+        dependencyList.end(),
+        newDepList.begin(),
+        [ dependencyFilter ](const TimeDependency& dep) { 
+            auto it = std::lower_bound(
+                dependencyFilter.begin(),
+                dependencyFilter.end(),
+                dep.phaseDep,
+                [](const StringMapper& cmd, const StringMapper& depName){
+                    return depName.isPool() || cmd < depName;
+                }
+            );
+
+            if (dep.phaseDep.isPool() || it != dependencyFilter.end() && *it == dep.phaseDep) 
+                return true;
+
+            return false;
+        }
+    );
+
+    newDepList.shrink_to_fit();
+
+    dependencyList = newDepList;
+
+    std::sort(
+        dependencyList.begin(), 
+        dependencyList.end(), 
+        [](const TimeDependency& v1, const TimeDependency& v2) {
+            return v1.timeValue < v2.timeValue;
+        }
+    );
+
+}
+
+void DRAMTimeDependenciesBase::mFilterDependencyMap(DependencyMap& dependencyMap, const std::vector<StringMapper>& dependencyFilter) const {
+    if (!dependencyMap.empty()) {
+
+        auto itFilter = dependencyFilter.begin();
+        auto itFilterLast = std::lower_bound(
+            dependencyFilter.begin(), 
+            dependencyFilter.end(), 
+            dependencyMap.rbegin()->first
+        );
+
+        auto itDependencyMap = dependencyMap.begin();
+
+        while (true) {
+
+            auto pair = std::mismatch(
+                itFilter,
+                itFilterLast,
+                itDependencyMap,
+                [](const StringMapper& cmd, const std::pair<StringMapper, PhaseTimeDependencies>& vpair) {
+                    return cmd == vpair.first;
+                }
+            );
+
+            if (pair.first == dependencyFilter.end() || pair.second == dependencyMap.end()) {
+                dependencyMap.erase(pair.second, dependencyMap.end());
+                break;
+
+            } else if (*(pair.first) < pair.second->first) {
+                ++(pair.first);
+
+            } else if (*(pair.first) == pair.second->first) {
+                ++(pair.second);
+
+            } else {
+                pair.second = dependencyMap.erase(pair.second);
+
+            }
+
+            itFilter = pair.first;
+            itDependencyMap = pair.second;
+
+        }
+    }
+
+}
+
+uint DRAMTimeDependenciesBase::mFindVectorMaximum(const std::vector<TimeDependency>& dependencyList) const {
+    auto maxElement = std::max_element(
+        dependencyList.begin(),
+        dependencyList.end(),
+        [](const TimeDependency& dep1, const TimeDependency& dep2) {
+            return dep1.timeValue < dep2.timeValue;
+        }
+    );
+
+    if (maxElement == dependencyList.end()) return 0;
+
+    return maxElement->timeValue;
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.h

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "data/tracedb.h"
+#include "businessObjects/dramTimeDependencies/common/common.h"
+#include "poolcontrollermap.h"
+
+class DRAMTimeDependenciesBase {
+public:
+    DRAMTimeDependenciesBase(const QJsonObject& memspec, const uint tCK);
+    virtual ~DRAMTimeDependenciesBase() = default;
+
+    DependencyMap getDependencies(std::vector<QString>& dependencyFilter) const;
+
+    const uint getClk() const { return tCK; }
+
+    PoolControllerMap getPools() const;
+
+protected:
+    void mFilterDependencyList(std::vector<TimeDependency>& dependencyList, const std::vector<StringMapper>& dependencyFilter) const;
+    void mFilterDependencyMap(DependencyMap& dependencyMap, const std::vector<StringMapper>& dependencyFilter) const;
+    uint mFindVectorMaximum(const std::vector<TimeDependency>& dependencyList) const;
+    
+protected:
+    QJsonObject mMemspecJson;
+
+// To be implemented by the specializing class
+protected:
+    virtual void mInitializeValues() {} ;
+    virtual DependencyMap mSpecializedGetDependencies() const { DependencyMap map; return map; } ;
+    
+    uint tCK = 0;
+
+    std::map<StringMapper, PoolController> mPools;
+
+};
+

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.cpp

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "poolcontroller.h"
+#include <algorithm>
+
+PoolController::PoolController(const uint poolSize, const std::vector<PoolEntry>& dependencies)
+: mDependencies(mAuxSortInput(dependencies)) 
+{
+    mPoolSize = poolSize;
+
+}
+
+void PoolController::clear() {
+    mPool.clear();
+    mCount = 0;
+
+}
+
+void PoolController::push(DBDependencyEntry dep) {
+    mPool.push_back(dep);
+    mCount++;
+
+}
+
+void PoolController::increment() {
+    mCount++;
+}
+
+void PoolController::merge(std::vector<DBDependencyEntry>& depEntries) {
+    if(mCount >= mPoolSize) {
+        depEntries.insert( depEntries.end(), mPool.begin(), mPool.end() );
+    }
+}
+
+uint PoolController::getBusyTime(const StringMapper& phaseName) {
+    PoolEntry v{phaseName, 0};
+
+    auto entryIt = std::lower_bound(
+        mDependencies.begin(), 
+        mDependencies.end(), 
+        v,
+        [](const PoolEntry& e1, const PoolEntry& e2) {
+            return e1.first < e2.first;
+        }
+    );
+
+    if (entryIt->first == phaseName) {
+        return entryIt->second;
+    } else {
+        return 0;
+    }
+}
+
+std::vector<PoolEntry> PoolController::mAuxSortInput(std::vector<PoolEntry> vec) {
+    std::sort(
+        vec.begin(), 
+        vec.end(),
+        [](const PoolEntry& e1, const PoolEntry& e2) {
+            return e1.first < e2.first;
+        }
+    );
+
+    return vec;
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontroller.h

@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/common/common.h"
+
+typedef std::pair<StringMapper, uint> PoolEntry;
+
+class PoolController {
+public:
+    PoolController(const uint poolSize, const std::vector<PoolEntry>& dependencies);
+    ~PoolController() = default;
+
+    void clear();
+    void push(DBDependencyEntry);
+    void increment();
+    void merge(std::vector<DBDependencyEntry>& depEntries);
+    size_t count() { return mCount; }
+    
+    uint getBusyTime(const StringMapper& phaseName);
+
+protected:
+    const std::vector<PoolEntry> mDependencies;
+    std::vector<DBDependencyEntry> mPool;
+    uint mCount = 0;
+    uint mPoolSize = 0;
+
+protected:
+    static std::vector<PoolEntry> mAuxSortInput(std::vector<PoolEntry> vec);
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.cpp

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "poolcontrollermap.h"
+
+PoolControllerMap::PoolControllerMap(const std::map<StringMapper, PoolController>& pools) {
+    mPools = pools;
+}
+
+void PoolControllerMap::clear() {
+    for (auto& p : mPools) {
+        p.second.clear();
+    }
+
+}
+
+void PoolControllerMap::push(const StringMapper& poolName, DBDependencyEntry dep) {
+    auto pool = mPools.find(poolName);
+    if (pool != mPools.end()) {
+        pool->second.push(dep);
+
+    } else {
+        // TODO throw?
+    }
+}
+
+void PoolControllerMap::increment(const StringMapper& poolName) {
+    auto pool = mPools.find(poolName);
+    if (pool != mPools.end()) {
+        pool->second.increment();
+
+    } else {
+        // TODO throw?
+    }
+}
+
+void PoolControllerMap::merge(std::vector<DBDependencyEntry>& depEntries) {
+    for (auto& p : mPools) {
+        p.second.merge(depEntries);
+    }
+}
+
+uint PoolControllerMap::getBusyTime(const StringMapper& poolName, const StringMapper& phaseName) {
+    auto pool = mPools.find(poolName);
+    if (pool != mPools.end()) {
+        return pool->second.getBusyTime(phaseName);
+
+    } else {
+        // TODO throw?
+        return 0;
+    
+    }
+}
+
+size_t PoolControllerMap::count(const StringMapper& poolName) {
+    auto pool = mPools.find(poolName);
+    if (pool != mPools.end()) {
+        return pool->second.count();
+
+    } else {
+        // TODO throw?
+        return 0;
+    
+    }
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/poolcontrollermap.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "poolcontroller.h"
+
+class PoolControllerMap {
+public:
+    PoolControllerMap(const std::map<StringMapper, PoolController>& pools);
+    ~PoolControllerMap() = default;
+
+    void clear();
+    void push(const StringMapper& poolName, DBDependencyEntry);
+    void increment(const StringMapper& poolName);
+    void merge(std::vector<DBDependencyEntry>& depEntries);
+    size_t count(const StringMapper& poolName);
+
+    uint getBusyTime(const StringMapper& poolName, const StringMapper& phaseName);
+
+
+protected:
+    std::map<StringMapper, PoolController> mPools;
+
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.cpp

@@ -0,0 +1,372 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "DDR3TimeDependencies.h"
+
+using namespace std;
+
+DDR3TimeDependencies::DDR3TimeDependencies(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) {
+    mInitializeValues();
+}
+
+void DDR3TimeDependencies::mInitializeValues() {
+    burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
+    dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
+
+    tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt();
+    tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
+    tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt();
+    tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt();
+    tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt();
+    tCCD = tCK * mMemspecJson["memtimingspec"].toObject()["CCD"].toInt();
+    tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
+    tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt();
+    tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt();
+    tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt();
+    tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt();
+    tWTR = tCK * mMemspecJson["memtimingspec"].toObject()["WTR"].toInt();
+    tCKESR = tCK * mMemspecJson["memtimingspec"].toObject()["CKESR"].toInt();
+    tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt();
+    tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt();
+    tXPDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XPDLL"].toInt();
+    tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt();
+    tXSDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XSDLL"].toInt();
+    tAL = tCK * mMemspecJson["memtimingspec"].toObject()["AL"].toInt();
+    tRFC = tCK * mMemspecJson["memtimingspec"].toObject()["RFC"].toInt();
+    tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI"].toInt();
+    tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt();
+    tACTPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["ACTPDEN"].toInt();
+    tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt();
+    tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt();
+    tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt();
+    
+    tPD = tCKE;
+    tBURST = (uint) ((burstLength / (float) dataRate) * tCK);
+    tRDWR = tRL + tBURST + 2 * tCK - tWL;
+    tRDWR_R = tRL + tBURST + tRTRS - tWL;
+    tWRRD = tWL + tBURST + tWTR;
+    tWRRD_R = tWL + tBURST + tRTRS - tRL;
+    tWRPRE = tWL + tBURST + tWR;
+    tRDPDEN = tRL + tBURST + tCK;
+    tWRPDEN = tWL + tBURST + tWR;
+    tWRAPDEN = tWL + tBURST + tWR + tCK;
+
+    mPools.insert({
+        "CMD_BUS", {
+        1, {
+            {"ACT", tCK},
+            {"RD", tCK},
+            {"WR", tCK},
+            {"PREPB", tCK},
+            {"RDA", tCK},
+            {"WRA", tCK},
+            {"REFAB", tCK},
+            {"PREAB", tCK},
+            {"PDEP", tCK},
+            {"PDXP", tCK},
+            {"SREFEN", tCK},
+            {"SREFEX", tCK},
+            {"PDEA", tCK},
+            {"PDXA", tCK},
+            }
+        }
+    });
+    mPools.insert({"NAW", {4, {{"ACT", tFAW}}}});
+    
+}
+
+const vector<QString> DDR3TimeDependencies::getPossiblePhases() {
+    return {"ACT",
+            "RD",
+            "RDA",
+            "WR",
+            "WRA",
+            "PREPB",
+            "PREAB",
+            "REFAB",
+            "PDEA",
+            "PDXA",
+            "PDEP",
+            "PDXP",
+            "SREFEN",
+            "SREFEX"
+    };
+}
+
+DependencyMap DDR3TimeDependencies::mSpecializedGetDependencies() const {
+    DependencyMap dmap;
+
+    dmap.emplace(
+        piecewise_construct, 
+        forward_as_tuple("ACT"), 
+        forward_as_tuple(
+            initializer_list<TimeDependency>{
+                {tRC, "ACT", DependencyType::IntraBank, "tRC"},
+                {tAL + tRTP + tRP, "RDA", DependencyType::IntraBank, "tAL + tRTP + tRP"},
+                {tWRPRE + tRP, "WRA", DependencyType::IntraBank, "tWRPRE + tRP"},
+                {tRP, "PREPB", DependencyType::IntraBank, "tRP"},
+                {tRRD, "ACT", DependencyType::IntraRank, "tRRD"},
+                {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+                {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+                {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+                {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+                {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+                {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"},
+                {tFAW, "NAW", DependencyType::IntraRank, "tFAW"},
+            }
+        )
+    );
+
+    dmap.emplace(
+        piecewise_construct, 
+        forward_as_tuple("RD"), 
+        forward_as_tuple(
+            initializer_list<TimeDependency>{
+                {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+                {tCCD, "RD", DependencyType::IntraRank, "tCCD"},
+                {tCCD, "RDA", DependencyType::IntraRank, "tCCD"},
+                {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"},
+                {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"},
+                {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+                {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+                {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
+                {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
+                {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
+                {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
+                {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"},
+            }
+        )
+    );
+
+    dmap.emplace(
+        piecewise_construct, 
+        forward_as_tuple("RDA"), 
+        forward_as_tuple(
+            initializer_list<TimeDependency>{
+                {tRCD - tAL, "ACT", DependencyType::IntraBank,  "tRCD - tAL"},
+                {tWRPRE - tRTP, "WR", DependencyType::IntraBank,  "tWRPRE - tRTP"},
+                {tCCD, "RD", DependencyType::IntraRank,  "tCCD"},
+                {tCCD, "RDA", DependencyType::IntraRank,  "tCCD"},
+                {tWRRD, "WR", DependencyType::IntraRank,  "tWRRD"},
+                {tWRRD, "WRA", DependencyType::IntraRank,  "tWRRD"},
+                {tXP, "PDXA", DependencyType::IntraRank,  "tXP"},
+                {tXSDLL, "SREFEX", DependencyType::IntraRank,  "tXSDLL"},
+                {tBURST + tRTRS, "RD", DependencyType::InterRank,  "tBURST + tRTRS"},
+                {tBURST + tRTRS, "RDA", DependencyType::InterRank,  "tBURST + tRTRS"},
+                {tWRRD_R, "WR", DependencyType::InterRank,  "tWRRD_R"},
+                {tWRRD_R, "WRA", DependencyType::InterRank,  "tWRRD_R"},
+                {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"},
+            }
+        )
+    );
+
+    dmap.emplace(
+        piecewise_construct, 
+        forward_as_tuple("WR"), 
+        forward_as_tuple(
+            initializer_list<TimeDependency>{
+                {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+                {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
+                {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
+                {tCCD, "WR", DependencyType::IntraRank, "tCCD"},
+                {tCCD, "WRA", DependencyType::IntraRank, "tCCD"},
+                {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+                {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+                {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
+                {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
+                {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
+                {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
+                {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"},
+            }
+        )
+    );
+
+    dmap.emplace(
+        piecewise_construct, 
+        forward_as_tuple("WRA"), 
+        forward_as_tuple(
+            initializer_list<TimeDependency>{
+                {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+                {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
+                {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
+                {tCCD, "WR", DependencyType::IntraRank, "tCCD"},
+                {tCCD, "WRA", DependencyType::IntraRank, "tCCD"},
+                {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+                {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+                {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
+                {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
+                {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
+                {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
+                {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"},
+            }
+        )
+    );
+
+    dmap.emplace(
+        piecewise_construct, 
+        forward_as_tuple("PREPB"), 
+        forward_as_tuple(
+            initializer_list<TimeDependency>{
+                {tRAS, "ACT", DependencyType::IntraBank, "tRAS"},
+                {tAL + tRTP, "RD", DependencyType::IntraBank, "tAL + tRTP"},
+                {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"},
+                {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+                {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"},
+            }
+        )
+    );
+
+    dmap.emplace(
+        piecewise_construct, 
+        forward_as_tuple("PREAB"), 
+        forward_as_tuple(
+            initializer_list<TimeDependency>{
+                {tRAS, "ACT", DependencyType::IntraRank, "tRAS"},
+                {tAL + tRTP, "RD", DependencyType::IntraRank, "tAL + tRTP"},
+                {tAL + tRTP, "RDA", DependencyType::IntraRank, "tAL + tRTP"},
+                {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"},
+                {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"},
+                {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+                {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"},
+            }
+        )
+    );
+
+    dmap.emplace(
+        piecewise_construct, 
+        forward_as_tuple("REFAB"), 
+        forward_as_tuple(
+            initializer_list<TimeDependency>{
+                {tRC, "ACT", DependencyType::IntraRank, "tRC"},
+                {tAL + tRTP + tRP, "RDA", DependencyType::IntraRank, "tAL + tRTP + tRP"},
+                {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"},
+                {tRP, "PREPB", DependencyType::IntraRank, "tRP"},
+                {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+                {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+                {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+                {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+                {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"},
+            }
+        )
+    );
+
+    dmap.emplace(
+        piecewise_construct, 
+        forward_as_tuple("PDEA"), 
+        forward_as_tuple(
+            initializer_list<TimeDependency>{
+                {tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"},
+                {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"},
+                {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"},
+                {tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"},
+                {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
+                {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
+                {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"},
+                {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"},
+            }
+        )
+    );
+
+    dmap.emplace(
+        piecewise_construct, 
+        forward_as_tuple("PDXA"), 
+        forward_as_tuple(
+            initializer_list<TimeDependency>{
+                {tPD, "PDEA", DependencyType::IntraRank, "tPD"},
+                {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"},
+            }
+        )
+    );
+
+    dmap.emplace(
+        piecewise_construct, 
+        forward_as_tuple("PDEP"), 
+        forward_as_tuple(
+            initializer_list<TimeDependency>{
+                {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"},
+                {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"},
+                {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
+                {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
+                {tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"},
+                {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"},
+                {tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"},
+                {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+                {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"},
+            }
+        )
+    );
+
+    dmap.emplace(
+        piecewise_construct, 
+        forward_as_tuple("PDXP"), 
+        forward_as_tuple(
+            initializer_list<TimeDependency>{
+                {tPD, "PDEP", DependencyType::IntraRank, "tPD"},
+                {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"},
+            }
+        )
+    );
+
+    dmap.emplace(
+        piecewise_construct, 
+        forward_as_tuple("SREFEN"), 
+        forward_as_tuple(
+            initializer_list<TimeDependency>{
+                {tRC, "ACT", DependencyType::IntraRank, "tRC"},
+                {max({tRDPDEN, tAL + tRTP + tRP}), "RDA", DependencyType::IntraRank, "max(tRDPDEN, tAL + tRTP + tRP)"},
+                {max({tWRAPDEN, tWRPRE + tRP}), "WRA", DependencyType::IntraRank, "max(tWRAPDEN, tWRPRE + tRP)"},
+                {tRP, "PREPB", DependencyType::IntraRank, "tRP"},
+                {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+                {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+                {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+                {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+                {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"},
+            }
+        )
+    );
+
+    dmap.emplace(
+        piecewise_construct, 
+        forward_as_tuple("SREFEX"), 
+        forward_as_tuple(
+            initializer_list<TimeDependency>{
+                {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"},
+                {tCK, "CMD_BUS", DependencyType::InterRank, "CMD_BUS"},
+            }
+        )
+    );
+
+    return dmap;
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/DDR3TimeDependencies.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "businessObjects/dramTimeDependencies/deviceDependencies/dramtimedependenciesbase.h"
+
+class DDR3TimeDependencies final : public DRAMTimeDependenciesBase {
+public:
+    DDR3TimeDependencies(const QJsonObject& memspec, const uint tCK);
+
+    static const std::vector<QString> getPossiblePhases();
+
+protected:
+    void mInitializeValues() override;
+    DependencyMap mSpecializedGetDependencies() const override;
+    
+protected:
+    uint burstLength;
+    uint dataRate;
+
+    uint tRP;
+    uint tRAS;
+    uint tRC;
+    uint tRTP;
+    uint tRRD;
+    uint tCCD;
+    uint tRCD;
+    uint tFAW;
+    uint tRL;
+    uint tWL;
+    uint tWR;
+    uint tWTR;
+    uint tCKESR;
+    uint tCKE;
+    uint tXP;
+    uint tXPDLL;
+    uint tXS;
+    uint tXSDLL;
+    uint tAL;
+    uint tRFC;
+    uint tREFI;
+    uint tRTRS;
+
+    uint tACTPDEN;
+    uint tPRPDEN;
+    uint tREFPDEN;
+
+    uint tPD;
+    uint tBURST;
+    uint tRDWR;
+    uint tRDWR_R;
+    uint tWRRD;
+    uint tWRRD_R;
+    uint tWRPRE;
+    uint tRDPDEN;
+    uint tWRPDEN;
+    uint tWRAPDEN;
+
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.cpp

@@ -0,0 +1,387 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "TimeDependenciesInfoDDR3.h"
+
+using namespace std;
+
+TimeDependenciesInfoDDR3::TimeDependenciesInfoDDR3(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) {
+  mInitializeValues();
+}
+
+void TimeDependenciesInfoDDR3::mInitializeValues() {
+  burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
+  dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
+
+  tCCD = tCK * mMemspecJson["memtimingspec"].toObject()["CCD"].toInt();
+  tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
+  tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt();
+  tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
+  tCL = tCK * mMemspecJson["memtimingspec"].toObject()["CL"].toInt();
+  tCWL = tCK * mMemspecJson["memtimingspec"].toObject()["CWL"].toInt();
+  tAL = tCK * mMemspecJson["memtimingspec"].toObject()["AL"].toInt();
+  tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt();
+  tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt();
+  tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt();
+  tWTR = tCK * mMemspecJson["memtimingspec"].toObject()["WTR"].toInt();
+  tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt();
+  tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt();
+  tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt();
+  tRFC = tCK * mMemspecJson["memtimingspec"].toObject()["RFC"].toInt();
+  tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt();
+  tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt();
+  tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt();
+  tXSDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XSDLL"].toInt();
+  tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt();
+  tCKESR = tCK * mMemspecJson["memtimingspec"].toObject()["CKESR"].toInt();
+  tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt();
+  tACTPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["ACTPDEN"].toInt();
+  tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt();
+  tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt();
+
+  tPD = tCKE;
+
+  tBURST = (uint) (burstLength / (float) dataRate) * tCK;
+  tRDWR = tRL + tBURST + 2 * tCK - tWL;
+  tRDWR_R = tRL + tBURST + tRTRS - tWL;
+  tWRRD = tWL + tBURST + tWTR - tAL;
+  tWRPRE = tWL + tBURST + tWR;
+  tWRRD_R = tWL + tBURST + tRTRS - tRL;
+  tRDPDEN = tRL + tBURST + tCK;
+  tWRPDEN = tWL + tBURST + tWR;
+  tWRAPDEN = tWL + tBURST + tWR + tCK;
+
+  mPools.insert({
+    "CMD_BUS", {
+      1, {
+        {"ACT", tCK},
+        {"RD", tCK},
+        {"WR", tCK},
+        {"PREPB", tCK},
+        {"RDA", tCK},
+        {"WRA", tCK},
+        {"REFAB", tCK},
+        {"PREAB", tCK},
+        {"PDEP", tCK},
+        {"PDXP", tCK},
+        {"SREFEN", tCK},
+        {"SREFEX", tCK},
+        {"PDEA", tCK},
+        {"PDXA", tCK},
+      }
+    }
+  });
+
+  mPools.insert({
+    "NAW", {
+      4, {
+        {"ACT", tFAW},
+      }
+    }
+  });
+  
+}
+
+const std::vector<QString> TimeDependenciesInfoDDR3::getPossiblePhases() {
+  return {
+    "ACT",
+    "RD",
+    "WR",
+    "PREPB",
+    "RDA",
+    "WRA",
+    "REFAB",
+    "PREAB",
+    "PDEP",
+    "PDXP",
+    "SREFEN",
+    "SREFEX",
+    "PDEA",
+    "PDXA",
+  };
+}
+
+DependencyMap TimeDependenciesInfoDDR3::mSpecializedGetDependencies() const {
+  DependencyMap dmap;
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("ACT"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC, "ACT", DependencyType::IntraBank, "tRC"},
+        {tRRD, "ACT", DependencyType::IntraRank, "tRRD"},
+        {tAL + tRTP + tRP, "RDA", DependencyType::IntraBank, "tAL + tRTP + tRP"},
+        {tWRPRE + tRP, "WRA", DependencyType::IntraBank, "tWRPRE + tRP"},
+        {tRP, "PREPB", DependencyType::IntraBank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+        {tFAW, "NAW", DependencyType::IntraRank, "tFAW"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RD"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tCCD, "RD", DependencyType::IntraBank, "tCCD"},
+        {tCCD, "RD", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD, "RDA", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tWRRD, "WR", DependencyType::IntraBank, "tWRRD"},
+        {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"},
+        {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
+        {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"},
+        {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WR"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"},
+        {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
+        {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
+        {tCCD, "WR", DependencyType::IntraBank, "tCCD"},
+        {tCCD, "WR", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD, "WRA", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREPB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS, "ACT", DependencyType::IntraBank, "tRAS"},
+        {tAL + tRTP, "RD", DependencyType::IntraBank, "tAL + tRTP"},
+        {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RDA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tCCD, "RD", DependencyType::IntraBank, "tCCD"},
+        {tCCD, "RD", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD, "RDA", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {max({tWRRD, tWRPRE - tRTP - tAL}), "WR", DependencyType::IntraBank, "max(tWRRD, tWRPRE - tRTP - tAL)"},
+        {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"},
+        {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
+        {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"},
+        {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WRA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"},
+        {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
+        {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
+        {tCCD, "WR", DependencyType::IntraBank, "tCCD"},
+        {tCCD, "WR", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD, "WRA", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("REFAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC, "ACT", DependencyType::IntraRank, "tRC"},
+        {tAL + tRTP + tRP, "RDA", DependencyType::IntraRank, "tAL + tRTP + tRP"},
+        {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"},
+        {tRP, "PREPB", DependencyType::IntraRank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS, "ACT", DependencyType::IntraRank, "tRAS"},
+        {tAL + tRTP, "RD", DependencyType::IntraRank, "tAL + tRTP"},
+        {tAL + tRTP, "RDA", DependencyType::IntraRank, "tAL + tRTP"},
+        {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"},
+        {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDEP"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"},
+        {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"},
+        {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
+        {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
+        {tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"},
+        {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"},
+        {tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDXP"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tPD, "PDEP", DependencyType::IntraRank, "tPD"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("SREFEN"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC, "ACT", DependencyType::IntraRank, "tRC"},
+        {max({tRDPDEN, tAL + tRTP + tRP}), "RDA", DependencyType::IntraRank, "max(tRDPDEN, tAL + tRTP + tRP)"},
+        {max({tWRAPDEN, tWRPRE + tRP}), "WRA", DependencyType::IntraRank, "max(tWRAPDEN, tWRPRE + tRP)"},
+        {tRP, "PREPB", DependencyType::IntraRank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("SREFEX"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDEA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"},
+        {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"},
+        {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"},
+        {tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"},
+        {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
+        {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
+        {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDXA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tPD, "PDEA", DependencyType::IntraRank, "tPD"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  return dmap;
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR3.h

@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "../dramtimedependenciesbase.h"
+
+class TimeDependenciesInfoDDR3 final : public DRAMTimeDependenciesBase {
+  public:
+    TimeDependenciesInfoDDR3(const QJsonObject& memspec, const uint clk);
+
+    static const std::vector<QString> getPossiblePhases();
+
+  protected:
+    void mInitializeValues() override;
+    DependencyMap mSpecializedGetDependencies() const override;
+
+  protected:
+    uint burstLength;
+    uint dataRate;
+
+    uint tCCD;
+    uint tRCD;
+    uint tRP;
+    uint tRAS;
+    uint tCL;
+    uint tCWL;
+    uint tAL;
+    uint tRL;
+    uint tWL;
+    uint tRTP;
+    uint tWTR;
+    uint tRRD;
+    uint tWR;
+    uint tFAW;
+    uint tRFC;
+    uint tRC;
+    uint tXP;
+    uint tXS;
+    uint tXSDLL;
+    uint tCKE;
+    uint tCKESR;
+    uint tPD;
+    uint tREFPDEN;
+    uint tACTPDEN;
+    uint tPRPDEN;
+    uint tRTRS;
+
+    uint tBURST;
+    uint tRDWR;
+    uint tRDWR_R;
+    uint tWRRD;
+    uint tWRPRE;
+    uint tWRRD_R;
+    uint tRDPDEN;
+    uint tWRPDEN;
+    uint tWRAPDEN;
+
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.cpp

@@ -0,0 +1,420 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "TimeDependenciesInfoDDR4.h"
+
+using namespace std;
+
+TimeDependenciesInfoDDR4::TimeDependenciesInfoDDR4(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) {
+  mInitializeValues();
+}
+
+void TimeDependenciesInfoDDR4::mInitializeValues() {
+  burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
+  dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
+
+  tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
+  tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt();
+  tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
+  tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt();
+  tCL = tCK * mMemspecJson["memtimingspec"].toObject()["CL"].toInt();
+  tCWL = tCK * mMemspecJson["memtimingspec"].toObject()["CWL"].toInt();
+  tAL = tCK * mMemspecJson["memtimingspec"].toObject()["AL"].toInt();
+  tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt();
+  tRPRE = tCK * mMemspecJson["memtimingspec"].toObject()["RPRE"].toInt();
+  tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt();
+  tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt();
+  tCCD_S = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S"].toInt();
+  tCCD_L = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L"].toInt();
+  tRRD_S = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_S"].toInt();
+  tRRD_L = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_L"].toInt();
+  tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt();
+  tWTR_S = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_S"].toInt();
+  tWTR_L = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_L"].toInt();
+  tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt();
+  tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt();
+  tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt();
+  tXSDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XSDLL"].toInt();
+  tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt();
+  tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt();
+  tCKESR = tCK * mMemspecJson["memtimingspec"].toObject()["CKESR"].toInt();
+  tACTPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["ACTPDEN"].toInt();
+  tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt();
+  tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt();
+  tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt();
+
+  tPD = tCKE;
+  tRFC = tCK * (
+    (mMemspecJson["memtimingspec"].toObject()["REFM"].toInt() == 4) ?
+      (mMemspecJson["memtimingspec"].toObject()["RFC4"].toInt(1)) :
+      (
+        (mMemspecJson["memtimingspec"].toObject()["REFM"].toInt() == 2) ?
+          (mMemspecJson["memtimingspec"].toObject()["RFC2"].toInt(1)) :
+          (mMemspecJson["memtimingspec"].toObject()["RFC"].toInt(1))
+      )
+    );
+                   
+  tBURST = (uint) (burstLength / (float) dataRate) * tCK;
+  tRDWR = tRL + tBURST + tCK - tWL + tWPRE;
+  tRDWR_R = tRL + tBURST + tRTRS - tWL + tWPRE;
+  tWRRD_S = tWL + tBURST + tWTR_S - tAL;
+  tWRRD_L = tWL + tBURST + tWTR_L - tAL;
+  tWRRD_R = tWL + tBURST + tRTRS - tRL + tRPRE;
+  tRDAACT = tAL + tRTP + tRP;
+  tWRPRE = tWL + tBURST + tWR;
+  tWRAACT = tWRPRE + tRP;
+  tRDPDEN = tRL + tBURST + tCK;
+  tWRPDEN = tWL + tBURST + tWR;
+  tWRAPDEN = tWL + tBURST + tWR + tCK;
+
+  mPools.insert({
+    "CMD_BUS", {
+      1, {
+        {"ACT", tCK},
+        {"RD", tCK},
+        {"WR", tCK},
+        {"PREPB", tCK},
+        {"RDA", tCK},
+        {"WRA", tCK},
+        {"REFAB", tCK},
+        {"PREAB", tCK},
+        {"PDEP", tCK},
+        {"PDXP", tCK},
+        {"SREFEN", tCK},
+        {"SREFEX", tCK},
+        {"PDEA", tCK},
+        {"PDXA", tCK},
+      }
+    }
+  });
+
+  mPools.insert({
+    "NAW", {
+      4, {
+        {"ACT", tFAW},
+      }
+    }
+  });
+
+}
+
+const std::vector<QString> TimeDependenciesInfoDDR4::getPossiblePhases() {
+  return {
+    "ACT",
+    "RD",
+    "WR",
+    "PREPB",
+    "RDA",
+    "WRA",
+    "REFAB",
+    "PREAB",
+    "PDEP",
+    "PDXP",
+    "SREFEN",
+    "SREFEX",
+    "PDEA",
+    "PDXA",
+  };
+}
+
+DependencyMap TimeDependenciesInfoDDR4::mSpecializedGetDependencies() const {
+  DependencyMap dmap;
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("ACT"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC, "ACT", DependencyType::IntraBank, "tRC"},
+        {tRRD_L, "ACT", DependencyType::IntraBankGroup, "tRRD_L"},
+        {tRRD_S, "ACT", DependencyType::IntraRank, "tRRD_S"},
+        {tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"},
+        {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"},
+        {tRP, "PREPB", DependencyType::IntraBank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+        {tFAW, "NAW", DependencyType::IntraRank, "tFAW"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RD"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tCCD_L, "RD", DependencyType::IntraBank, "tCCD_L"}, //
+        {tCCD_L, "RD", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "RD", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD_L, "RDA", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "RDA", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tWRRD_L, "WR", DependencyType::IntraBank, "tWRRD_L"}, //
+        {tWRRD_L, "WR", DependencyType::IntraBankGroup, "tWRRD_L"},
+        {tWRRD_S, "WR", DependencyType::IntraRank, "tWRRD_S"},
+        {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
+        {tWRRD_L, "WRA", DependencyType::IntraBankGroup, "tWRRD_L"},
+        {tWRRD_S, "WRA", DependencyType::IntraRank, "tWRRD_S"},
+        {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WR"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, //
+        {tRDWR, "RD", DependencyType::IntraBankGroup, "tRDWR"}, //
+        {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
+        {tRDWR, "RDA", DependencyType::IntraBankGroup, "tRDWR"}, //
+        {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
+        {tCCD_L, "WR", DependencyType::IntraBank, "tCCD_L"}, //
+        {tCCD_L, "WR", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "WR", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD_L, "WRA", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "WRA", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREPB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS, "ACT", DependencyType::IntraBank, "tRAS"},
+        {tAL + tRTP, "RD", DependencyType::IntraBank, "tAL + tRTP"},
+        {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RDA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tCCD_L, "RD", DependencyType::IntraBank, "tCCD_L"},
+        {tCCD_L, "RD", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "RD", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD_L, "RDA", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "RDA", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {max({tWRRD_L, tWRPRE - tRTP - tAL}), "WR", DependencyType::IntraBank, "max(tWRRD_L, tWRPRE - tRTP - tAL)"},
+        {tWRRD_L, "WR", DependencyType::IntraBankGroup, "tWRRD_L"},
+        {tWRRD_S, "WR", DependencyType::IntraRank, "tWRRD_S"},
+        {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
+        {tWRRD_L, "WRA", DependencyType::IntraBankGroup, "tWRRD_L"},
+        {tWRRD_S, "WRA", DependencyType::IntraRank, "tWRRD_S"},
+        {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WRA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD - tAL, "ACT", DependencyType::IntraBank, "tRCD - tAL"},
+        {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"},
+        {tRDWR, "RD", DependencyType::IntraBankGroup, "tRDWR"},
+        {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
+        {tRDWR, "RDA", DependencyType::IntraBankGroup, "tRDWR"},
+        {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
+        {tCCD_L, "WR", DependencyType::IntraBank, "tCCD_L"},
+        {tCCD_L, "WR", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "WR", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD_L, "WRA", DependencyType::IntraBankGroup, "tCCD_L"},
+        {tCCD_S, "WRA", DependencyType::IntraRank, "tCCD_S"},
+        {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXSDLL, "SREFEX", DependencyType::IntraRank, "tXSDLL"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("REFAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC, "ACT", DependencyType::IntraRank, "tRC"},
+        {tRDAACT, "RDA", DependencyType::IntraRank, "tRDAACT"},
+        {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"},
+        {tRP, "PREPB", DependencyType::IntraRank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS, "ACT", DependencyType::IntraRank, "tRAS"},
+        {tAL + tRTP, "RD", DependencyType::IntraRank, "tAL + tRTP"},
+        {tAL + tRTP, "RDA", DependencyType::IntraRank, "tAL + tRTP"},
+        {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"},
+        {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDEP"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"},
+        {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"},
+        {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
+        {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
+        {tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"},
+        {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"},
+        {tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDXP"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tPD, "PDEP", DependencyType::IntraRank, "tPD"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("SREFEN"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC, "ACT", DependencyType::IntraRank, "tRC"},
+        {max({tRDPDEN, tAL + tRTP + tRP}), "RDA", DependencyType::IntraRank, "max(tRDPDEN, tAL + tRTP + tRP)"},
+        {max({tWRAPDEN, tWRPRE + tRP}), "WRA", DependencyType::IntraRank, "max(tWRAPDEN, tWRPRE + tRP)"},
+        {tRP, "PREPB", DependencyType::IntraRank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("SREFEX"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDEA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"},
+        {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"},
+        {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"},
+        {tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"},
+        {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
+        {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
+        {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDXA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tPD, "PDEA", DependencyType::IntraRank, "tPD"},
+        {tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  return dmap;
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR4.h

@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "../dramtimedependenciesbase.h"
+
+class TimeDependenciesInfoDDR4 final : public DRAMTimeDependenciesBase {
+  public:
+    TimeDependenciesInfoDDR4(const QJsonObject& memspec, const uint clk);
+
+    static const std::vector<QString> getPossiblePhases();
+
+  protected:
+    void mInitializeValues() override;
+    DependencyMap mSpecializedGetDependencies() const override;
+
+  protected:
+    uint burstLength;
+    uint dataRate;
+
+    uint tRCD;
+    uint tRP;
+    uint tRAS;
+    uint tRC;
+    uint tCL;
+    uint tCWL;
+    uint tAL;
+    uint tRL;
+    uint tRPRE;
+    uint tWPRE;
+    uint tWL;
+    uint tCCD_S;
+    uint tCCD_L;
+    uint tRRD_S;
+    uint tRRD_L;
+    uint tFAW;
+    uint tWTR_S;
+    uint tWTR_L;
+    uint tRTP;
+    uint tWR;
+    uint tRFC;
+    uint tXS;
+    uint tXSDLL;
+    uint tXP;
+    uint tCKE;
+    uint tCKESR;
+    uint tPD;
+    uint tACTPDEN;
+    uint tPRPDEN;
+    uint tREFPDEN;
+    uint tRTRS;
+
+    uint tBURST;
+    uint tRDWR;
+    uint tRDWR_R;
+    uint tWRRD_S;
+    uint tWRRD_L;
+    uint tWRRD_R;
+    uint tRDAACT;
+    uint tWRPRE;
+    uint tWRAACT;
+    uint tRDPDEN;
+    uint tWRPDEN;
+    uint tWRAPDEN;
+
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.cpp

@@ -0,0 +1,619 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "TimeDependenciesInfoDDR5.h"
+#include <cmath>
+
+using namespace std;
+
+TimeDependenciesInfoDDR5::TimeDependenciesInfoDDR5(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) {
+  mInitializeValues();
+
+}
+
+void TimeDependenciesInfoDDR5::rankIDToRankIDs(size_t rankID, size_t& dimmRID, size_t& physRID, size_t& logRID) const {
+  logRID = rankID;
+  physRID = logRID / mNumLogicalRanksPerPhysicalRank;
+  dimmRID = physRID / mNumPhysicalRanksPerDIMMRank;
+}
+
+void TimeDependenciesInfoDDR5::bankIDToBankInGroup(size_t logicalRankID, size_t bankID, size_t& bankInGroup) const {
+  bankInGroup = logicalRankID * mNumBanksPerGroup + bankID % mNumBanksPerGroup;
+
+}
+
+void TimeDependenciesInfoDDR5::mInitializeValues() {
+  mNumOfRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfRanks"].toInt();
+  mNumOfDIMMRanks = mMemspecJson["memarchitecturespec"].toObject()["nbrOfDIMMRanks"].toInt();
+  mNumPhysicalRanksPerDIMMRank = mMemspecJson["memarchitecturespec"].toObject()["nbrOfPhysicalRanks"].toInt();
+  mNumLogicalRanksPerPhysicalRank = mMemspecJson["memarchitecturespec"].toObject()["nbrOfLogicalRanks"].toInt();
+
+  mNumBanksPerGroup = mMemspecJson["memarchitecturespec"].toObject()["nbrOfBanks"].toInt(1);
+  mNumBanksPerGroup /= mMemspecJson["memarchitecturespec"].toObject()["nbrOfBankGroups"].toInt(1);
+
+  burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
+  dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
+  refMode = mMemspecJson["memarchitecturespec"].toObject()["refMode"].toInt();
+  cmdMode = mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt();
+  bitWidth = mMemspecJson["memarchitecturespec"].toObject()["width"].toInt();
+
+  tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
+  tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt();
+  tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt();
+  tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
+  tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt();
+  RBL = tCK * mMemspecJson["memtimingspec"].toObject()["BL"].toInt();
+  tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt();
+  tRPRE = tCK * mMemspecJson["memtimingspec"].toObject()["RPRE"].toInt();
+  tRPST = tCK * mMemspecJson["memtimingspec"].toObject()["RPST"].toInt();
+  tRDDQS = tCK * mMemspecJson["memtimingspec"].toObject()["RDDQS"].toInt();
+  tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt();
+  WBL = tCK * mMemspecJson["memtimingspec"].toObject()["BL"].toInt();
+  tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt();
+  tWPST = tCK * mMemspecJson["memtimingspec"].toObject()["WPST"].toInt();
+  tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt();
+  tCCD_L_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_slr"].toInt();
+  tCCD_L_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR_slr"].toInt();
+  tCCD_S_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S_slr"].toInt();
+  tCCD_S_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S_WR_slr"].toInt();
+  tCCD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_dlr"].toInt();
+  tCCD_WR_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_WR_dlr"].toInt();
+  tCCD_WR_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_WR_dpr"].toInt();
+  tRRD_S_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_S_slr"].toInt();
+  tRRD_L_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_L_slr"].toInt();
+  tRRD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RRD_dlr"].toInt();
+  tFAW_slr = tCK * mMemspecJson["memtimingspec"].toObject()["FAW_slr"].toInt();
+  tFAW_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["FAW_dlr"].toInt();
+  tWTR_L = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_L"].toInt();
+  tWTR_S = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_S"].toInt();
+  tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_slr"].toInt();
+  tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_dlr"].toInt();
+  tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC_dpr"].toInt();
+  tRFCsb_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFCsb_slr"].toInt();
+  tRFCsb_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFCsb_dlr"].toInt();
+  tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI"].toInt();
+  tREFSBRD_slr = tCK * mMemspecJson["memtimingspec"].toObject()["REFSBRD_slr"].toInt();
+  tREFSBRD_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["REFSBRD_dlr"].toInt();
+  tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt();
+  UNKNOWN = tCK * mMemspecJson["memtimingspec"].toObject()["NKNOWN"].toInt();
+  tCPDED = tCK * mMemspecJson["memtimingspec"].toObject()["CPDED"].toInt();
+  tPD = tCK * mMemspecJson["memtimingspec"].toObject()["PD"].toInt();
+  tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt();
+  tACTPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["ACTPDEN"].toInt();
+  tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt();
+  tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt();
+
+  tRC = tRAS + tRP;
+  
+  if (refMode == 1) {
+    tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_slr"].toInt();
+    tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_dlr"].toInt();
+    tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC1_dpr"].toInt();
+    tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI1"].toInt();
+  } else {
+    tRFC_slr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_slr"].toInt();
+    tRFC_dlr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_dlr"].toInt();
+    tRFC_dpr = tCK * mMemspecJson["memtimingspec"].toObject()["RFC2_dpr"].toInt();
+    tREFI = tCK * mMemspecJson["memtimingspec"].toObject()["REFI2"].toInt();
+  }
+
+  if (cmdMode == 2) {
+    shortCmdOffset = 1 * tCK;
+    longCmdOffset = 3 * tCK;
+  } else {
+    shortCmdOffset = 0 * tCK;
+    longCmdOffset = 1 * tCK;
+  }
+
+  cmdLengthDiff = tCK * mMemspecJson["memarchitecturespec"].toObject()["cmdMode"].toInt();
+  if (!(burstLength == 16 && bitWidth == 4))
+    tCCD_L_WR_slr = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L_WR2_slr"].toInt();
+
+  tBURST16 = 8 * tCK;
+  tBURST32 = 16 * tCK;
+
+  tRD_BURST = (uint) (RBL / (float) dataRate) * tCK;
+  tWR_BURST = (uint) (WBL / (float) dataRate) * tCK;
+  tWTRA = tWR - tRTP;
+  tWRRDA = tWL + tBURST16 + tWTRA;
+  tWRPRE = tWL + tBURST16 + tWR;
+  tRDAACT = tRTP + tRP;
+  tWRAACT = tWRPRE + tRP;
+  tCCD_L_RTW_slr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE;
+  tCCD_S_RTW_slr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE;
+  tCCD_RTW_dlr = tRL - tWL + tBURST16 + 2 * tCK - tRDDQS + tRPST + tWPRE;
+  tRDRD_dpr = tRD_BURST + tRTRS;
+  tRDRD_ddr = tRD_BURST + tRTRS;
+  tRDWR_dpr = tRL - tWL + tRD_BURST + tRTRS - tRDDQS + tRPST + tWPRE;
+  tRDWR_ddr = tRL - tWL + tRD_BURST + tRTRS - tRDDQS + tRPST + tWPRE;
+  tCCD_L_WTR_slr = tWL + tBURST16 + tWTR_L;
+  tCCD_S_WTR_slr = tWL + tBURST16 + tWTR_S;
+  tCCD_WTR_dlr = tWL + tBURST16 + tWTR_S;
+  tWRWR_dpr = max(tCCD_WR_dpr, tBURST16 + tRTRS);
+  tWRWR_ddr = tBURST16 + tRTRS;
+  tWRRD_dpr = tWL - tRL + tBURST16 + tRTRS + tRDDQS + tWPST + tRPRE;
+  tWRRD_ddr = tWL - tRL + tBURST16 + tRTRS + tRDDQS + tWPST + tRPRE;
+  tRDPDEN = tRL + tBURST16 + cmdLengthDiff;
+  tWRPDEN = tWL + tBURST16 + tWR + cmdLengthDiff;
+  tWRAPDEN = tWL + tBURST16 + tWR + cmdLengthDiff;
+
+  mPools.insert({
+    "CMD_BUS", {
+      1, {
+        {"ACT", 2 * tCK},
+        {"RD", 2 * tCK},
+        {"WR", 2 * tCK},
+        {"RDA", 2 * tCK},
+        {"WRA", 2 * tCK},
+        {"PREPB", tCK},
+        {"PREAB", tCK},
+        {"REFAB", tCK},
+        {"PRESB", tCK},
+        {"RFMAB", tCK},
+        {"REFSB", tCK},
+        {"RFMSB", tCK},
+      }
+    }
+  });
+
+  mPools.insert({
+    "FAW_LOGICAL", {
+      4, {
+        {"ACT", tFAW_slr - longCmdOffset},
+        {"REFSB", tFAW_slr - shortCmdOffset},
+        {"RFMSB", tFAW_slr - shortCmdOffset},
+      }
+    }
+  });
+
+  mPools.insert({
+    "FAW_PHYSICAL", {
+      4, {
+        {"ACT", tFAW_dlr - longCmdOffset},
+        {"REFSB", tFAW_dlr - shortCmdOffset},
+        {"RFMSB", tFAW_dlr - shortCmdOffset},
+      }
+    }
+  });
+
+}
+
+const std::vector<QString> TimeDependenciesInfoDDR5::getPossiblePhases() {
+  return {
+    "ACT",
+    "RD",
+    "WR",
+    "PRESB",
+    "PREPB",
+    "RDA",
+    "WRA",
+    "RFMAB",
+    "REFSB",
+    "RFMSB",
+    "REFAB",
+    "PREAB",
+    "PDEP",
+    "PDXP",
+    "SREFEN",
+    "SREFEX",
+    "PDEA",
+    "PDXA",
+  };
+}
+
+DependencyMap TimeDependenciesInfoDDR5::mSpecializedGetDependencies() const {
+  DependencyMap dmap;
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("ACT"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC, "ACT", DependencyType::IntraBank, "tRC"},
+        {tRRD_L_slr, "ACT", DependencyType::IntraBankGroup, "tRRD_L_slr"},
+        {tRRD_S_slr, "ACT", DependencyType::IntraLogicalRank, "tRRD_S_slr"},
+        {tRRD_dlr, "ACT", DependencyType::IntraPhysicalRank, "tRRD_dlr"},
+        {tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"},
+        {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"},
+        {tWRAACT + tBURST16, "WRA", DependencyType::IntraBank, "tWRAACT + tBURST16"},
+        {tRP - cmdLengthDiff, "PREPB", DependencyType::IntraBank, "tRP - tCK"},
+        {tRP - cmdLengthDiff, "PRESB", DependencyType::IntraBankInGroup, "tRP - tCK"},
+        {tRP - cmdLengthDiff, "PREAB", DependencyType::IntraLogicalRank, "tRP - tCK"},
+        {tRFC_slr - cmdLengthDiff, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"},
+        {tRFC_slr - cmdLengthDiff, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr - tCK"},
+        {tRFCsb_slr - cmdLengthDiff, "REFSB", DependencyType::IntraBankInGroup, "tRFCsb_slr - tCK"},
+        {tREFSBRD_slr - cmdLengthDiff, "REFSB", DependencyType::IntraLogicalRank, "tREFSBRD_slr - tCK"},
+        {tREFSBRD_dlr - cmdLengthDiff, "REFSB", DependencyType::IntraPhysicalRank, "tREFSBRD_dlr - tCK"},
+        {tRFCsb_slr - cmdLengthDiff, "RFMSB", DependencyType::IntraBankInGroup, "tRFCsb_slr - tCK"},
+        {tREFSBRD_slr - cmdLengthDiff, "RFMSB", DependencyType::IntraLogicalRank, "tREFSBRD_slr - tCK"},
+        {tREFSBRD_dlr - cmdLengthDiff, "RFMSB", DependencyType::IntraPhysicalRank, "tREFSBRD_dlr - tCK"},
+        {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
+        {tFAW_slr - longCmdOffset, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"},
+        {tFAW_dlr - longCmdOffset, "FAW_PHYSICAL", DependencyType::IntraPhysicalRank, "tFAW_dlr"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RD"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
+        {tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"},
+        {tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
+        {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr"},
+        {tCCD_dlr + tBURST32, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"},
+        {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr"},
+        {tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"},
+        {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr"},
+        {tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"},
+        {tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"},
+        {tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
+        {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr"},
+        {tCCD_dlr + tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"},
+        {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr"},
+        {tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"},
+        {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr"},
+        {tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"},
+        {tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"},
+        {tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"},
+        {tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"},
+        {tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"},
+        {tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"},
+        {tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"},
+        {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr"},
+        {tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"},
+        {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr"},
+        {tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"},
+        {tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"},
+        {tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"},
+        {tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"},
+        {tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"},
+        {tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"},
+        {tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"},
+        {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr"},
+        {tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"},
+        {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr"},
+        {tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"},
+        {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WR"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
+        {tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"},
+        {tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"},
+        {tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"},
+        {tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"},
+        {tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"},
+        {tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"},
+        {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr"},
+        {tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"},
+        {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr"},
+        {tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"},
+        {tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"},
+        {tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"},
+        {tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"},
+        {tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"},
+        {tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"},
+        {tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"},
+        {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr"},
+        {tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"},
+        {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr"},
+        {tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"},
+        {tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"},
+        {tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
+        {tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"},
+        {tCCD_WR_dlr + tBURST32, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"},
+        {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr"},
+        {tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"},
+        {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr"},
+        {tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"},
+        {tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"},
+        {tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16"},
+        {tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
+        {tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"},
+        {tCCD_WR_dlr + tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"},
+        {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr"},
+        {tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"},
+        {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr"},
+        {tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"},
+        {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREPB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBank, "tRAS + tCK"},
+        {tRTP + cmdLengthDiff, "RD", DependencyType::IntraBank, "tRTP + tCK"},
+        {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBank, "tWRPRE + tCK"},
+        {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBank, "tWRPRE + tCK + tBURST16"},
+        {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"},
+        {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"},
+        {tPPD, "PRESB", DependencyType::IntraPhysicalRank, "tPPD"},
+        {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RDA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
+        {tCCD_L_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_slr"},
+        {tCCD_S_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
+        {tCCD_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr"},
+        {tCCD_dlr + tBURST32, "RD", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"},
+        {tRDRD_dpr, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr"},
+        {tRDRD_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"},
+        {tRDRD_ddr, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr"},
+        {tRDRD_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"},
+        {tCCD_L_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_slr"},
+        {tCCD_S_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_slr"},
+        {tCCD_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr"},
+        {tCCD_dlr + tBURST32, "RDA", DependencyType::IntraPhysicalRank, "tCCD_dlr + tBURST32"},
+        {tRDRD_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr"},
+        {tRDRD_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDRD_dpr + tBURST16"},
+        {tRDRD_ddr, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr"},
+        {tRDRD_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDRD_ddr + tBURST16"},
+        {tWRRDA, "WR", DependencyType::IntraBank, "tWRRDA"},
+        {tWRRDA + tBURST16, "WR", DependencyType::IntraBank, "tWRRDA + tBURST16"},
+        {tCCD_L_WTR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"},
+        {tCCD_L_WTR_slr + tBURST16, "WR", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"},
+        {tCCD_S_WTR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"},
+        {tCCD_S_WTR_slr + tBURST16, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"},
+        {tCCD_WTR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"},
+        {tCCD_WTR_dlr + tBURST16, "WR", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"},
+        {tWRRD_dpr, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr"},
+        {tWRRD_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"},
+        {tWRRD_ddr, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr"},
+        {tWRRD_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"},
+        {tCCD_L_WTR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr"},
+        {tCCD_L_WTR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WTR_slr + tBURST16"},
+        {tCCD_S_WTR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr"},
+        {tCCD_S_WTR_slr + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WTR_slr + tBURST16"},
+        {tCCD_WTR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr"},
+        {tCCD_WTR_dlr + tBURST16, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WTR_dlr + tBURST16"},
+        {tWRRD_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr"},
+        {tWRRD_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRRD_dpr + tBURST16"},
+        {tWRRD_ddr, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr"},
+        {tWRRD_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRRD_ddr + tBURST16"},
+        {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WRA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
+        {tCCD_L_RTW_slr, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"},
+        {tCCD_L_RTW_slr + tBURST16, "RD", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"},
+        {tCCD_S_RTW_slr, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"},
+        {tCCD_S_RTW_slr + tBURST16, "RD", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"},
+        {tCCD_RTW_dlr, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"},
+        {tCCD_RTW_dlr + tBURST16, "RD", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"},
+        {tRDWR_dpr, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr"},
+        {tRDWR_dpr + tBURST16, "RD", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"},
+        {tRDWR_ddr, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr"},
+        {tRDWR_ddr + tBURST16, "RD", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"},
+        {tCCD_L_RTW_slr, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr"},
+        {tCCD_L_RTW_slr + tBURST16, "RDA", DependencyType::IntraBankGroup, "tCCD_L_RTW_slr + tBURST16"},
+        {tCCD_S_RTW_slr, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr"},
+        {tCCD_S_RTW_slr + tBURST16, "RDA", DependencyType::IntraLogicalRank, "tCCD_S_RTW_slr + tBURST16"},
+        {tCCD_RTW_dlr, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr"},
+        {tCCD_RTW_dlr + tBURST16, "RDA", DependencyType::IntraPhysicalRank, "tCCD_RTW_dlr + tBURST16"},
+        {tRDWR_dpr, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr"},
+        {tRDWR_dpr + tBURST16, "RDA", DependencyType::IntraDIMMRank, "tRDWR_dpr + tBURST16"},
+        {tRDWR_ddr, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr"},
+        {tRDWR_ddr + tBURST16, "RDA", DependencyType::InterDIMMRank, "tRDWR_ddr + tBURST16"},
+        {tCCD_L_WR_slr, "WR", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"},
+        {tCCD_S_WR_slr, "WR", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
+        {tCCD_WR_dlr, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"},
+        {tCCD_WR_dlr + tBURST32, "WR", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"},
+        {tWRWR_dpr, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr"},
+        {tWRWR_dpr + tBURST16, "WR", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"},
+        {tWRWR_ddr, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr"},
+        {tWRWR_ddr + tBURST16, "WR", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"},
+        {tCCD_L_WR_slr, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr"},
+        {tCCD_L_WR_slr + tBURST16, "WRA", DependencyType::IntraBankGroup, "tCCD_L_WR_slr + tBURST16"},
+        {tCCD_S_WR_slr, "WRA", DependencyType::IntraLogicalRank, "tCCD_S_WR_slr"},
+        {tCCD_WR_dlr, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr"},
+        {tCCD_WR_dlr + tBURST32, "WRA", DependencyType::IntraPhysicalRank, "tCCD_WR_dlr + tBURST32"},
+        {tWRWR_dpr, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr"},
+        {tWRWR_dpr + tBURST16, "WRA", DependencyType::IntraDIMMRank, "tWRWR_dpr + tBURST16"},
+        {tWRWR_ddr, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr"},
+        {tWRWR_ddr + tBURST16, "WRA", DependencyType::InterDIMMRank, "tWRWR_ddr + tBURST16"},
+        {2 * tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("REFAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"},
+        {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"},
+        {tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK"},
+        {tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16"},
+        {tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"},
+        {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
+        {tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
+        {tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
+        {tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
+        {tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
+        {tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
+        {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RFMAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRC + tCK"},
+        {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraPhysicalRank, "tRDAACT + tCK"},
+        {tWRPRE + tRP + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK"},
+        {tWRPRE + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tRP + tCK + tBURST16"},
+        {tRP, "PREPB", DependencyType::IntraLogicalRank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraLogicalRank, "tRP"},
+        {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
+        {tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
+        {tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
+        {tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
+        {tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
+        {tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
+        {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("REFSB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRC + tCK"},
+        {tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"},
+        {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRDAACT + tCK"},
+        {tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK"},
+        {tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRAACT + tRP + tCK + tBURST16"},
+        {tRP, "PREPB", DependencyType::IntraBankInGroup, "tRP"},
+        {tRP, "PRESB", DependencyType::IntraBankInGroup, "tRP"},
+        {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
+        {tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
+        {tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
+        {tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
+        {tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
+        {tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
+        {tRFCsb_slr, "REFSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"},
+        {tRFCsb_dlr, "REFSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"},
+        {tRFCsb_slr, "RFMSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"},
+        {tRFCsb_dlr, "RFMSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"},
+        {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
+        {tFAW_slr - shortCmdOffset, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"},
+        {tFAW_dlr - shortCmdOffset, "FAW_PHYSICAL", DependencyType::IntraPhysicalRank, "tFAW_dlr"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RFMSB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC + cmdLengthDiff, "ACT", DependencyType::IntraBankGroup, "tRC + tCK"},
+        {tRRD_L_slr + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRRD_L_slr + tCK"},
+        {tRDAACT + cmdLengthDiff, "RDA", DependencyType::IntraBankGroup, "tRDAACT + tCK"},
+        {tWRAACT + tRP + cmdLengthDiff, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK"},
+        {tWRAACT + tRP + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankGroup, "tWRAACT + tRP + tCK + tBURST16"},
+        {tRP, "PREPB", DependencyType::IntraBankGroup, "tRP"},
+        {tRP, "PRESB", DependencyType::IntraBankGroup, "tRP"},
+        {tRFC_slr, "REFAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
+        {tRFC_dlr, "REFAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
+        {tRFC_dpr, "REFAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
+        {tRFC_slr, "RFMAB", DependencyType::IntraLogicalRank, "tRFC_slr"},
+        {tRFC_dlr, "RFMAB", DependencyType::IntraPhysicalRank, "tRFC_dlr"},
+        {tRFC_dpr, "RFMAB", DependencyType::IntraDIMMRank, "tRFC_dpr"},
+        {tRFCsb_slr, "REFSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"},
+        {tRFCsb_dlr, "REFSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"},
+        {tRFCsb_slr, "RFMSB", DependencyType::IntraLogicalRank, "tRFCsb_slr"},
+        {tRFCsb_dlr, "RFMSB", DependencyType::IntraPhysicalRank, "tRFCsb_dlr"},
+        {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
+        {tFAW_slr - shortCmdOffset, "FAW_LOGICAL", DependencyType::IntraLogicalRank, "tFAW_slr"},
+        {tFAW_dlr - shortCmdOffset, "FAW_PHYSICAL", DependencyType::IntraPhysicalRank, "tFAW_dlr"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraLogicalRank, "tRAS + tCK"},
+        {tRTP + cmdLengthDiff, "RD", DependencyType::IntraLogicalRank, "tRTP + tCK"},
+        {tRTP + cmdLengthDiff, "RDA", DependencyType::IntraLogicalRank, "tRTP + tCK"},
+        {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK"},
+        {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16"},
+        {tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK"},
+        {tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraLogicalRank, "tWRPRE + tCK + tBURST16"},
+        {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"},
+        {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"},
+        {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PRESB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS + cmdLengthDiff, "ACT", DependencyType::IntraBankInGroup, "tRAS + tCK"},
+        {tRTP + cmdLengthDiff, "RD", DependencyType::IntraBankInGroup, "tRTP + tCK"},
+        {tRTP + cmdLengthDiff, "RDA", DependencyType::IntraBankInGroup, "tRTP + tCK"},
+        {tWRPRE + cmdLengthDiff, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK"},
+        {tWRPRE + cmdLengthDiff + tBURST16, "WR", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16"},
+        {tWRPRE + cmdLengthDiff, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK"},
+        {tWRPRE + cmdLengthDiff + tBURST16, "WRA", DependencyType::IntraBankInGroup, "tWRPRE + tCK + tBURST16"},
+        {tPPD, "PREPB", DependencyType::IntraPhysicalRank, "tPPD"},
+        {tPPD, "PREAB", DependencyType::IntraPhysicalRank, "tPPD"},
+        {tCK, "CMD_BUS", DependencyType::InterDIMMRank, "CommandBus"},
+      }
+    )
+  );
+
+  return dmap;
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoDDR5.h

@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "../dramtimedependenciesbase.h"
+
+class TimeDependenciesInfoDDR5 final : public DRAMTimeDependenciesBase {
+  public:
+    TimeDependenciesInfoDDR5(const QJsonObject& memspec, const uint clk);
+
+    static const std::vector<QString> getPossiblePhases();
+
+    void rankIDToRankIDs(size_t rankID, size_t& dimmRID, size_t& physRID, size_t& logRID) const;
+    void bankIDToBankInGroup(size_t logicalRankID, size_t bankID, size_t& bankInGroup) const;
+
+  protected:
+    void mInitializeValues() override;
+    DependencyMap mSpecializedGetDependencies() const override;
+
+  protected:
+    uint mNumOfRanks;
+    uint mNumOfDIMMRanks;
+    uint mNumLogicalRanksPerPhysicalRank;
+    uint mNumPhysicalRanksPerDIMMRank;
+    uint mNumBanksPerGroup;
+
+    uint burstLength;
+    uint dataRate;
+    uint refMode;
+
+    uint tRCD;
+    uint tPPD;
+    uint tRP;
+    uint tRAS;
+    uint tRC;
+    uint tRL;
+    uint RBL;
+    uint tRTP;
+    uint tRPRE;
+    uint tRPST;
+    uint tRDDQS;
+    uint tWL;
+    uint WBL;
+    uint tWPRE;
+    uint tWPST;
+    uint tWR;
+    uint tCCD_L_slr;
+    uint tCCD_L_WR_slr;
+    uint tCCD_S_slr;
+    uint tCCD_S_WR_slr;
+    uint tCCD_dlr;
+    uint tCCD_WR_dlr;
+    uint tCCD_WR_dpr;
+    uint tRRD_S_slr;
+    uint tRRD_L_slr;
+    uint tRRD_dlr;
+    uint tFAW_slr;
+    uint tFAW_dlr;
+    uint tWTR_L;
+    uint tWTR_S;
+    uint tRFC_slr;
+    uint tRFC_dlr;
+    uint tRFC_dpr;
+    uint tRFCsb_slr;
+    uint tRFCsb_dlr;
+    uint tREFI;
+    uint tREFSBRD_slr;
+    uint tREFSBRD_dlr;
+    uint tRTRS;
+    uint UNKNOWN;
+    uint tCPDED;
+    uint tPD;
+    uint tXP;
+    uint tACTPDEN;
+    uint tPRPDEN;
+    uint tREFPDEN;
+
+    uint tRD_BURST;
+    uint tWR_BURST;
+    uint tWTRA;
+    uint tWRRDA;
+    uint tWRPRE;
+    uint tRDAACT;
+    uint tWRAACT;
+    uint tCCD_L_RTW_slr;
+    uint tCCD_S_RTW_slr;
+    uint tCCD_RTW_dlr;
+    uint tRDRD_dpr;
+    uint tRDRD_ddr;
+    uint tRDWR_dpr;
+    uint tRDWR_ddr;
+    uint tCCD_L_WTR_slr;
+    uint tCCD_S_WTR_slr;
+    uint tCCD_WTR_dlr;
+    uint tWRWR_dpr;
+    uint tWRWR_ddr;
+    uint tWRRD_dpr;
+    uint tWRRD_ddr;
+    uint tRDPDEN;
+    uint tWRPDEN;
+    uint tWRAPDEN;
+
+    uint cmdMode;
+    uint bitWidth;
+    uint cmdLengthDiff;
+    uint shortCmdOffset;
+    uint longCmdOffset;
+
+    uint tBURST16;
+    uint tBURST32;
+    
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.cpp

@@ -0,0 +1,431 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "TimeDependenciesInfoHBM2.h"
+
+using namespace std;
+
+TimeDependenciesInfoHBM2::TimeDependenciesInfoHBM2(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) {
+  mInitializeValues();
+}
+
+void TimeDependenciesInfoHBM2::mInitializeValues() {
+  burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
+  dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
+
+  tRP = tCK * mMemspecJson["memtimingspec"].toObject()["RP"].toInt();
+  tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
+  tRC = tCK * mMemspecJson["memtimingspec"].toObject()["RC"].toInt();
+  tRCDRD = tCK * mMemspecJson["memtimingspec"].toObject()["RCDRD"].toInt();
+  tRCDWR = tCK * mMemspecJson["memtimingspec"].toObject()["RCDWR"].toInt();
+  tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt();
+  tRRDS = tCK * mMemspecJson["memtimingspec"].toObject()["RRDS"].toInt();
+  tRRDL = tCK * mMemspecJson["memtimingspec"].toObject()["RRDL"].toInt();
+  tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt();
+  tPL = tCK * mMemspecJson["memtimingspec"].toObject()["PL"].toInt();
+  tCCDS = tCK * mMemspecJson["memtimingspec"].toObject()["CCDS"].toInt();
+  tCCDL = tCK * mMemspecJson["memtimingspec"].toObject()["CCDL"].toInt();
+  tRTW = tCK * mMemspecJson["memtimingspec"].toObject()["RTW"].toInt();
+  tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt();
+  tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt();
+  tWTRS = tCK * mMemspecJson["memtimingspec"].toObject()["WTRS"].toInt();
+  tWTRL = tCK * mMemspecJson["memtimingspec"].toObject()["WTRL"].toInt();
+  tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt();
+  tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt();
+  tRFC = tCK * mMemspecJson["memtimingspec"].toObject()["RFC"].toInt();
+  tRFCSB = tCK * mMemspecJson["memtimingspec"].toObject()["RFCSB"].toInt();
+  tRREFD = tCK * mMemspecJson["memtimingspec"].toObject()["RREFD"].toInt();
+  tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt();
+  tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt();
+
+  tPD = tCKE;
+  tCKESR = tCKE + tCK;
+
+  tBURST = (uint) (burstLength / (float) dataRate) * tCK;
+  tRDPDE = tRL + tPL + tBURST + tCK;
+  tRDSRE = tRDPDE;
+  tWRPRE = tWL + tBURST + tWR;
+  tWRPDE = tWL + tPL + tBURST + tCK + tWR;
+  tWRAPDE = tWL + tPL + tBURST + tCK + tWR;
+  tWRRDS = tWL + tBURST + tWTRS;
+  tWRRDL = tWL + tBURST + tWTRL;
+
+  mPools.insert({
+    "RAS_BUS", {
+      1, {
+        {"ACT", 2*tCK},
+        {"PREPB", tCK},
+        {"PREAB", tCK},
+        {"REFPB", tCK},
+        {"REFAB", tCK},
+        {"PDEA", tCK},
+        {"PDXA", tCK},
+        {"PDEP", tCK},
+        {"PDXP", tCK},
+        {"SREFEN", tCK},
+        {"SREFEX", tCK},
+      }
+    }
+  });
+
+  mPools.insert({
+    "CAS_BUS", {
+      1, {
+        {"RD", tCK},
+        {"RDA", tCK},
+        {"WR", tCK},
+        {"WRA", tCK},
+        {"PDEA", tCK},
+        {"PDXA", tCK},
+        {"PDEP", tCK},
+        {"PDXP", tCK},
+        {"SREFEN", tCK},
+        {"SREFEX", tCK},
+      }
+    }
+  });
+
+  mPools.insert({
+    "NAW", {
+      4, {
+        {"ACT", tFAW},
+        {"REFPB", tFAW},
+      }
+    }
+  });
+  
+}
+
+const std::vector<QString> TimeDependenciesInfoHBM2::getPossiblePhases() {
+  return {
+    "ACT",
+    "RD",
+    "WR",
+    "PREPB",
+    "RDA",
+    "WRA",
+    "REFPB",
+    "REFAB",
+    "PREAB",
+    "PDEP",
+    "PDXP",
+    "SREFEN",
+    "SREFEX",
+    "PDEA",
+    "PDXA",
+  };
+}
+
+DependencyMap TimeDependenciesInfoHBM2::mSpecializedGetDependencies() const {
+  DependencyMap dmap;
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("ACT"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC, "ACT", DependencyType::IntraBank, "tRC"},
+        {tRRDL, "ACT", DependencyType::IntraBankGroup, "tRRDL"},
+        {tRRDS, "ACT", DependencyType::IntraRank, "tRRDS"},
+        {tRTP + tRP - tCK, "RDA", DependencyType::IntraBank, "tRTP + tRP - tCK"},
+        {tWRPRE + tRP - tCK, "WRA", DependencyType::IntraBank, "tWRPRE + tRP - tCK"},
+        {tRP - tCK, "PREPB", DependencyType::IntraBank, "tRP - tCK"},
+        {tRP - tCK, "PREAB", DependencyType::IntraRank, "tRP - tCK"},
+        {tXP - tCK, "PDXA", DependencyType::IntraRank, "tXP - tCK"},
+        {tXP - tCK, "PDXP", DependencyType::IntraRank, "tXP - tCK"},
+        {tRFC - tCK, "REFAB", DependencyType::IntraRank, "tRFC - tCK"},
+        {tRFCSB - tCK, "REFPB", DependencyType::IntraBank, "tRFCSB - tCK"},
+        {tRREFD - tCK, "REFPB", DependencyType::IntraBankGroup, "tRREFD - tCK"},
+        {tRREFD - tCK, "REFPB", DependencyType::IntraRank, "tRREFD - tCK"},
+        {tXS - tCK, "SREFEX", DependencyType::IntraRank, "tXS - tCK"},
+        {2 * tCK, "RAS_BUS", DependencyType::InterRank, "2 * tCK"},
+        {tFAW, "NAW", DependencyType::IntraRank, "tFAW"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RD"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCDRD + tCK, "ACT", DependencyType::IntraBank, "tRCDRD + tCK"},
+        {tCCDL, "RD", DependencyType::IntraBank, "tCCDL"},
+        {tCCDL, "RD", DependencyType::IntraBankGroup, "tCCDL"},
+        {tCCDS, "RD", DependencyType::IntraRank, "tCCDS"},
+        {tCCDL, "RDA", DependencyType::IntraBankGroup, "tCCDL"},
+        {tCCDS, "RDA", DependencyType::IntraRank, "tCCDS"},
+        {tWRRDL, "WR", DependencyType::IntraBank, "tWRRDL"},
+        {tWRRDL, "WR", DependencyType::IntraBankGroup, "tWRRDL"},
+        {tWRRDS, "WR", DependencyType::IntraRank, "tWRRDS"},
+        {tWRRDL, "WRA", DependencyType::IntraBankGroup, "tWRRDL"},
+        {tWRRDS, "WRA", DependencyType::IntraRank, "tWRRDS"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WR"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCDWR + tCK, "ACT", DependencyType::IntraBank, "tRCDWR + tCK"},
+        {tRTW, "RD", DependencyType::IntraBank, "tRTW"},
+        {tRTW, "RD", DependencyType::IntraBankGroup, "tRTW"},
+        {tRTW, "RD", DependencyType::IntraRank, "tRTW"},
+        {tRTW, "RDA", DependencyType::IntraBankGroup, "tRTW"},
+        {tRTW, "RDA", DependencyType::IntraRank, "tRTW"},
+        {tCCDL, "WR", DependencyType::IntraBank, "tCCDL"},
+        {tCCDL, "WR", DependencyType::IntraBankGroup, "tCCDL"},
+        {tCCDS, "WR", DependencyType::IntraRank, "tCCDS"},
+        {tCCDL, "WRA", DependencyType::IntraBankGroup, "tCCDL"},
+        {tCCDS, "WRA", DependencyType::IntraRank, "tCCDS"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREPB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS + tCK, "ACT", DependencyType::IntraBank, "tRAS + tCK"},
+        {tRTP, "RD", DependencyType::IntraBank, "tRTP"},
+        {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RDA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCDRD + tCK, "ACT", DependencyType::IntraBank, "tRCDRD + tCK"},
+        {tCCDL, "RD", DependencyType::IntraBank, "tCCDL"},
+        {tCCDL, "RD", DependencyType::IntraBankGroup, "tCCDL"},
+        {tCCDS, "RD", DependencyType::IntraRank, "tCCDS"},
+        {tCCDL, "RDA", DependencyType::IntraBankGroup, "tCCDL"},
+        {tCCDS, "RDA", DependencyType::IntraRank, "tCCDS"},
+        {tWL + tBURST + max({tWR - tRTP, tWTRL}), "WR", DependencyType::IntraBank, "tWL + tBURST + max(tWR - tRTP, tWTRL)"},
+        {tWRRDL, "WR", DependencyType::IntraBankGroup, "tWRRDL"},
+        {tWRRDS, "WR", DependencyType::IntraRank, "tWRRDS"},
+        {tWRRDL, "WRA", DependencyType::IntraBankGroup, "tWRRDL"},
+        {tWRRDS, "WRA", DependencyType::IntraRank, "tWRRDS"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WRA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCDWR + tCK, "ACT", DependencyType::IntraBank, "tRCDWR + tCK"},
+        {tRTW, "RD", DependencyType::IntraBank, "tRTW"},
+        {tRTW, "RD", DependencyType::IntraBankGroup, "tRTW"},
+        {tRTW, "RD", DependencyType::IntraRank, "tRTW"},
+        {tRTW, "RDA", DependencyType::IntraBankGroup, "tRTW"},
+        {tRTW, "RDA", DependencyType::IntraRank, "tRTW"},
+        {tCCDL, "WR", DependencyType::IntraBank, "tCCDL"},
+        {tCCDL, "WR", DependencyType::IntraBankGroup, "tCCDL"},
+        {tCCDS, "WR", DependencyType::IntraRank, "tCCDS"},
+        {tCCDL, "WRA", DependencyType::IntraBankGroup, "tCCDL"},
+        {tCCDS, "WRA", DependencyType::IntraRank, "tCCDS"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("REFPB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC + tCK, "ACT", DependencyType::IntraBank, "tRC + tCK"},
+        {tRRDL + tCK, "ACT", DependencyType::IntraBankGroup, "tRRDL + tCK"},
+        {tRRDS + tCK, "ACT", DependencyType::IntraRank, "tRRDS + tCK"},
+        {tRTP + tRP, "RDA", DependencyType::IntraBank, "tRTP + tRP"},
+        {tWRPRE + tRP, "WRA", DependencyType::IntraBank, "tWRPRE + tRP"},
+        {tRP, "PREPB", DependencyType::IntraBank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tRFCSB, "REFPB", DependencyType::IntraBank, "tRFCSB"},
+        {tRREFD, "REFPB", DependencyType::IntraBankGroup, "tRREFD"},
+        {tRREFD, "REFPB", DependencyType::IntraRank, "tRREFD"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"},
+        {tFAW, "NAW", DependencyType::IntraRank, "tFAW"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("REFAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC + tCK, "ACT", DependencyType::IntraRank, "tRC + tCK"},
+        {tRTP + tRP, "RDA", DependencyType::IntraRank, "tRTP + tRP"},
+        {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"},
+        {tRP, "PREPB", DependencyType::IntraRank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tRFCSB, "REFPB", DependencyType::IntraRank, "tRFCSB"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS + tCK, "ACT", DependencyType::IntraRank, "tRAS + tCK"},
+        {tRTP, "RD", DependencyType::IntraRank, "tRTP"},
+        {tRTP, "RDA", DependencyType::IntraRank, "tRTP"},
+        {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"},
+        {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tRFCSB, "REFPB", DependencyType::IntraRank, "tRFCSB"},
+        {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDEP"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRDPDE, "RD", DependencyType::IntraRank, "tRDPDE"},
+        {tRDPDE, "RDA", DependencyType::IntraRank, "tRDPDE"},
+        {tWRAPDE, "WRA", DependencyType::IntraRank, "tWRAPDE"},
+        {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"},
+        {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDXP"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tPD, "PDEP", DependencyType::IntraRank, "tPD"},
+        {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"},
+        {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("SREFEN"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRC + tCK, "ACT", DependencyType::IntraRank, "tRC + tCK"},
+        {max({tRTP + tRP, tRDSRE}), "RDA", DependencyType::IntraRank, "max(tRTP + tRP, tRDSRE)"},
+        {tWRPRE + tRP, "WRA", DependencyType::IntraRank, "tWRPRE + tRP"},
+        {tRP, "PREPB", DependencyType::IntraRank, "tRP"},
+        {tRP, "PREAB", DependencyType::IntraRank, "tRP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFC, "REFAB", DependencyType::IntraRank, "tRFC"},
+        {tRFCSB, "REFPB", DependencyType::IntraRank, "tRFCSB"},
+        {tXS, "SREFEX", DependencyType::IntraRank, "tXS"},
+        {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"},
+        {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("SREFEX"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tCKESR, "SREFEN", DependencyType::IntraRank, "tCKESR"},
+        {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"},
+        {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDEA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRDPDE, "RD", DependencyType::IntraRank, "tRDPDE"},
+        {tRDPDE, "RDA", DependencyType::IntraRank, "tRDPDE"},
+        {tWRPDE, "WR", DependencyType::IntraRank, "tWRPDE"},
+        {tWRAPDE, "WRA", DependencyType::IntraRank, "tWRAPDE"},
+        {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"},
+        {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"},
+        {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDXA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tPD, "PDEA", DependencyType::IntraRank, "tPD"},
+        {tCK, "RAS_BUS", DependencyType::InterRank, "tCK"},
+        {tCK, "CAS_BUS", DependencyType::InterRank, "tCK"},
+      }
+    )
+  );
+
+  return dmap;
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoHBM2.h

@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "../dramtimedependenciesbase.h"
+
+class TimeDependenciesInfoHBM2 final : public DRAMTimeDependenciesBase {
+  public:
+    TimeDependenciesInfoHBM2(const QJsonObject& memspec, const uint clk);
+
+    static const std::vector<QString> getPossiblePhases();
+
+  protected:
+    void mInitializeValues() override;
+    DependencyMap mSpecializedGetDependencies() const override;
+
+  protected:
+    uint burstLength;
+    uint dataRate;
+
+    uint tRP;
+    uint tRAS;
+    uint tRC;
+    uint tRCDRD;
+    uint tRCDWR;
+    uint tRTP;
+    uint tRRDS;
+    uint tRRDL;
+    uint tRL;
+    uint tPL;
+    uint tCCDS;
+    uint tCCDL;
+    uint tRTW;
+    uint tWL;
+    uint tWR;
+    uint tWTRS;
+    uint tWTRL;
+    uint tCKE;
+    uint tPD;
+    uint tXP;
+    uint tRFC;
+    uint tRFCSB;
+    uint tRREFD;
+    uint tXS;
+    uint tCKESR;
+    uint tFAW;
+
+    uint tBURST;
+    uint tRDPDE;
+    uint tRDSRE;
+    uint tWRPRE;
+    uint tWRPDE;
+    uint tWRAPDE;
+    uint tWRRDS;
+    uint tWRRDL;
+
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.cpp

@@ -0,0 +1,442 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "TimeDependenciesInfoLPDDR4.h"
+
+using namespace std;
+
+TimeDependenciesInfoLPDDR4::TimeDependenciesInfoLPDDR4(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) {
+  mInitializeValues();
+}
+
+void TimeDependenciesInfoLPDDR4::mInitializeValues() {
+  burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
+  dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
+
+  tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt();
+  tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
+  tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
+  tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt();
+  tRPpb = tCK * mMemspecJson["memtimingspec"].toObject()["RPpb"].toInt();
+  tRPab = tCK * mMemspecJson["memtimingspec"].toObject()["RPab"].toInt();
+  tRCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RCpb"].toInt();
+  tRCab = tCK * mMemspecJson["memtimingspec"].toObject()["RCab"].toInt();
+  tCCD = tCK * mMemspecJson["memtimingspec"].toObject()["CCD"].toInt();
+  tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt();
+  tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt();
+  tWTR = tCK * mMemspecJson["memtimingspec"].toObject()["WTR"].toInt();
+  tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt();
+  tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt();
+  tRPST = tCK * mMemspecJson["memtimingspec"].toObject()["RPST"].toInt();
+  tDQSCK = tCK * mMemspecJson["memtimingspec"].toObject()["DQSCK"].toInt();
+  tDQSS = tCK * mMemspecJson["memtimingspec"].toObject()["DQSS"].toInt();
+  tDQS2DQ = tCK * mMemspecJson["memtimingspec"].toObject()["DQS2DQ"].toInt();
+  tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt();
+  tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt();
+  tRFCab = tCK * mMemspecJson["memtimingspec"].toObject()["RFCab"].toInt();
+  tRFCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RFCpb"].toInt();
+  tESCKE = tCK * mMemspecJson["memtimingspec"].toObject()["ESCKE"].toInt();
+  tSR = tCK * mMemspecJson["memtimingspec"].toObject()["SR"].toInt();
+  tXSR = tCK * mMemspecJson["memtimingspec"].toObject()["XSR"].toInt();
+  tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt();
+  tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt();
+  tCMDCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CMDCKE"].toInt();
+  tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt();
+
+  tBURST = (uint) (burstLength / (float) dataRate) * tCK;
+  tRDWR = tRL + tDQSCK + tBURST - tWL + tWPRE + tRPST;
+  tRDWR_R = tRL + tBURST + tRTRS - tWL;
+  tWRRD = tWL + tCK + tBURST + tWTR;
+  tWRRD_R = tWL + tBURST + tRTRS - tRL;
+  tRDPRE = tRTP + tBURST - 6 * tCK;
+  tRDAACT = tRTP + tRPpb + tBURST - 8 * tCK;
+  tWRPRE = 2 * tCK + tWL + tCK + tBURST + tWR;
+  tWRAACT = tWL + tBURST + tWR + tCK + tRPpb;
+  tACTPDEN = 3 * tCK + tCMDCKE;
+  tPRPDEN = tCK + tCMDCKE;
+  tRDPDEN = 3 * tCK + tRL + tDQSCK + tBURST + tRPST;
+  tWRPDEN = 3 * tCK + tWL + (ceil((uint) (tDQSS / (float) tCK)) + ceil((uint) (tDQS2DQ / (float) tCK))) * tCK + tBURST + tWR;
+  tWRAPDEN = 3 * tCK + tWL + (ceil((uint) (tDQSS / (float) tCK)) + ceil((uint) (tDQS2DQ / (float) tCK))) * tCK + tBURST + tWR + 2 * tCK;
+  tREFPDEN = tCK + tCMDCKE;
+  tSREFPDEN = tCK + tESCKE;
+
+  mPools.insert({
+    "CMD_BUS", {
+      1, {
+        {"ACT", 4 * tCK},
+        {"RD", 4 * tCK},
+        {"WR", 4 * tCK},
+        {"RDA", 4 * tCK},
+        {"WRA", 4 * tCK},
+        {"PREPB", 2 * tCK},
+        {"PREAB", 2 * tCK},
+        {"REFAB", 2 * tCK},
+        {"SREFEN", 2 * tCK},
+        {"SREFEX", 2 * tCK},
+        {"REFPB", 2 * tCK},
+      }
+    }
+  });
+
+  mPools.insert({
+    "NAW", {
+      4, {
+        {"ACT", tFAW},
+        {"REFPB", tFAW},
+      }
+    }
+  });
+
+}
+
+const std::vector<QString> TimeDependenciesInfoLPDDR4::getPossiblePhases() {
+  return {
+    "ACT",
+    "RD",
+    "WR",
+    "PREPB",
+    "RDA",
+    "WRA",
+    "REFPB",
+    "REFAB",
+    "PREAB",
+    "PDEP",
+    "PDXP",
+    "SREFEN",
+    "SREFEX",
+    "PDEA",
+    "PDXA",
+    "SRPDEN",
+    "SRPDEX",
+  };
+}
+
+DependencyMap TimeDependenciesInfoLPDDR4::mSpecializedGetDependencies() const {
+  DependencyMap dmap;
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("ACT"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCpb, "ACT", DependencyType::IntraBank, "tRCpb"},
+        {tRRD, "ACT", DependencyType::IntraRank, "tRRD"},
+        {tRDAACT, "RDA", DependencyType::IntraBank, "tRDAACT"},
+        {tWRAACT, "WRA", DependencyType::IntraBank, "tWRAACT"},
+        {tRPpb - 2 * tCK, "PREPB", DependencyType::IntraBank, "tRPpb - 2 * tCK"},
+        {tRPab - 2 * tCK, "PREAB", DependencyType::IntraRank, "tRPab - 2 * tCK"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFCab - 2 * tCK, "REFAB", DependencyType::IntraRank, "tRFCab - 2 * tCK"},
+        {tRFCpb - 2 * tCK, "REFPB", DependencyType::IntraBank, "tRFCpb - 2 * tCK"},
+        {tRRD - 2 * tCK, "REFPB", DependencyType::IntraRank, "tRRD - 2 * tCK"},
+        {tXSR - 2 * tCK, "SREFEX", DependencyType::IntraRank, "tXSR - 2 * tCK"},
+        {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+        {tFAW, "NAW", DependencyType::IntraRank, "tFAW"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RD"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
+        {tCCD, "RD", DependencyType::IntraBank, "tCCD"}, //
+        {tCCD, "RD", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD, "RDA", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tWRRD, "WR", DependencyType::IntraBank, "tWRRD"},
+        {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"},
+        {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
+        {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"},
+        {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WR"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
+        {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"}, //
+        {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
+        {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
+        {tCCD, "WR", DependencyType::IntraBank, "tCCD"},
+        {tCCD, "WR", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD, "WRA", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREPB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS + 2 * tCK, "ACT", DependencyType::IntraBank, "tRAS + 2 * tCK"},
+        {tRDPRE, "RD", DependencyType::IntraBank, "tRDPRE"},
+        {tWRPRE, "WR", DependencyType::IntraBank, "tWRPRE"},
+        {tPPD, "PREPB", DependencyType::IntraRank, "tPPD"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RDA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
+        {tCCD, "RD", DependencyType::IntraBank, "tCCD"},
+        {tCCD, "RD", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "RD", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD, "RDA", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "RDA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {max({tWRRD, tWRPRE - tRDPRE}), "WR", DependencyType::IntraBank, "max(tWRRD, tWRPRE - tRDPRE)"},
+        {tWRRD, "WR", DependencyType::IntraRank, "tWRRD"},
+        {tWRRD_R, "WR", DependencyType::InterRank, "tWRRD_R"},
+        {tWRRD, "WRA", DependencyType::IntraRank, "tWRRD"},
+        {tWRRD_R, "WRA", DependencyType::InterRank, "tWRRD_R"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WRA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD, "ACT", DependencyType::IntraBank, "tRCD"},
+        {tRDWR, "RD", DependencyType::IntraBank, "tRDWR"},
+        {tRDWR, "RD", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RD", DependencyType::InterRank, "tRDWR_R"},
+        {tRDWR, "RDA", DependencyType::IntraRank, "tRDWR"},
+        {tRDWR_R, "RDA", DependencyType::InterRank, "tRDWR_R"},
+        {tCCD, "WR", DependencyType::IntraBank, "tCCD"},
+        {tCCD, "WR", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "WR", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tCCD, "WRA", DependencyType::IntraRank, "tCCD"},
+        {tBURST + tRTRS, "WRA", DependencyType::InterRank, "tBURST + tRTRS"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {4 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("REFPB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCpb + 2 * tCK, "ACT", DependencyType::IntraBank, "tRCpb + 2 * tCK"},
+        {tRRD + 2 * tCK, "ACT", DependencyType::IntraRank, "tRRD + 2 * tCK"},
+        {tRDPRE + tRPpb, "RDA", DependencyType::IntraBank, "tRDPRE + tRPpb"},
+        {tWRPRE + tRPpb, "WRA", DependencyType::IntraBank, "tWRPRE + tRPpb"},
+        {tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"},
+        {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"},
+        {tRFCpb, "REFPB", DependencyType::IntraBank, "tRFCpb"}, //
+        {tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"},
+        {tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"},
+        {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+        {tFAW, "NAW", DependencyType::IntraRank, "tFAW"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("REFAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCpb + 2 * tCK, "ACT", DependencyType::IntraRank, "tRCpb + 2 * tCK"},
+        {tRDPRE + tRPpb, "RDA", DependencyType::IntraRank, "tRDPRE + tRPpb"},
+        {tWRPRE + tRPpb, "WRA", DependencyType::IntraRank, "tWRPRE + tRPpb"},
+        {tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"},
+        {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"},
+        {tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"},
+        {tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"},
+        {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS + 2 * tCK, "ACT", DependencyType::IntraRank, "tRAS + 2 * tCK"},
+        {tRDPRE, "RD", DependencyType::IntraRank, "tRDPRE"},
+        {tRDPRE, "RDA", DependencyType::IntraRank, "tRDPRE"},
+        {tWRPRE, "WR", DependencyType::IntraRank, "tWRPRE"},
+        {tWRPRE, "WRA", DependencyType::IntraRank, "tWRPRE"},
+        {tPPD, "PREPB", DependencyType::IntraRank, "tPPD"},
+        {tXP, "PDXA", DependencyType::IntraRank, "tXP"},
+        {tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"},
+        {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDEP"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"},
+        {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"},
+        {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
+        {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
+        {tPRPDEN, "PREAB", DependencyType::IntraRank, "tPRPDEN"},
+        {tCKE, "PDXP", DependencyType::IntraRank, "tCKE"},
+        {tREFPDEN, "REFAB", DependencyType::IntraRank, "tREFPDEN"},
+        {tREFPDEN, "REFPB", DependencyType::IntraRank, "tREFPDEN"},
+        {tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDXP"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tCKE, "PDEP", DependencyType::IntraRank, "tCKE"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("SREFEN"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCpb + 2 * tCK, "ACT", DependencyType::IntraRank, "tRCpb + 2 * tCK"},
+        {max({tRDPDEN, tRDPRE + tRPpb}), "RDA", DependencyType::IntraRank, "max(tRDPDEN, tRDPRE + tRPpb)"},
+        {max({tWRAPDEN, tWRPRE + tRPpb}), "WRA", DependencyType::IntraRank, "max(tWRAPDEN, tWRPRE + tRPpb)"},
+        {tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"},
+        {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
+        {tXP, "PDXP", DependencyType::IntraRank, "tXP"},
+        {tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"},
+        {tRFCpb, "REFPB", DependencyType::IntraRank, "tRFCpb"},
+        {tXSR, "SREFEX", DependencyType::IntraRank, "tXSR"},
+        {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("SREFEX"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tSR, "SREFEN", DependencyType::IntraRank, "tSR"},
+        {tXP, "SRPDEX", DependencyType::IntraRank, "tXP"}, //
+        {2 * tCK, "CMD_BUS", DependencyType::InterRank, "CommandBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDEA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tACTPDEN, "ACT", DependencyType::IntraRank, "tACTPDEN"},
+        {tRDPDEN, "RD", DependencyType::IntraRank, "tRDPDEN"},
+        {tRDPDEN, "RDA", DependencyType::IntraRank, "tRDPDEN"},
+        {tWRPDEN, "WR", DependencyType::IntraRank, "tWRPDEN"},
+        {tWRAPDEN, "WRA", DependencyType::IntraRank, "tWRAPDEN"},
+        {tPRPDEN, "PREPB", DependencyType::IntraRank, "tPRPDEN"},
+        {tCKE, "PDXA", DependencyType::IntraRank, "tCKE"},
+        {tREFPDEN, "REFPB", DependencyType::IntraRank, "tREFPDEN"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PDXA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tCKE, "PDEA", DependencyType::IntraRank, "tCKE"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("SRPDEN"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tSREFPDEN, "SREFEN", DependencyType::IntraRank, "tSREFPDEN"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("SRPDEX"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tCKE, "SRPDEN", DependencyType::IntraRank, "tCKE"},
+      }
+    )
+  );
+
+  return dmap;
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR4.h

@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "../dramtimedependenciesbase.h"
+
+class TimeDependenciesInfoLPDDR4 final : public DRAMTimeDependenciesBase {
+  public:
+    TimeDependenciesInfoLPDDR4(const QJsonObject& memspec, const uint clk);
+
+    static const std::vector<QString> getPossiblePhases();
+
+  protected:
+    void mInitializeValues() override;
+    DependencyMap mSpecializedGetDependencies() const override;
+
+  protected:
+    uint burstLength;
+    uint dataRate;
+
+    uint tRRD;
+    uint tRCD;
+    uint tRAS;
+    uint tFAW;
+    uint tRPpb;
+    uint tRPab;
+    uint tRCpb;
+    uint tRCab;
+    uint tCCD;
+    uint tRTP;
+    uint tWR;
+    uint tWTR;
+    uint tPPD;
+    uint tWPRE;
+    uint tRPST;
+    uint tDQSCK;
+    uint tDQSS;
+    uint tDQS2DQ;
+    uint tRL;
+    uint tWL;
+    uint tRFCab;
+    uint tRFCpb;
+    uint tESCKE;
+    uint tSR;
+    uint tXSR;
+    uint tXP;
+    uint tCKE;
+    uint tCMDCKE;
+    uint tRTRS;
+
+    uint tBURST;
+    uint tRDWR;
+    uint tRDWR_R;
+    uint tWRRD;
+    uint tWRRD_R;
+    uint tRDPRE;
+    uint tRDAACT;
+    uint tWRPRE;
+    uint tWRAACT;
+    uint tACTPDEN;
+    uint tPRPDEN;
+    uint tRDPDEN;
+    uint tWRPDEN;
+    uint tWRAPDEN;
+    uint tREFPDEN;
+    uint tSREFPDEN;
+
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.cpp

@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "TimeDependenciesInfoLPDDR5.h"
+
+using namespace std;
+
+TimeDependenciesInfoLPDDR5::TimeDependenciesInfoLPDDR5(const QJsonObject& memspec, const uint tCK) : DRAMTimeDependenciesBase(memspec, tCK) {
+  mInitializeValues();
+}
+
+void TimeDependenciesInfoLPDDR5::mInitializeValues() {
+  burstLength = mMemspecJson["memarchitecturespec"].toObject()["burstLength"].toInt();
+  dataRate = mMemspecJson["memarchitecturespec"].toObject()["dataRate"].toInt();
+  per2BankOffset = mMemspecJson["memarchitecturespec"].toObject()["per2BankOffset"].toInt();
+
+  tRCD = tCK * mMemspecJson["memtimingspec"].toObject()["RCD"].toInt();
+  tRPpb = tCK * mMemspecJson["memtimingspec"].toObject()["RPpb"].toInt();
+  tRPab = tCK * mMemspecJson["memtimingspec"].toObject()["RPab"].toInt();
+  tRAS = tCK * mMemspecJson["memtimingspec"].toObject()["RAS"].toInt();
+  tRCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RCpb"].toInt();
+  tRCab = tCK * mMemspecJson["memtimingspec"].toObject()["RCab"].toInt();
+  tCL = tCK * mMemspecJson["memtimingspec"].toObject()["CL"].toInt();
+  tCWL = tCK * mMemspecJson["memtimingspec"].toObject()["CWL"].toInt();
+  tAL = tCK * mMemspecJson["memtimingspec"].toObject()["AL"].toInt();
+  tRL = tCK * mMemspecJson["memtimingspec"].toObject()["RL"].toInt();
+  tRPRE = tCK * mMemspecJson["memtimingspec"].toObject()["RPRE"].toInt();
+  tWPRE = tCK * mMemspecJson["memtimingspec"].toObject()["WPRE"].toInt();
+  tWL = tCK * mMemspecJson["memtimingspec"].toObject()["WL"].toInt();
+  tCCD_S = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_S"].toInt();
+  tCCD_L = tCK * mMemspecJson["memtimingspec"].toObject()["CCD_L"].toInt();
+  tRRD = tCK * mMemspecJson["memtimingspec"].toObject()["RRD"].toInt();
+  tFAW = tCK * mMemspecJson["memtimingspec"].toObject()["FAW"].toInt();
+  tWTR_S = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_S"].toInt();
+  tWTR_L = tCK * mMemspecJson["memtimingspec"].toObject()["WTR_L"].toInt();
+  tRTP = tCK * mMemspecJson["memtimingspec"].toObject()["RTP"].toInt();
+  tWR = tCK * mMemspecJson["memtimingspec"].toObject()["WR"].toInt();
+  tRFCab = tCK * mMemspecJson["memtimingspec"].toObject()["RFCab"].toInt();
+  tRFCpb = tCK * mMemspecJson["memtimingspec"].toObject()["RFCpb"].toInt();
+  tXS = tCK * mMemspecJson["memtimingspec"].toObject()["XS"].toInt();
+  tXSDLL = tCK * mMemspecJson["memtimingspec"].toObject()["XSDLL"].toInt();
+  tXP = tCK * mMemspecJson["memtimingspec"].toObject()["XP"].toInt();
+  tCKE = tCK * mMemspecJson["memtimingspec"].toObject()["CKE"].toInt();
+  tCKESR = tCK * mMemspecJson["memtimingspec"].toObject()["CKESR"].toInt();
+  tPD = tCK * mMemspecJson["memtimingspec"].toObject()["PD"].toInt();
+  tPRPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["PRPDEN"].toInt();
+  tREFPDEN = tCK * mMemspecJson["memtimingspec"].toObject()["REFPDEN"].toInt();
+  tRTRS = tCK * mMemspecJson["memtimingspec"].toObject()["RTRS"].toInt();
+  tRBTP = tCK * mMemspecJson["memtimingspec"].toObject()["RBTP"].toInt();
+  BL_n_min_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_min_16"].toInt();
+  BL_n_min_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_min_32"].toInt();
+  BL_n_max_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_max_16"].toInt();
+  BL_n_max_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_max_32"].toInt();
+  BL_n_S_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_S_16"].toInt();
+  BL_n_S_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_S_32"].toInt();
+  BL_n_L_16 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_L_16"].toInt();
+  BL_n_L_32 = tCK * mMemspecJson["memtimingspec"].toObject()["BL_n_L_32"].toInt();
+  tWCK2DQO = tCK * mMemspecJson["memtimingspec"].toObject()["WCK2DQO"].toInt();
+  tPPD = tCK * mMemspecJson["memtimingspec"].toObject()["PPD"].toInt();
+  tpbR2act = tCK * mMemspecJson["memtimingspec"].toObject()["pbR2act"].toInt();
+  tpbR2pbR = tCK * mMemspecJson["memtimingspec"].toObject()["pbR2pbR"].toInt();
+
+  tBURST16 = (uint) (16 / (float) dataRate) * tCK;
+  tBURST32 = (uint) (32 / (float) dataRate) * tCK;
+
+  mPools.insert({
+    "CMD_BUS", {
+      1, {
+        {"ACT", 2 * tCK},
+        {"RD", tCK},
+        {"WR", tCK},
+        {"RDA", tCK},
+        {"WRA", tCK},
+        {"PREPB", tCK},
+        {"PREAB", tCK},
+        {"REFAB", tCK},
+        {"REFPB", tCK},
+        {"REFP2B", tCK},
+      }
+    }
+  });
+
+  mPools.insert({
+    "NAW", {
+      4, {
+        {"ACT", tFAW},
+        {"REFPB", tFAW},
+        {"REFP2B", tFAW},
+      }
+    }
+  });
+
+}
+
+const std::vector<QString> TimeDependenciesInfoLPDDR5::getPossiblePhases() {
+  return {
+    "ACT",
+    "RD",
+    "WR",
+    "PREPB",
+    "RDA",
+    "WRA",
+    "REFPB",
+    "REFP2B",
+    "REFAB",
+    "PREAB",
+  };
+}
+
+DependencyMap TimeDependenciesInfoLPDDR5::mSpecializedGetDependencies() const {
+  DependencyMap dmap;
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("ACT"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCpb, "ACT", DependencyType::IntraBank, "tRCpb"},
+        {tRRD, "ACT", DependencyType::IntraRank, "tRRD"},
+        {BL_n_min_16 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb - tCK"},
+        {BL_n_min_32 + tRBTP + tRPpb - tCK, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb - tCK"},
+        {tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb - tCK"},
+        {tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb - tCK"},
+        {tRPpb - tCK, "PREPB", DependencyType::IntraBank, "tRPpb - tCK"},
+        {tRPab - tCK, "PREAB", DependencyType::IntraRank, "tRPab - tCK"},
+        {tRFCab - tCK, "REFAB", DependencyType::IntraRank, "tRFCab - tCK"},
+        {tpbR2act - tCK, "REFPB", DependencyType::IntraRank, "tpbR2act - tCK"},
+        {tpbR2act - tCK, "REFP2B", DependencyType::IntraRank, "tpbR2act - tCK"},
+        {tRFCpb - tCK, "REFPB", DependencyType::IntraBank, "tRFCpb - tCK"},
+        {tRFCpb - tCK, "REFP2B", DependencyType::IntraBank, "tRFCpb - tCK"},
+        {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
+        {0, "NAW", DependencyType::IntraRank, "tFAW"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RD"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
+        {BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16"},
+        {BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32"},
+        {BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16"},
+        {BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32"},
+        {tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS"},
+        {tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS"},
+        {BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16"},
+        {BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32"},
+        {BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16"},
+        {BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32"},
+        {tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS"},
+        {tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS"},
+        {tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
+        {tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
+        {tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
+        {tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
+        {tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
+        {tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
+        {tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
+        {tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
+        {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WR"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
+        {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
+        {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
+        {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
+        {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
+        {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
+        {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
+        {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
+        {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
+        {BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16"},
+        {BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32"},
+        {BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16"},
+        {BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32"},
+        {tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS"},
+        {tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS"},
+        {BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16"},
+        {BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32"},
+        {BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16"},
+        {BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32"},
+        {tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS"},
+        {tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS"},
+        {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREPB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS + tCK, "ACT", DependencyType::IntraBank, "tRAS + tCK"},
+        {BL_n_min_16 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_16 + tRBTP"},
+        {BL_n_min_32 + tRBTP, "RD", DependencyType::IntraBank, "BL_n_min_32 + tRBTP"},
+        {tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR"},
+        {tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR"},
+        {tPPD, "PREPB", DependencyType::IntraRank, "tPPD"},
+        {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("RDA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
+        {BL_n_L_16, "RD", DependencyType::IntraBankGroup, "BL_n_L_16"},
+        {BL_n_L_32, "RD", DependencyType::IntraBankGroup, "BL_n_L_32"},
+        {BL_n_S_16, "RD", DependencyType::IntraRank, "BL_n_S_16"},
+        {BL_n_S_32, "RD", DependencyType::IntraRank, "BL_n_S_32"},
+        {tBURST16 + tRTRS, "RD", DependencyType::InterRank, "tBURST16 + tRTRS"},
+        {tBURST32 + tRTRS, "RD", DependencyType::InterRank, "tBURST32 + tRTRS"},
+        {BL_n_L_16, "RDA", DependencyType::IntraBankGroup, "BL_n_L_16"},
+        {BL_n_L_32, "RDA", DependencyType::IntraBankGroup, "BL_n_L_32"},
+        {BL_n_S_16, "RDA", DependencyType::IntraRank, "BL_n_S_16"},
+        {BL_n_S_32, "RDA", DependencyType::IntraRank, "BL_n_S_32"},
+        {tBURST16 + tRTRS, "RDA", DependencyType::InterRank, "tBURST16 + tRTRS"},
+        {tBURST32 + tRTRS, "RDA", DependencyType::InterRank, "tBURST32 + tRTRS"},
+        {tWL + BL_n_max_16 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
+        {tWL + BL_n_max_32 + tWTR_L, "WR", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
+        {tWL + BL_n_min_16 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
+        {tWL + BL_n_min_32 + tWTR_S, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
+        {tWL + BL_n_max_16 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_16 + tWTR_L"},
+        {tWL + BL_n_max_32 + tWTR_L, "WRA", DependencyType::IntraBankGroup, "tWL + BL_n_max_32 + tWTR_L"},
+        {tWL + BL_n_min_16 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tWTR_S"},
+        {tWL + BL_n_min_32 + tWTR_S, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tWTR_S"},
+        {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("WRA"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCD + tCK, "ACT", DependencyType::IntraBank, "tRCD + tCK"},
+        {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
+        {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
+        {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
+        {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RD", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
+        {tRL + BL_n_max_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_16 + tWCK2DQO - tWL"},
+        {tRL + BL_n_max_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraBankGroup, "tRL + BL_n_max_32 + tWCK2DQO - tWL"},
+        {tRL + BL_n_min_16 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_16 + tWCK2DQO - tWL"},
+        {tRL + BL_n_min_32 + tWCK2DQO - tWL, "RDA", DependencyType::IntraRank, "tRL + BL_n_min_32 + tWCK2DQO - tWL"},
+        {BL_n_L_16, "WR", DependencyType::IntraBankGroup, "BL_n_L_16"},
+        {BL_n_L_32, "WR", DependencyType::IntraBankGroup, "BL_n_L_32"},
+        {BL_n_S_16, "WR", DependencyType::IntraRank, "BL_n_S_16"},
+        {BL_n_S_32, "WR", DependencyType::IntraRank, "BL_n_S_32"},
+        {tBURST16 + tRTRS, "WR", DependencyType::InterRank, "tBURST16 + tRTRS"},
+        {tBURST32 + tRTRS, "WR", DependencyType::InterRank, "tBURST32 + tRTRS"},
+        {BL_n_L_16, "WRA", DependencyType::IntraBankGroup, "BL_n_L_16"},
+        {BL_n_L_32, "WRA", DependencyType::IntraBankGroup, "BL_n_L_32"},
+        {BL_n_S_16, "WRA", DependencyType::IntraRank, "BL_n_S_16"},
+        {BL_n_S_32, "WRA", DependencyType::IntraRank, "BL_n_S_32"},
+        {tBURST16 + tRTRS, "WRA", DependencyType::InterRank, "tBURST16 + tRTRS"},
+        {tBURST32 + tRTRS, "WRA", DependencyType::InterRank, "tBURST32 + tRTRS"},
+        {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("REFAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCpb + tCK, "ACT", DependencyType::IntraRank, "tRCpb + tCK"},
+        {BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP + tRPpb"},
+        {BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP + tRPpb"},
+        {tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"},
+        {tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"},
+        {tRPpb, "PREPB", DependencyType::IntraRank, "tRPpb"},
+        {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
+        {tRFCab, "REFAB", DependencyType::IntraRank, "tRFCab"},
+        {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("PREAB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRAS + tCK, "ACT", DependencyType::IntraRank, "tRAS + tCK"},
+        {BL_n_min_16 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_16 + tRBTP"},
+        {BL_n_min_32 + tRBTP, "RD", DependencyType::IntraRank, "BL_n_min_32 + tRBTP"},
+        {BL_n_min_16 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_16 + tRBTP"},
+        {BL_n_min_32 + tRBTP, "RDA", DependencyType::IntraRank, "BL_n_min_32 + tRBTP"},
+        {tWL + BL_n_min_16 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR"},
+        {tWL + BL_n_min_32 + tCK + tWR, "WR", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR"},
+        {tWL + BL_n_min_16 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_16 + tCK + tWR"},
+        {tWL + BL_n_min_32 + tCK + tWR, "WRA", DependencyType::IntraRank, "tWL + BL_n_min_32 + tCK + tWR"},
+        {tPPD, "PREPB", DependencyType::IntraRank, "tPPD"},
+        {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("REFPB"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"},
+        {tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"},
+        {BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb"},
+        {BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb"},
+        {tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"},
+        {tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"},
+        {tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"},
+        {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
+        {tRFCpb, "REFPB", DependencyType::IntraBank, "tRFCpb"},
+        {tpbR2pbR, "REFPB", DependencyType::IntraRank, "tpbR2pbR"},
+        {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
+        {0, "NAW", DependencyType::IntraRank, "tFAW"},
+      }
+    )
+  );
+
+  dmap.emplace(
+    piecewise_construct,
+    forward_as_tuple("REFP2B"),
+    forward_as_tuple(
+      initializer_list<TimeDependency>{
+        {tRCpb + tCK, "ACT", DependencyType::IntraBank, "tRCpb + tCK"},
+        {tRRD + tCK, "ACT", DependencyType::IntraRank, "tRRD + tCK"},
+        {BL_n_min_16 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_16 + tRBTP + tRPpb"},
+        {BL_n_min_32 + tRBTP + tRPpb, "RDA", DependencyType::IntraBank, "BL_n_min_32 + tRBTP + tRPpb"},
+        {tWL + BL_n_min_16 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_16 + tCK + tWR + tRPpb"},
+        {tWL + BL_n_min_32 + tCK + tWR + tRPpb, "WRA", DependencyType::IntraBank, "tWL + BL_n_min_32 + tCK + tWR + tRPpb"},
+        {tRPpb, "PREPB", DependencyType::IntraBank, "tRPpb"},
+        {tRPab, "PREAB", DependencyType::IntraRank, "tRPab"},
+        {tRFCpb, "REFP2B", DependencyType::IntraBank, "tRFCpb"},
+        {tpbR2pbR, "REFP2B", DependencyType::IntraRank, "tpbR2pbR"},
+        {0, "CMD_BUS", DependencyType::InterRank, "CMDBus"},
+        {0, "NAW", DependencyType::IntraRank, "tFAW"},
+      }
+    )
+  );
+
+  return dmap;
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/deviceDependencies/specialized/TimeDependenciesInfoLPDDR5.h

@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include "../dramtimedependenciesbase.h"
+
+class TimeDependenciesInfoLPDDR5 final : public DRAMTimeDependenciesBase {
+  public:
+    TimeDependenciesInfoLPDDR5(const QJsonObject& memspec, const uint clk);
+
+    static const std::vector<QString> getPossiblePhases();
+
+    uint getPer2BankOffset() { return per2BankOffset; }
+
+  protected:
+    void mInitializeValues() override;
+    DependencyMap mSpecializedGetDependencies() const override;
+
+  protected:
+    uint burstLength;
+    uint dataRate;
+    uint per2BankOffset;
+  
+    uint tRCD;
+    uint tRPpb;
+    uint tRPab;
+    uint tRAS;
+    uint tRCpb;
+    uint tRCab;
+    uint tCL;
+    uint tCWL;
+    uint tAL;
+    uint tRL;
+    uint tRPRE;
+    uint tWPRE;
+    uint tWL;
+    uint tCCD_S;
+    uint tCCD_L;
+    uint tRRD;
+    uint tFAW;
+    uint tWTR_S;
+    uint tWTR_L;
+    uint tRTP;
+    uint tWR;
+    uint tRFCab;
+    uint tRFCpb;
+    uint tXS;
+    uint tXSDLL;
+    uint tXP;
+    uint tCKE;
+    uint tCKESR;
+    uint tPD;
+    uint tPRPDEN;
+    uint tREFPDEN;
+    uint tRTRS;
+    uint tRBTP;
+    uint BL_n_min_16;
+    uint BL_n_min_32;
+    uint BL_n_max_16;
+    uint BL_n_max_32;
+    uint BL_n_S_16;
+    uint BL_n_S_32;
+    uint BL_n_L_16;
+    uint BL_n_L_32;
+    uint tWCK2DQO;
+    uint tPPD;
+
+    uint tpbR2act;
+    uint tpbR2pbR;
+
+    uint tBURST16;
+    uint tBURST32;
+    uint tRDWR;
+    uint tRDWR_R;
+    uint tWRRD_S;
+    uint tWRRD_L;
+    uint tWRRD_R;
+    uint tRDAACT;
+    uint tWRPRE;
+    uint tWRAACT;
+    uint tRDPDEN;
+    uint tWRPDEN;
+    uint tWRAPDEN;
+
+};

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.cpp

@@ -0,0 +1,341 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#include "phasedependenciestracker.h"
+
+#include <chrono>
+#include <iostream>
+
+void 
+PhaseDependenciesTracker::calculateDependencies(TraceDB& tdb, std::vector<QString>& commands) {
+    using std::chrono::high_resolution_clock;
+    using std::chrono::duration_cast;
+    using std::chrono::duration;
+    using std::chrono::microseconds;
+
+    auto deviceInstantiationTimeStart = high_resolution_clock::now();
+        auto deviceConfig = ConfigurationFactory::make(tdb);
+    auto deviceInstantiationTimeEnd = high_resolution_clock::now();
+    auto deviceInstantiationTimeDuration = duration_cast<microseconds>(deviceInstantiationTimeEnd - deviceInstantiationTimeStart);
+
+    mBeginTransaction(tdb);
+
+    mDropTable(tdb);
+
+    if (commands.size() > 0) {
+        auto phasesLoadingTimeStart = high_resolution_clock::now();
+            auto& phases = mGetFilteredPhases(deviceConfig, tdb, commands);
+        auto phasesLoadingTimeEnd = high_resolution_clock::now();
+        auto phasesLoadingTimeDuration = duration_cast<microseconds>(phasesLoadingTimeEnd - phasesLoadingTimeStart);
+
+        if (phases.size() != 0) {
+            auto dependenciesCalcTimeStart = high_resolution_clock::now();
+                auto& entries = mCalculateDependencies(deviceConfig, phases, commands);
+            auto dependenciesCalcTimeEnd = high_resolution_clock::now();
+            auto dependenciesCalcTimeDuration = duration_cast<microseconds>(dependenciesCalcTimeEnd - dependenciesCalcTimeStart);
+
+            if (entries.size() > 0) {
+                mCreateTable(tdb);
+            }
+
+            auto tableInsertionTimeStart = high_resolution_clock::now();
+                mInsertIntoTable(tdb, entries);
+            auto tableInsertionTimeEnd = high_resolution_clock::now();
+            auto tableInsertionTimeDuration = duration_cast<microseconds>(tableInsertionTimeEnd - tableInsertionTimeStart);
+
+            auto totalTime = deviceInstantiationTimeDuration + phasesLoadingTimeDuration + dependenciesCalcTimeDuration + tableInsertionTimeDuration;
+
+
+        std::cout << "PhaseDependenciesTracker times (us):" << std::endl
+                  << "\tDevice instantiation: " << deviceInstantiationTimeDuration.count() << std::endl
+                  << "\tPhase loading: " << phasesLoadingTimeDuration.count() << std::endl
+                  << "\tDependencies calculation: " << dependenciesCalcTimeDuration.count() << std::endl
+                  << "\tDB table population: " << tableInsertionTimeDuration.count() << std::endl
+                  << " - Total time: " << totalTime.count() << std::endl;
+
+        } else {
+            // TODO - not sure if necessary. Still, a possibility
+            // mRollbackChanges(tdb);
+            // return;
+        }
+
+    }
+
+    mCommitTransaction(tdb);
+}
+
+void PhaseDependenciesTracker::mDropTable(TraceDB& tdb) {
+    QString command = "DROP TABLE IF EXISTS DirectDependencies; ";
+    
+    auto query = mExecuteQuery(tdb, command);
+    query.finish();
+}
+
+void PhaseDependenciesTracker::mCreateTable(TraceDB& tdb) {
+    QString command = "CREATE TABLE DirectDependencies( DelayedPhaseID INT, DelayedPhaseName, DependencyType, TimeDependency, DependencyPhaseID INT, DependencyPhaseName ); ";
+    
+    auto query = mExecuteQuery(tdb, command);
+    query.finish();
+}
+
+void PhaseDependenciesTracker::mInsertIntoTable(TraceDB& tdb, const std::vector<DBDependencyEntry>& entries) {
+    static const size_t bulkInsertionSize = 30;
+    
+    auto numberOfEntries = entries.size();
+
+    QString command;
+    size_t counter = 0;
+    for (const auto& entry : entries) {
+        if (counter == 0) {
+            // Reset command string and add first entry
+            command = "INSERT INTO 'DirectDependencies' ('DelayedPhaseID', 'DelayedPhaseName', 'DependencyType', 'TimeDependency', 'DependencyPhaseID', 'DependencyPhaseName') ";
+            mAddFirstEntryCommandString(command, entry);
+            
+            counter++;
+
+        } else if (counter == bulkInsertionSize-1) {
+            // Write last entry and submit
+            mAddEntryCommandString(command, entry);
+
+            auto query = mExecuteQuery(tdb, command);
+            query.finish();
+
+            counter = 0;
+
+        } else {
+            // Write entry
+            mAddEntryCommandString(command, entry);
+
+            counter++;
+
+
+        }
+
+    }
+
+    if (counter != 0) {
+        auto query = mExecuteQuery(tdb, command);
+        query.finish();
+    }
+
+}
+
+const std::vector<std::shared_ptr<DBPhaseEntryBase>>
+PhaseDependenciesTracker::mGetFilteredPhases(const std::shared_ptr<ConfigurationBase> deviceConfig, TraceDB& tdb, const std::vector<QString>& commands) {
+    std::vector<std::shared_ptr<DBPhaseEntryBase>> phases;
+
+    QString queryStr = "SELECT Phases.*, Transactions.TBank, Transactions.TBankgroup, Transactions.TRank "
+            " FROM Phases "
+            " INNER JOIN Transactions "
+            " ON Phases.Transact=Transactions.ID "
+            " WHERE PhaseName IN (";
+        
+    for (const auto& cmd : commands) {
+        queryStr = queryStr + '\"' + cmd + "\",";
+    }
+    queryStr.back() = ')'; 
+    queryStr += " ORDER BY PhaseBegin; ";
+
+    auto query = mExecuteQuery(tdb, queryStr);
+
+    if (!query.next())
+        return phases;
+
+    if (!query.last()) {
+        throw sqlException( ("Query:\n " + tdb.queryToString(query) + "\n failed. Error: \n"
+                             "Could not retrieve number of rows\n").toStdString(),
+                             tdb.pathToDB.toStdString());
+    }
+
+    size_t nrows = query.at() + 1;
+
+    if (!query.first()) {
+        throw sqlException( ("Query:\n " + tdb.queryToString(query) + "\n failed. Error: \n"
+                             "Could not retrieve number of rows safely\n").toStdString(),
+                             tdb.pathToDB.toStdString());
+    }
+
+    phases.resize(nrows);
+
+    size_t rowIt = 0;
+    do {
+        // TODO factory method
+        phases[rowIt] = deviceConfig->makePhaseEntry(query);
+
+        ++rowIt;
+    } while (query.next());
+
+    if  (rowIt != nrows) {
+        throw std::runtime_error("An error occurred while fetching phases in 'PhaseDependenciesTracker::mGetFilteredPhases': expected " + std::to_string(nrows) + " rows, but found " + std::to_string(rowIt) + "\n");
+    }
+
+    query.finish();
+
+    return phases;
+}
+
+const std::vector<DBDependencyEntry>
+PhaseDependenciesTracker::mCalculateDependencies(const std::shared_ptr<ConfigurationBase> deviceConfig, const std::vector<std::shared_ptr<DBPhaseEntryBase>>& phases, std::vector<QString>& commands) {
+    std::vector<DBDependencyEntry> entries;
+    entries.reserve((size_t) (0.4 * phases.size()));
+
+    // Get dependencies for device
+    const DependencyMap deviceDependencies = deviceConfig->getDependencies(commands);
+
+    // Tries to find all timing dependencies for each phase on the trace
+    PoolControllerMap poolController = deviceConfig->getPools();
+    for (size_t i = 1; i < phases.size(); i++) {
+        // Pool dependencies variables reset
+        poolController.clear();
+
+        // Auxiliary variables
+        const auto phase = phases[i];
+        if (phase == nullptr) continue;
+        
+        // Get time dependency descriptions for the current phase
+        const auto& deps = deviceDependencies.at(phase->phaseName);
+
+        // Loop all previous phases until there cannot be any more time dependencies
+        for (int j = i-1; j >= 0; j--) {
+            // Get next phase to analyse
+            const auto& otherPhase = phases[j];
+            // Calculates the time difference in nanoseconds
+            const auto timeDiff = phase->phaseBegin - otherPhase->phaseBegin;
+            // Time difference begin greater than the maximum possible dependency time ends the internal loop
+            if (timeDiff > deps.maxTime) break;
+
+            // For each possible dependency for the current phase,
+            // checks if otherPhase would match as a dependency
+            for (const auto& dep : deps.dependencies) {
+                bool isPoolDep = dep.phaseDep.isPool();
+                if (!isPoolDep && dep.phaseDep != otherPhase->phaseName) continue;
+                
+                if (!phase->potentialDependency(dep, otherPhase)) {
+                    continue;
+                }
+
+                if (isPoolDep) {
+                    // Captures activate window and command bus dependencies
+
+                    auto busyTime = poolController.getBusyTime(dep.phaseDep, otherPhase->phaseName);
+                    if (busyTime > 0 && timeDiff <= busyTime) {
+                        if (timeDiff == busyTime) { 
+                            // Captures only the first (exactly matching time) phase in
+                            // the pool window as a dependency
+                            poolController.push(dep.phaseDep, DBDependencyEntry{
+                                phase->id,
+                                phase->phaseName.getIDStr(),
+                                PhaseDependency::dependencyTypeName(dep.depType),
+                                dep.timeDepName,
+                                otherPhase->id,
+                                otherPhase->phaseName.getIDStr()
+                            });
+                        } 
+
+                        if (timeDiff < busyTime) {
+                            poolController.increment(dep.phaseDep);
+                        }
+                    
+                    }
+
+                    continue; 
+                }
+
+                if (timeDiff == dep.timeValue) {
+                    entries.emplace_back(DBDependencyEntry{
+                        phase->id,
+                        phase->phaseName.getIDStr(),
+                        PhaseDependency::dependencyTypeName(dep.depType),
+                        dep.timeDepName,
+                        otherPhase->id,
+                        otherPhase->phaseName.getIDStr()
+                    });
+                }
+
+            }
+
+        }
+
+        poolController.merge(entries);
+
+    }
+
+    return entries;
+}
+
+QSqlQuery PhaseDependenciesTracker::mExecuteQuery(TraceDB& tdb, const QString queryStr) {
+    QSqlQuery query(tdb.database);
+    query.prepare(queryStr);
+    tdb.executeQuery(query);
+
+    return query;
+}
+
+void PhaseDependenciesTracker::mBeginTransaction(TraceDB& tdb) {
+    const QString queryStr = "BEGIN TRANSACTION;";
+    auto query = mExecuteQuery(tdb, queryStr);
+    query.finish();
+}
+
+void PhaseDependenciesTracker::mRollbackChanges(TraceDB& tdb) {
+    const QString queryStr = "ROLLBACK;";
+    auto query = mExecuteQuery(tdb, queryStr);
+    query.finish();
+}
+
+void PhaseDependenciesTracker::mCommitTransaction(TraceDB& tdb) {
+    const QString queryStr = "COMMIT;";
+    auto query = mExecuteQuery(tdb, queryStr);
+    query.finish();
+}
+
+void PhaseDependenciesTracker::mAddFirstEntryCommandString(QString& command, const DBDependencyEntry& entry) {
+    command = command + " SELECT '" + QString::number(entry.delayedPhaseID) + "' AS 'DelayedPhaseID', '"
+                      + entry.delayedPhaseName + "' AS 'DelayedPhaseName', '"
+                      + entry.dependencyType + "' AS 'DependencyType', '"
+                      + entry.timeDependency + "' AS 'TimeDependency', '"
+                      + QString::number(entry.dependencyPhaseID) + "' AS 'DependencyPhaseID', '"
+                      + entry.dependencyPhaseName + "' AS 'DependencyPhaseName' ";
+
+}
+
+void PhaseDependenciesTracker::mAddEntryCommandString(QString& command, const DBDependencyEntry& entry) {
+    command = command + " UNION ALL SELECT '" + QString::number(entry.delayedPhaseID) + "', '"
+                      + entry.delayedPhaseName + "', '"
+                      + entry.dependencyType + "', '"
+                      + entry.timeDependency + "', '"
+                      + QString::number(entry.dependencyPhaseID) + "', '"
+                      + entry.dependencyPhaseName + "' ";
+}

DRAMSys/traceAnalyzer/businessObjects/dramTimeDependencies/phasedependenciestracker.h

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2022, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Iron Prando da Silva
+ */
+
+#pragma once
+
+#include <vector>
+#include <string>
+#include <QString>
+
+#include "data/tracedb.h"
+#include "configurations/configurationfactory.h"
+#include "common/common.h"
+
+class PhaseDependenciesTracker {
+public:
+    static void calculateDependencies(TraceDB& tdb, std::vector<QString>& dependencyFilter);
+
+private:
+    static void mDropTable(TraceDB& tdb);
+    static void mCreateTable(TraceDB& tdb);
+    static void mInsertIntoTable(TraceDB& tdb, const std::vector<DBDependencyEntry>& entries);
+
+    static const std::vector<std::shared_ptr<DBPhaseEntryBase>> mGetFilteredPhases(const std::shared_ptr<ConfigurationBase>, TraceDB& tdb, const std::vector<QString>& commands);
+    static const std::vector<DBDependencyEntry> mCalculateDependencies(const std::shared_ptr<ConfigurationBase>, const std::vector<std::shared_ptr<DBPhaseEntryBase>>& phases, std::vector<QString>& commands);
+
+    static QSqlQuery mExecuteQuery(TraceDB& tdb, const QString queryStr);
+
+    PhaseDependenciesTracker() = delete;
+    ~PhaseDependenciesTracker() = delete;
+
+private:
+    static void mBeginTransaction(TraceDB& tdb);
+    static void mRollbackChanges(TraceDB& tdb);
+    static void mCommitTransaction(TraceDB& tdb); 
+
+    inline static void mAddFirstEntryCommandString(QString& command, const DBDependencyEntry& entry);
+    inline static void mAddEntryCommandString(QString& command, const DBDependencyEntry& entry);
+
+};

DRAMSys/traceAnalyzer/businessObjects/phases/phase.cpp

@@ -73,14 +73,11 @@ void Phase::draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap &
         drawPhaseSymbol(span.Begin(), span.End(), yVal, drawingProperties.drawText, getPhaseSymbol(), painter, xMap,
                         yMap, drawingProperties.textColor);
 
-        if (getGranularity() == Granularity::Bankwise)
+        DependencyOptions drawDependenciesOptions = drawingProperties.drawDependenciesOption;
+        if (drawDependenciesOptions.draw == DependencyOption::All ||
+            (drawDependenciesOptions.draw == DependencyOption::Selected && highlight))
         {
-            DependencyOptions drawDependenciesOptions = drawingProperties.drawDependenciesOption;
-            if (drawDependenciesOptions.draw == DependencyOption::All ||
-                (drawDependenciesOptions.draw == DependencyOption::Selected && highlight))
-            {
-                drawPhaseDependencies(span.Begin(), span.End(), yVal, drawingProperties, painter, xMap, yMap);
-            }
+            drawPhaseDependencies(span.Begin(), span.End(), yVal, drawingProperties, painter, xMap, yMap);
         }
     }
 
@@ -276,14 +273,17 @@ std::vector<int> RESP::getYVals(const TraceDrawingProperties &drawingProperties)
 
 QColor Phase::getColor(const TraceDrawingProperties &drawingProperties) const
 {
-    switch (drawingProperties.colorGrouping)
-    {
+    switch (drawingProperties.colorGrouping) {
     case ColorGrouping::PhaseType:
         return getPhaseColor();
+        break;
     case ColorGrouping::Thread:
         return ColorGenerator::getColor(static_cast<unsigned int>(transaction.lock()->thread));
-    case ColorGrouping::AlphaTransaction:
-        return ColorGenerator::getAlphaColored(transaction.lock()->id);
+        break;
+    case ColorGrouping::RainbowTransaction:
+        return ColorGenerator::getRainbowColored(transaction.lock()->id, ColorName::HSV15);
+
+        break;
     case ColorGrouping::Transaction:
     default:
         return ColorGenerator::getColor(transaction.lock()->id);

DRAMSys/traceAnalyzer/businessObjects/phases/phasedependency.cpp

@@ -127,3 +127,39 @@ void PhaseDependency::mDraw(QPoint &end, double depY, const TraceDrawingProperti
         drawText(painter, mTimeDependency, textPosition, alignment);
     }
 }
+
+QString PhaseDependency::dependencyTypeName(DependencyType dtype) {
+    switch(dtype) {
+        case IntraBank:
+            return "IntraBank";
+
+        case IntraBankGroup:
+            return "IntraBankGroup";
+        
+        case IntraBankInGroup:
+            return "IntraBankInGroup";
+
+        case IntraRank:
+            return "IntraRank";
+
+        case IntraLogicalRank:
+            return "IntraLogicalRank";
+
+        case IntraPhysicalRank:
+            return "IntraPhysicalRank";
+
+        case IntraDIMMRank:
+            return "IntraDIMMRank";
+
+        case InterRank:
+            return "InterRank";
+
+        case InterDIMMRank:
+            return "InterDIMMRank";
+
+        default:
+            // TODO - maybe throw?
+            return "";
+
+    }
+}

DRAMSys/traceAnalyzer/businessObjects/phases/phasedependency.h

@@ -48,9 +48,15 @@ class Phase;
 
 enum DependencyType
 {
-    Bank,
-    Rank,
-    InterRank
+    IntraBank,
+    IntraBankGroup,
+    IntraBankInGroup,
+    IntraRank,
+    IntraLogicalRank,
+    IntraPhysicalRank,
+    IntraDIMMRank,
+    InterRank,
+    InterDIMMRank,
 };
 
 class PhaseDependency
@@ -68,6 +74,8 @@ public:
     bool draw(QPoint &end, const TraceDrawingProperties &drawingProperties, QPainter *painter, const QwtScaleMap &xMap,
               const QwtScaleMap &yMap);
 
+    static QString dependencyTypeName(DependencyType);
+
 protected:
     DependencyType mType;
     QString mTimeDependency;

DRAMSys/traceAnalyzer/businessObjects/pythoncaller.cpp

@@ -52,8 +52,6 @@ PythonCaller &PythonCaller::instance()
 }
 
 PythonCaller::PythonCaller() :
-    testModuleName("tests"),
-    testFunctionName("runTests"),
     metricModuleName("metrics"),
     metricFunctionName("calculateMetrics"),
     getMetricFunctionName("getMetrics"),
@@ -73,13 +71,11 @@ PythonCaller::PythonCaller() :
     PyList_Insert(sysPath, 0, path);
     Py_DECREF(path);
 
-    qDebug() << "Test:" << testModuleName.c_str() << testFunctionName.c_str();
     qDebug() << "Metric:" << metricModuleName.c_str() << metricFunctionName.c_str();
     qDebug() << "Plot:" << plotsModuleName.c_str() << plotsFunctionName.c_str();
     qDebug() << "VcdExport:" << vcdExportModuleName.c_str() << vcdExportFunctionName.c_str();
     qDebug() << "Script: " << pathToScripts.c_str();
 
-    pRunTestsFunction = loadFunctionFromModule(testModuleName, testFunctionName);
     pCalculateMetricsFunction = loadFunctionFromModule(metricModuleName,
                                                        metricFunctionName);
     pGenPlotsFunction = loadFunctionFromModule(plotsModuleName, plotsFunctionName);
@@ -119,7 +115,6 @@ PyObject *PythonCaller::loadFunctionFromModule(std::string moduleName, std::stri
 
 PythonCaller::~PythonCaller()
 {
-    Py_DECREF(pRunTestsFunction);
     Py_DECREF(pCalculateMetricsFunction);
     Py_DECREF(pGenPlotsFunction);
     Py_DECREF(pGetMetricsFunction);
@@ -149,7 +144,8 @@ PyObject *PythonCaller::callMetricsFunction(PyObject *function, QString argument
 
     if (!pResult) {
         PyErr_Print();
-        throw std::runtime_error(std::string("Error in calling " + testFunctionName + " in module " + testModuleName));
+        throw std::runtime_error(
+            std::string("Error in calling " + metricFunctionName + " in module " + metricModuleName));
     }
 
     return pResult;
@@ -169,7 +165,7 @@ PyObject *PythonCaller::callFunctionWithStringArgument(PyObject *function,
 
     if (!pResult) {
         PyErr_Print();
-        throw std::runtime_error(std::string("Error in calling " + testFunctionName + " in module " + testModuleName));
+        throw std::runtime_error(std::string("Error in calling function with string argument"));
     }
 
     return pResult;
@@ -188,24 +184,6 @@ PyObject *PythonCaller::callFunctionWithoutArguments(PyObject *function)
     return pResult;
 }
 
-TraceTestResults PythonCaller::runTestsOnTrace(QString pathToTrace)
-{
-    TraceTestResults traceTestResult(QFileInfo(pathToTrace).baseName());
-    PyObject *pResult = callFunctionWithStringArgument(pRunTestsFunction,
-                                                       pathToTrace);
-
-    for (Py_ssize_t i = 0; i < PyList_Size(pResult); ++i) {
-        PyObject *currentTestResult = PyList_GetItem(pResult, i);
-        QString testName(PyUnicode_AsUTF8(PyTuple_GetItem(currentTestResult, 0)));
-        bool testPassed = (Py_True == PyTuple_GetItem(currentTestResult, 1));
-        QString message(PyUnicode_AsUTF8(PyTuple_GetItem(currentTestResult, 2)));
-
-        traceTestResult.addTestResult(TestResult(testName, testPassed, message));
-    }
-    Py_DECREF(pResult);
-    return traceTestResult;
-}
-
 TraceCalculatedMetrics PythonCaller::calculateMetricsOnTrace(QString pathToTrace, std::vector<long> list)
 {
     TraceCalculatedMetrics result(QFileInfo(pathToTrace).baseName());

DRAMSys/traceAnalyzer/businessObjects/pythoncaller.h

@@ -49,7 +49,6 @@
 #include <QString>
 #include <string>
 #include <map>
-#include "businessObjects/tracetestresults.h"
 #include "businessObjects/tracecalculatedmetrics.h"
 
 class PythonCaller
@@ -57,7 +56,6 @@ class PythonCaller
 public:
     static PythonCaller &instance();
 
-    TraceTestResults runTestsOnTrace(QString pathToTrace);
     TraceCalculatedMetrics calculateMetricsOnTrace(QString pathToTrace,
                                                    std::vector<long> list);
     std::vector<std::string> getMetrics(QString pathToTrace);
@@ -72,14 +70,13 @@ private:
     PythonCaller(const PythonCaller &other) = delete;
     PythonCaller &operator=(const PythonCaller &other) = delete;
 
-    PyObject *pRunTestsFunction, *pCalculateMetricsFunction, *pGetMetricsFunction;
+    PyObject *pCalculateMetricsFunction, *pGetMetricsFunction;
     PyObject *pGenPlotsFunction;
     PyObject *pVcdExportFunction = nullptr;
     PyObject *pVcdExportDependenciesFunction;
     PyObject *loadFunctionFromModule(std::string moduleName,
                                      std::string functionName);
-    std::string testModuleName, testFunctionName, metricModuleName,
-        metricFunctionName, getMetricFunctionName, pathToScripts;
+    std::string metricModuleName, metricFunctionName, getMetricFunctionName, pathToScripts;
     std::string plotsModuleName;
     std::string plotsFunctionName;
 

DRAMSys/traceAnalyzer/businessObjects/traceplotlinemodel.cpp

@@ -356,14 +356,16 @@ QString AbstractTracePlotLineModel::getLabel(LineType type)
     }
 }
 
-QString AbstractTracePlotLineModel::getLabel(unsigned int rank)
+QString AbstractTracePlotLineModel::getLabel(unsigned int rank) const
 {
-    return "RA" + QString::number(rank);
+    std::string_view rankLabel = dataBusType == DataBusType::LegacyMode ? "RA" : "PC";
+    return rankLabel.data() + QString::number(rank);
 }
 
-QString AbstractTracePlotLineModel::getLabel(unsigned int rank, unsigned int group, unsigned int bank)
+QString AbstractTracePlotLineModel::getLabel(unsigned int rank, unsigned int group, unsigned int bank) const
 {
-    return "RA" + QString::number(rank) + " BG" + QString::number(group) + " BA" + QString::number(bank);
+    std::string_view rankLabel = dataBusType == DataBusType::LegacyMode ? "RA" : "PC";
+    return rankLabel.data() + QString::number(rank) + " BG" + QString::number(group) + " BA" + QString::number(bank);
 }
 
 AbstractTracePlotLineModel::CommandBusType AbstractTracePlotLineModel::getCommandBusType(const GeneralInfo &generalInfo)

DRAMSys/traceAnalyzer/businessObjects/traceplotlinemodel.h

@@ -174,8 +174,8 @@ protected:
     std::shared_ptr<Node> createRankGroupNode(unsigned int rank) const;
 
     static QString getLabel(LineType type);
-    static QString getLabel(unsigned int rank);
-    static QString getLabel(unsigned int rank, unsigned int group, unsigned int bank);
+    QString getLabel(unsigned int rank) const;
+    QString getLabel(unsigned int rank, unsigned int group, unsigned int bank) const;
 
     static CommandBusType getCommandBusType(const GeneralInfo &generalInfo);
     static DataBusType getDataBusType(const GeneralInfo &generalInfo);

DRAMSys/traceAnalyzer/data/QueryTexts.h

@@ -62,7 +62,7 @@ struct TransactionQueryTexts {
             "WITH timespanTransactions AS (" + selectTransactionsByTimespan +
             ") SELECT * from DirectDependencies WHERE DelayedPhaseID IN ("
             " SELECT DirectDependencies.DelayedPhaseID FROM DirectDependencies JOIN timespanTransactions "
-            " ON DirectDependencies.DelayedPhaseID = timespanTransactions.PhaseID )";
+            " ON DirectDependencies.DelayedPhaseID = timespanTransactions.PhaseID ) ";
 
         // For some reason I could not use a parameter for these below
         selectDependencyTypePercentages =
@@ -78,7 +78,7 @@ struct TransactionQueryTexts {
             ") "
             "SELECT param, ROUND(ndeps*100.0 / (SELECT total FROM TotalDeps), 3) as percentage "
             "FROM DependencyTypeDeps "
-            "ORDER BY percentage DESC ";
+            "ORDER BY percentage DESC ;";
 
         selectTimeDependencyPercentages =
             "WITH TotalDeps (total) AS ( "
@@ -93,7 +93,7 @@ struct TransactionQueryTexts {
             ") "
             "SELECT param, ROUND(ndeps*100.0 / (SELECT total FROM TotalDeps), 3) as percentage "
             "FROM DependencyTypeDeps "
-            "ORDER BY percentage DESC ";
+            "ORDER BY percentage DESC ;";
 
         selectDelayedPhasePercentages =
             "WITH TotalDeps (total) AS ( "
@@ -108,7 +108,7 @@ struct TransactionQueryTexts {
             ") "
             "SELECT param, ROUND(ndeps*100.0 / (SELECT total FROM TotalDeps), 3) as percentage "
             "FROM DependencyTypeDeps "
-            "ORDER BY percentage DESC ";
+            "ORDER BY percentage DESC ;";
 
         selectDependencyPhasePercentages =
             "WITH TotalDeps (total) AS ( "
@@ -123,7 +123,7 @@ struct TransactionQueryTexts {
             ") "
             "SELECT param, ROUND(ndeps*100.0 / (SELECT total FROM TotalDeps), 3) as percentage "
             "FROM DependencyTypeDeps "
-            "ORDER BY percentage DESC ";
+            "ORDER BY percentage DESC ;";
     }
 
 };

DRAMSys/traceAnalyzer/data/tracedb.cpp

@@ -60,13 +60,16 @@ TraceDB::TraceDB(const QString& path, bool openExisting)
     if (database.isValid() && database.isOpen())
     {
         // Close the database connection if it exists and was not closed yet.
-        database.removeDatabase(path);
         database.close();
+        QSqlDatabase::removeDatabase(path);
     }
 
     database = QSqlDatabase::addDatabase("QSQLITE", path);
     database.setDatabaseName(path);
-    database.open();
+    if (!database.open())
+    {
+        qDebug() << database.lastError().text();
+    }
     if (!openExisting)
         dropAndCreateTables();
     prepareQueries();
@@ -77,28 +80,29 @@ TraceDB::TraceDB(const QString& path, bool openExisting)
 void TraceDB::prepareQueries()
 {
     selectTransactionsByTimespan = QSqlQuery(database);
-    selectTransactionsByTimespan.prepare(queryTexts.selectTransactionsByTimespan);
-    selectTransactionById = QSqlQuery(database);
+    if (!selectTransactionsByTimespan.prepare(queryTexts.selectTransactionsByTimespan))
+        qDebug() << database.lastError().text();
+
+    selectTransactionById = QSqlQuery(database);
+    if (!selectTransactionById.prepare(queryTexts.selectTransactionById))
+        qDebug() << database.lastError().text();
 
-    selectTransactionById.prepare(queryTexts.selectTransactionById);
     selectDebugMessagesByTimespan = QSqlQuery(database);
-    selectDebugMessagesByTimespan.prepare("SELECT time, Message FROM DebugMessages WHERE :begin <= time AND time <= :end ");
+    if (!selectDebugMessagesByTimespan.prepare("SELECT time, Message FROM DebugMessages WHERE :begin <= time AND time <= :end "))
+        qDebug() << database.lastError().text();
+
     selectDebugMessagesByTimespanWithLimit = QSqlQuery(database);
-    selectDebugMessagesByTimespanWithLimit.prepare("SELECT time, Message FROM DebugMessages WHERE :begin <= time AND time <= :end LIMIT :limit");
+    if (!selectDebugMessagesByTimespanWithLimit.prepare("SELECT time, Message FROM DebugMessages WHERE :begin <= time AND time <= :end LIMIT :limit"))
+        qDebug() << database.lastError().text();
 
     checkDependenciesExist = QSqlQuery(database);
-    checkDependenciesExist.prepare(queryTexts.checkDependenciesExist);
-    selectDependenciesByTimespan = QSqlQuery(database);
-    selectDependenciesByTimespan.prepare(queryTexts.selectDependenciesByTimespan);
+    if (!checkDependenciesExist.prepare(queryTexts.checkDependenciesExist))
+        qDebug() << database.lastError().text();
+
+    selectDependenciesByTimespan = QSqlQuery(database);
+    if (!selectDependenciesByTimespan.prepare(queryTexts.selectDependenciesByTimespan))
+        qDebug() << database.lastError().text();
 
-    selectDependencyTypePercentages = QSqlQuery(database);
-    selectDependencyTypePercentages.prepare(queryTexts.selectDependencyTypePercentages);
-    selectTimeDependencyPercentages = QSqlQuery(database);
-    selectTimeDependencyPercentages.prepare(queryTexts.selectTimeDependencyPercentages);
-    selectDelayedPhasePercentages = QSqlQuery(database);
-    selectDelayedPhasePercentages.prepare(queryTexts.selectDelayedPhasePercentages);
-    selectDependencyPhasePercentages = QSqlQuery(database);
-    selectDependencyPhasePercentages.prepare(queryTexts.selectDependencyPhasePercentages);
 }
 
 void TraceDB::updateComments(const std::vector<CommentModel::Comment> &comments)
@@ -126,6 +130,7 @@ void TraceDB::updateFileDescription(const QString &description)
 
 void TraceDB::refreshData()
 {
+    prepareQueries();
     generalInfo = getGeneralInfoFromDB();
 }
 
@@ -150,10 +155,12 @@ std::vector<std::shared_ptr<Transaction>> TraceDB::getTransactionsInTimespan(con
 bool TraceDB::checkDependencyTableExists()
 {
     executeQuery(checkDependenciesExist);
-    if (checkDependenciesExist.next() && checkDependenciesExist.value(0).toInt() == 1)
-        return true;
 
-    return false;
+    bool exists = checkDependenciesExist.next() && checkDependenciesExist.value(0).toInt() == 1;
+
+    checkDependenciesExist.finish();
+
+    return exists;
 }
 
 void TraceDB::updateDependenciesInTimespan(const Timespan &span)
@@ -472,29 +479,53 @@ std::vector<CommentModel::Comment> TraceDB::getDebugMessagesInTimespan(const Tim
 DependencyInfos TraceDB::getDependencyInfos(DependencyInfos::Type infoType)
 {
     DependencyInfos dummy;
-    executeQuery(checkDependenciesExist);
-    if (!checkDependenciesExist.next() || checkDependenciesExist.value(0).toInt() != 1)
+    if (!checkDependencyTableExists())
     {
         return dummy;
     }
 
     switch (infoType)
     {
-    case DependencyInfos::Type::DependencyType:
-        executeQuery(selectDependencyTypePercentages);
-        return parseDependencyInfos(selectDependencyTypePercentages, infoType);
+        case DependencyInfos::Type::DependencyType:
+        {
+            selectDependencyTypePercentages = QSqlQuery(database);
+            if (!selectDependencyTypePercentages.prepare(queryTexts.selectDependencyTypePercentages))
+                qDebug() << database.lastError().text();
 
-    case DependencyInfos::Type::TimeDependency:
-        executeQuery(selectTimeDependencyPercentages);
-        return parseDependencyInfos(selectTimeDependencyPercentages, infoType);
+            executeQuery(selectDependencyTypePercentages);
+            return parseDependencyInfos(selectDependencyTypePercentages, infoType);
+        }
 
-    case DependencyInfos::Type::DelayedPhase:
-        executeQuery(selectDelayedPhasePercentages);
-        return parseDependencyInfos(selectDelayedPhasePercentages, infoType);
+        case DependencyInfos::Type::TimeDependency:
+        {
+            selectTimeDependencyPercentages = QSqlQuery(database);
+            if (!selectTimeDependencyPercentages.prepare(queryTexts.selectTimeDependencyPercentages))
+                qDebug() << database.lastError().text();
+                
+            executeQuery(selectTimeDependencyPercentages);
+            return parseDependencyInfos(selectTimeDependencyPercentages, infoType);
+        }
+
+        case DependencyInfos::Type::DelayedPhase:
+        {
+            selectDelayedPhasePercentages = QSqlQuery(database);
+            if (!selectDelayedPhasePercentages.prepare(queryTexts.selectDelayedPhasePercentages))
+                qDebug() << database.lastError().text();
+
+            executeQuery(selectDelayedPhasePercentages);
+            return parseDependencyInfos(selectDelayedPhasePercentages, infoType);
+        }
+
+        case DependencyInfos::Type::DependencyPhase:
+        {
+            selectDependencyPhasePercentages = QSqlQuery(database);
+            if (!selectDependencyPhasePercentages.prepare(queryTexts.selectDependencyPhasePercentages))
+                qDebug() << database.lastError().text();
+
+            executeQuery(selectDependencyPhasePercentages);
+            return parseDependencyInfos(selectDependencyPhasePercentages, infoType);
+        }
 
-    case DependencyInfos::Type::DependencyPhase:
-        executeQuery(selectDependencyPhasePercentages);
-        return parseDependencyInfos(selectDependencyPhasePercentages, infoType);
     }
 
     return dummy;
@@ -586,11 +617,11 @@ void TraceDB::mUpdateDependenciesFromQuery(QSqlQuery &query)
         QString dependencyTypeStr = query.value(2).toString();
         if (dependencyTypeStr == "bank")
         {
-            type = DependencyType::Bank;
+            type = DependencyType::IntraBank;
         }
         else if (dependencyTypeStr == "rank")
         {
-            type = DependencyType::Rank;
+            type = DependencyType::IntraRank;
         }
         else if (dependencyTypeStr == "interRank")
         {
@@ -642,6 +673,8 @@ DependencyInfos TraceDB::parseDependencyInfos(QSqlQuery &query, const Dependency
         infos.addInfo({query.value(0).toString(), query.value(1).toFloat()});
     }
 
+    query.finish();
+
     return infos;
 }
 
@@ -656,6 +689,7 @@ void TraceDB::executeQuery(QSqlQuery query)
     }
 
     else {
+        query.finish();
         throw sqlException( ("Query:\n " + queryToString(query) + "\n failed. Error: \n"
                              +
                              query.lastError().text()).toStdString(), this->pathToDB.toStdString());

DRAMSys/traceAnalyzer/data/tracedb.h

@@ -151,6 +151,9 @@ private:
     QVariant getParameterFromTable(const std::string& parameter, const std::string& table);
 
     std::map<unsigned int, std::shared_ptr<Phase>> _visiblePhases; // Updated at parseTransactionsFromQuery
+
+    // At businessObjects/phasedependenciestracker.h
+    friend class PhaseDependenciesTracker;
 };
 
 

DRAMSys/traceAnalyzer/evaluationtool.cpp

@@ -44,7 +44,6 @@
 #include <QDebug>
 #include <stdio.h>
 #include <iostream>
-#include <businessObjects/tracetestresults.h>
 #include <QApplication>
 #include <QFile>
 #include <QTextStream>
@@ -61,8 +60,6 @@ EvaluationTool::EvaluationTool(QWidget *parent) :
     ui->setupUi(this);
     traceFilesModel = new QStandardItemModel(this);
     ui->listView->setModel(traceFilesModel);
-    QObject::connect(ui->traceTestTreeWidget, SIGNAL(setMessage(QString)), this,
-                     SLOT(setTestMessage(QString)));
     selectMetrics = new SelectMetrics(this);
     QObject::connect(selectMetrics, SIGNAL(getSelectedMetrics()), this,
                      SLOT(getSelectedMetrics()));
@@ -81,16 +78,6 @@ void EvaluationTool::showForFiles(QList<QString> paths)
     ui->toolBox->setCurrentIndex(0);
 }
 
-void EvaluationTool::showAndRunTests(QList<QString> paths)
-{
-    cleanUpUI();
-    fillFileList(paths);
-    show();
-    ui->toolBox->setCurrentIndex(0);
-    selectMetrics->setMetrics(getMetrics());
-    runTests();
-}
-
 void EvaluationTool::showAndEvaluateMetrics(QList<QString> paths)
 {
     cleanUpUI();
@@ -118,9 +105,6 @@ void EvaluationTool::cleanUpUI()
     traceFilesModel->clear();
     calculatedMetrics.clear();
     ui->traceMetricTreeWidget->clear();
-    ui->traceTestTreeWidget->clear();
-    ui->testMessage->setPlainText(QString(""));
-    ui->testLight->setGray();
 }
 
 void EvaluationTool::fillFileList(QList<QString> paths)
@@ -134,43 +118,6 @@ void EvaluationTool::fillFileList(QList<QString> paths)
     }
 }
 
-void EvaluationTool::on_btn_test_clicked()
-{
-    runTests();
-}
-
-void EvaluationTool::runTests()
-{
-    ui->traceTestTreeWidget->clear();
-    ui->testLight->setGray();
-
-    bool allTestsPassed = true;
-    bool boxesChecked = false;
-
-    for (int row = 0; row < traceFilesModel->rowCount(); ++row)
-    {
-        TraceFileItem *item = static_cast<TraceFileItem *>(traceFilesModel->item(row));
-        if (item->checkState() == Qt::Checked)
-        {
-            boxesChecked = true;
-            TraceTestResults traceTestResult = PythonCaller::instance().runTestsOnTrace(item->getPath());
-            if (!traceTestResult.hasPassedAllTests())
-                allTestsPassed = false;
-            ui->traceTestTreeWidget->addTraceTestResult(traceTestResult);
-        }
-    }
-
-    if (!boxesChecked)
-        return;
-
-    ui->traceTestTreeWidget->expandAll();
-
-    if (allTestsPassed)
-        ui->testLight->setGreen();
-    else
-        ui->testLight->setRed();
-}
-
 void EvaluationTool::on_btn_calculateMetrics_clicked()
 {
     selectMetrics->raise();
@@ -203,11 +150,6 @@ void EvaluationTool::calculateMetrics(vector<long> selectedMetrics)
     ui->traceMetricTreeWidget->expandAll();
 }
 
-void EvaluationTool::setTestMessage(QString message)
-{
-    ui->testMessage->setPlainText(message);
-}
-
 EvaluationTool::TraceFileItem::TraceFileItem(const QString &path)
 {
     this->path = path;

DRAMSys/traceAnalyzer/evaluationtool.h

@@ -65,21 +65,16 @@ public:
     ~EvaluationTool();
 
     void showForFiles(QList<QString> paths);
-    void showAndRunTests(QList<QString> paths);
     void showAndEvaluateMetrics(QList<QString> paths);
 
 private Q_SLOTS:
-    void on_btn_test_clicked();
-    void setTestMessage(QString message);
     void on_btn_calculateMetrics_clicked();
     void on_btn_exportCSV_clicked();
     void on_btn_genPlots_clicked();
     void getSelectedMetrics();
 
-
 private:
     void fillFileList(QList<QString> paths);
-    void runTests();
     void cleanUpUI();
     void genPlots();
     void calculateMetrics(std::vector<long> selectedMetrics);

DRAMSys/traceAnalyzer/evaluationtool.ui

@@ -38,78 +38,15 @@
         </sizepolicy>
        </property>
        <property name="currentIndex">
-        <number>1</number>
+        <number>0</number>
        </property>
-       <widget class="QWidget" name="page">
-        <property name="geometry">
-         <rect>
-          <x>0</x>
-          <y>0</y>
-          <width>702</width>
-          <height>436</height>
-         </rect>
-        </property>
-        <attribute name="label">
-         <string>Test</string>
-        </attribute>
-        <layout class="QGridLayout" name="gridLayout_2">
-         <item row="0" column="0">
-          <layout class="QHBoxLayout" name="horizontalLayout_2">
-           <item>
-            <widget class="TraceTestTreeWidget" name="traceTestTreeWidget">
-             <column>
-              <property name="text">
-               <string notr="true">1</string>
-              </property>
-             </column>
-            </widget>
-           </item>
-           <item>
-            <layout class="QVBoxLayout" name="verticalLayout_2">
-             <item>
-              <widget class="QPushButton" name="btn_test">
-               <property name="text">
-                <string>Run tests</string>
-               </property>
-              </widget>
-             </item>
-             <item>
-              <layout class="QVBoxLayout" name="verticalLayout">
-               <item>
-                <widget class="TestLight" name="testLight" native="true">
-                 <property name="minimumSize">
-                  <size>
-                   <width>0</width>
-                   <height>30</height>
-                  </size>
-                 </property>
-                </widget>
-               </item>
-               <item>
-                <widget class="QLabel" name="label">
-                 <property name="text">
-                  <string>Message: </string>
-                 </property>
-                </widget>
-               </item>
-               <item>
-                <widget class="QPlainTextEdit" name="testMessage"/>
-               </item>
-              </layout>
-             </item>
-            </layout>
-           </item>
-          </layout>
-         </item>
-        </layout>
-       </widget>
        <widget class="QWidget" name="page_2">
         <property name="geometry">
          <rect>
           <x>0</x>
           <y>0</y>
-          <width>702</width>
-          <height>436</height>
+          <width>707</width>
+          <height>464</height>
          </rect>
         </property>
         <attribute name="label">
@@ -176,17 +113,6 @@
   </layout>
  </widget>
  <customwidgets>
-  <customwidget>
-   <class>TestLight</class>
-   <extends>QWidget</extends>
-   <header>presentation/util/testlight.h</header>
-   <container>1</container>
-  </customwidget>
-  <customwidget>
-   <class>TraceTestTreeWidget</class>
-   <extends>QTreeWidget</extends>
-   <header>presentation/tracetesttreewidget.h</header>
-  </customwidget>
   <customwidget>
    <class>TraceMetricTreeWidget</class>
    <extends>QTreeWidget</extends>

DRAMSys/traceAnalyzer/presentation/tracedrawingproperties.h

@@ -53,7 +53,7 @@ enum class ColorGrouping
     PhaseType,
     Transaction,
     Thread,
-    AlphaTransaction
+    RainbowTransaction
 };
 
 class TracePlotLineDataSource;

DRAMSys/traceAnalyzer/presentation/traceplot.cpp

@@ -190,10 +190,11 @@ void TracePlot::setUpActions()
     QObject::connect(setColorGroupingTransaction, SIGNAL(triggered()), this,
                      SLOT(on_colorGroupingTransaction()));
 
-    setColorGroupingAlphaTransaction = new QAction("Group by Transaction - Alpha Colored", this);
-    addAction(setColorGroupingAlphaTransaction);
-    QObject::connect(setColorGroupingAlphaTransaction, SIGNAL(triggered()), this,
-                     SLOT(on_colorGroupingAlphaTransaction()));
+    setColorGroupingRainbowTransaction = new QAction("Group by Transaction - Rainbow Colored", this);
+    setColorGroupingRainbowTransaction->setCheckable(true);
+    addAction(setColorGroupingRainbowTransaction);
+    QObject::connect(setColorGroupingRainbowTransaction, SIGNAL(triggered()), this,
+                     SLOT(on_colorGroupingRainbowTransaction()));
 
     setColorGroupingThread = new QAction("Group by Thread", this);
     setColorGroupingThread->setCheckable(true);
@@ -204,6 +205,7 @@ void TracePlot::setUpActions()
     QActionGroup *colorGroupingGroup = new QActionGroup(this);
     colorGroupingGroup->addAction(setColorGroupingPhase);
     colorGroupingGroup->addAction(setColorGroupingTransaction);
+    colorGroupingGroup->addAction(setColorGroupingRainbowTransaction);
     colorGroupingGroup->addAction(setColorGroupingThread);
 
     exportToPdf = new QAction("Export to SVG", this);
@@ -271,7 +273,7 @@ void TracePlot::setUpContextMenu()
 
     QMenu *colorGroupingSubMenu = new QMenu("Group by", contextMenu);
     colorGroupingSubMenu->addActions(
-        {setColorGroupingPhase, setColorGroupingTransaction, setColorGroupingThread, setColorGroupingAlphaTransaction});
+        {setColorGroupingPhase, setColorGroupingTransaction, setColorGroupingRainbowTransaction, setColorGroupingThread});
     contextMenu->addMenu(colorGroupingSubMenu);
 
     dependenciesSubMenu = new QMenu("Show dependencies", contextMenu);
@@ -588,6 +590,9 @@ void TracePlot::currentTraceTimeChanged()
     }
 
     setAxisScale(xBottom, GetCurrentTimespan().Begin(), GetCurrentTimespan().End());
+    
+    dependenciesSubMenu->setEnabled(navigator->TraceFile().checkDependencyTableExists());
+
     replot();
 }
 
@@ -661,10 +666,10 @@ void TracePlot::on_colorGroupingTransaction()
     replot();
 }
 
-void TracePlot::on_colorGroupingAlphaTransaction()
+void TracePlot::on_colorGroupingRainbowTransaction()
 {
-    drawingProperties.colorGrouping = ColorGrouping::AlphaTransaction;
-    Q_EMIT(colorGroupingChanged(ColorGrouping::AlphaTransaction));
+    drawingProperties.colorGrouping = ColorGrouping::RainbowTransaction;
+    Q_EMIT(colorGroupingChanged(ColorGrouping::RainbowTransaction));
     replot();
 }
 

DRAMSys/traceAnalyzer/presentation/traceplot.h

@@ -109,7 +109,7 @@ private Q_SLOTS:
     void on_colorGroupingPhase();
     void on_colorGroupingTransaction();
     void on_colorGroupingThread();
-    void on_colorGroupingAlphaTransaction();
+    void on_colorGroupingRainbowTransaction();
     void on_goToTransaction();
     void on_goToPhase();
     void on_deselectAll();
@@ -187,7 +187,7 @@ private:
     QAction *setColorGroupingPhase;
     QAction *setColorGroupingTransaction;
     QAction *setColorGroupingThread;
-    QAction *setColorGroupingAlphaTransaction;
+    QAction *setColorGroupingRainbowTransaction;
     QAction *exportToPdf;
     ToggleCollapsedAction *toggleCollapsedState;
 

DRAMSys/traceAnalyzer/presentation/tracetesttreewidget.cpp

@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2015, Technische Universität Kaiserslautern
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- *    contributors may be used to endorse or promote products derived from
- *    this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors:
- *    Janik Schlemminger
- *    Robert Gernhardt
- *    Matthias Jung
- */
-
-#include "tracetesttreewidget.h"
-
-TraceTestTreeWidget::TraceTestTreeWidget(QWidget *parent) : QTreeWidget(parent)
-{
-    QObject::connect(this, SIGNAL(itemSelectionChanged()), this,
-                     SLOT(itemSelectionChanged()));
-    setHeaderHidden(true);
-}
-
-void TraceTestTreeWidget::addTraceTestResult(const TraceTestResults
-                                             &traceTestResult)
-{
-    QTreeWidgetItem *top = new QTreeWidgetItem({traceTestResult.getTraceName()});
-    addTopLevelItem(top);
-
-    if (traceTestResult.hasPassedAllTests())
-        top->setForeground(0, Qt::green);
-    else
-        top->setForeground(0, Qt::red);
-
-    for (const TestResult &testResult : traceTestResult.getTestResults()) {
-        new TestResultTreeItem(top, testResult);
-    }
-}
-
-void TraceTestTreeWidget::itemSelectionChanged()
-{
-    if (!selectedItems().isEmpty()
-            && selectedItems().at(0)->type() ==
-            TestResultTreeItem::testResultTreeItemType) {
-        TestResultTreeItem *testResultItem = static_cast<TestResultTreeItem *>
-                                             (selectedItems().at(0));
-        Q_EMIT setMessage(testResultItem->getMessage());
-    } else {
-        setMessage(QString(""));
-    }
-}
-
-TraceTestTreeWidget::TestResultTreeItem::TestResultTreeItem(
-    QTreeWidgetItem *parent, const TestResult &testResult)
-    : QTreeWidgetItem(parent, testResultTreeItemType)
-{
-    setText(0, testResult.getTestName());
-    if (!testResult.hasPassed())
-        setForeground(0, Qt::red);
-    message = testResult.getMessage();
-}

DRAMSys/traceAnalyzer/presentation/util/colorgenerator.cpp

@@ -38,79 +38,30 @@
 
 #include "colorgenerator.h"
 #include <exception>
-ColorGenerator::ColorGenerator()
+
+QColor ColorGenerator::getColor(unsigned int i, ColorName color)
 {
-    r[0] = 0xFF;
-    r[1] = 0x00;
-    r[2] = 0x00;
-    r[3] = 0xFF;
-    g[0] = 0x00;
-    g[1] = 0xFF;
-    g[2] = 0x00;
-    g[3] = 0xFF;
-    b[0] = 0x00;
-    b[1] = 0x00;
-    b[2] = 0xFF;
-    b[3] = 0x00;
-
-    r[4] = 0xFF;
-    r[5] = 0x00;
-    r[6] = 0xFF;
-    r[7] = 0x6B;
-    g[4] = 0x00;
-    g[5] = 0xFF;
-    g[6] = 0xA5;
-    g[7] = 0x8E;
-    b[4] = 0xFF;
-    b[5] = 0xFF;
-    b[6] = 0x00;
-    b[7] = 0x23;
-
-    r[8] = 0x8A;
-    r[9] = 0xFF;
-    r[10] = 0x7C;
-    r[11] = 0x00;
-    g[8] = 0x2B;
-    g[9] = 0xD7;
-    g[10] = 0xFC;
-    g[11] = 0x00;
-    b[8] = 0xE2;
-    b[9] = 0x00;
-    b[10] = 0x00;
-    b[11] = 0x80;
-
-    r[12] = 0x80;
-    r[13] = 0x00;
-    r[14] = 0xEE;
-    r[15] = 0xFF;
-    g[12] = 0x00;
-    g[13] = 0x80;
-    g[14] = 0x82;
-    g[15] = 0x45;
-    b[12] = 0x00;
-    b[13] = 0x00;
-    b[14] = 0xEE;
-    b[15] = 0x00;
+    switch(color) {
+        case ColorName::Default:
+            return cDefault.getColor(i);
+        case ColorName::HSV15:
+            return cHSV15.getColor(i);
+    }
 
+    return {0, 0, 0};
 }
 
-QColor ColorGenerator::getColor(unsigned int i)
+QColor ColorGenerator::getRainbowColored(unsigned int i, ColorName color)
 {
-    static ColorGenerator gen;
-    i = i % 16;
-    QColor result(gen.r[i], gen.g[i], gen.b[i]);
-    result.setAlpha(130);
-    return result;
+    switch(color) {
+        case ColorName::Default:
+            return cDefault.getRainbowColored(i);
+        case ColorName::HSV15:
+            return cHSV15.getRainbowColored(i);
+    }
+
+    return {0, 0, 0};
 }
 
-QColor ColorGenerator::getAlphaColored(unsigned int i)
-{
-    static ColorGenerator gen;
-    const int minAlpha = 25;
-    const int alphaLevels = 40 - 255 / minAlpha;
-    int alpha = minAlpha + (int)(((255. - minAlpha) / alphaLevels) * (i % alphaLevels));
-    i = (i / alphaLevels) % 16;
-    QColor result(gen.r[i], gen.g[i], gen.b[i]);
-    result.setAlpha(alpha);
-    return result;
-}
+ColorDefault ColorGenerator::cDefault;
+ColorHSV15 ColorGenerator::cHSV15;

DRAMSys/traceAnalyzer/presentation/util/colorgenerator.h

@@ -39,21 +39,28 @@
 #ifndef COLORGENERATOR_H
 #define COLORGENERATOR_H
 
+#include "colorobject.h"
+
 #include <stdint.h>
 #include <QColor>
 
+enum ColorName
+{
+    Default,
+    HSV15
+};
+
 class ColorGenerator
 {
 private:
-    static constexpr int NumberOfColors = 16;
-    int r[NumberOfColors];
-    int g[NumberOfColors];
-    int b[NumberOfColors];
-    ColorGenerator();
+    ColorGenerator() = delete;
+
+    static ColorDefault cDefault;
+    static ColorHSV15 cHSV15;
 
 public:
-    static QColor getColor(unsigned int i);
-    static QColor getAlphaColored(unsigned int i);
+    static QColor getColor(unsigned int i, ColorName color = ColorName::Default);
+    static QColor getRainbowColored(unsigned int i, ColorName color = ColorName::Default);
 };
 
 

DRAMSys/traceAnalyzer/presentation/util/colorobject.cpp

@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2015, Technische Universität Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors:
+ *    Janik Schlemminger
+ *    Robert Gernhardt
+ *    Matthias Jung
+ *    Iron Prando da Silva
+ */
+
+#include "colorobject.h"
+
+
+QColor ColorObject::getColor(unsigned int i)
+{
+    i = i % numberOfColors;
+    QColor result(r[i], g[i], b[i]);
+    result.setAlpha(130);
+    return result;
+}
+
+QColor ColorObject::getRainbowColored(unsigned int i)
+{
+    const int minAlpha = 50;
+    const int alphaLevels = 20 - 255 / minAlpha;
+    const int alphaStep = (255. - minAlpha) / alphaLevels;
+
+    int alpha = minAlpha + (int)(alphaStep * (i % alphaLevels));
+    i = (i / alphaLevels) % numberOfColors;
+    QColor result(r[i], g[i], b[i]);
+    result.setAlpha(alpha);
+
+    return result;
+}
+
+ColorDefault::ColorDefault() 
+{
+    numberOfColors = 16;
+
+    r.resize(numberOfColors);
+    g.resize(numberOfColors);
+    b.resize(numberOfColors);
+
+    r[0] = 0xFF;
+    r[1] = 0x00;
+    r[2] = 0x00;
+    r[3] = 0xFF;
+    g[0] = 0x00;
+    g[1] = 0xFF;
+    g[2] = 0x00;
+    g[3] = 0xFF;
+    b[0] = 0x00;
+    b[1] = 0x00;
+    b[2] = 0xFF;
+    b[3] = 0x00;
+
+    r[4] = 0xFF;
+    r[5] = 0x00;
+    r[6] = 0xFF;
+    r[7] = 0x6B;
+    g[4] = 0x00;
+    g[5] = 0xFF;
+    g[6] = 0xA5;
+    g[7] = 0x8E;
+    b[4] = 0xFF;
+    b[5] = 0xFF;
+    b[6] = 0x00;
+    b[7] = 0x23;
+
+    r[8] = 0x8A;
+    r[9] = 0xFF;
+    r[10] = 0x7C;
+    r[11] = 0x00;
+    g[8] = 0x2B;
+    g[9] = 0xD7;
+    g[10] = 0xFC;
+    g[11] = 0x00;
+    b[8] = 0xE2;
+    b[9] = 0x00;
+    b[10] = 0x00;
+    b[11] = 0x80;
+
+    r[12] = 0x80;
+    r[13] = 0x00;
+    r[14] = 0xEE;
+    r[15] = 0xFF;
+    g[12] = 0x00;
+    g[13] = 0x80;
+    g[14] = 0x82;
+    g[15] = 0x45;
+    b[12] = 0x00;
+    b[13] = 0x00;
+    b[14] = 0xEE;
+    b[15] = 0x00;
+}
+
+ColorHSV15::ColorHSV15()
+{
+    numberOfColors = 15;
+
+    r.resize(numberOfColors);
+    g.resize(numberOfColors);
+    b.resize(numberOfColors);
+
+    r[0] = 0XFF;
+    r[1] = 0XFF;
+    r[2] = 0XFF;
+    r[3] = 0XD1;
+    r[4] = 0X6C;
+    r[5] = 0X08;
+    r[6] = 0X00;
+    r[7] = 0X00;
+    r[8] = 0X00;
+    r[9] = 0X00;
+    r[10] = 0X00;
+    r[11] = 0X54;
+    r[12] = 0XB9;
+    r[13] = 0XFF;
+    r[14] = 0XFF;
+
+    g[0] = 0X00;
+    g[1] = 0X64;
+    g[2] = 0XC9;
+    g[3] = 0XFF;
+    g[4] = 0XFF;
+    g[5] = 0XFF;
+    g[6] = 0XFF;
+    g[7] = 0XFF;
+    g[8] = 0XD9;
+    g[9] = 0X74;
+    g[10] = 0X10;
+    g[11] = 0X00;
+    g[12] = 0X00;
+    g[13] = 0X00;
+    g[14] = 0X00;
+
+    b[0] = 0X00;
+    b[1] = 0X00;
+    b[2] = 0X00;
+    b[3] = 0X00;
+    b[4] = 0X00;
+    b[5] = 0X00;
+    b[6] = 0X5C;
+    b[7] = 0XC1;
+    b[8] = 0XFF;
+    b[9] = 0XFF;
+    b[10] = 0XFF;
+    b[11] = 0XFF;
+    b[12] = 0XFF;
+    b[13] = 0XE1;
+    b[14] = 0X7C;
+}

DRAMSys/traceAnalyzer/presentation/util/colorobject.h

@@ -33,36 +33,39 @@
  *    Janik Schlemminger
  *    Robert Gernhardt
  *    Matthias Jung
+ *    Iron Prando da Silva
  */
 
-#ifndef TRACETESTRESULT_H
-#define TRACETESTRESULT_H
-#include <QString>
-#include <vector>
-#include "testresult.h"
+#pragma once
 
-class TraceTestResults
+#include <QColor>
+
+class ColorObject
 {
+protected:
+    int numberOfColors = 0;
+
+    std::vector<int> r;
+    std::vector<int> g;
+    std::vector<int> b;
+    // std::vector<int> a;
+
+    ColorObject() {};
+    
 public:
-    TraceTestResults(const QString &traceName): traceName(traceName) {}
 
-    void addTestResult(const TestResult &result)
-    {
-        testResults.push_back(result);
-    }
-
-    QString getTraceName() const
-    {
-        return traceName;
-    }
-    bool hasPassedAllTests() const;
-    const std::vector<TestResult>  &getTestResults() const
-    {
-        return testResults;
-    }
-private:
-    QString traceName;
-    std::vector<TestResult> testResults;
+    virtual QColor getColor(unsigned int i);
+    virtual QColor getRainbowColored(unsigned int i);
 };
 
-#endif // TRACETESTRESULT_H
+class ColorDefault : public ColorObject
+{
+public:
+    ColorDefault();
+};
+
+class ColorHSV15 : public ColorObject
+{
+public:
+    ColorHSV15();
+};

DRAMSys/traceAnalyzer/traceanalyzer.cpp

@@ -77,9 +77,6 @@ TraceAnalyzer::TraceAnalyzer(QSet<QString> paths, StartupOption option,
 
     for (const QString &path : paths)
         openTracefileTab(path);
-
-    if (option == StartupOption::runTests)
-        ui->actionTest->trigger();
 }
 
 TraceAnalyzer::~TraceAnalyzer()
@@ -245,13 +242,6 @@ void TraceAnalyzer::statusChanged(const QString &message)
     statusLabel->setText(message + QTime::currentTime().toString());
 }
 
-void TraceAnalyzer::on_actionTest_triggered()
-{
-    evaluationTool.raise();
-    evaluationTool.activateWindow();
-    evaluationTool.showAndRunTests(openedTraceFiles.values());
-}
-
 void TraceAnalyzer::on_actionMetrics_triggered()
 {
     evaluationTool.raise();

DRAMSys/traceAnalyzer/traceanalyzer.h

@@ -92,7 +92,6 @@ private Q_SLOTS:
     void on_actionReload_triggered();
     void on_actionReload_all_triggered();
     void on_actionExportAsVCD_triggered();
-    void on_actionTest_triggered();
     void on_actionMetrics_triggered();
     void on_actionClose_triggered();
     void on_actionClose_all_triggered();

DRAMSys/traceAnalyzer/traceanalyzer.ui

@@ -49,7 +49,7 @@
      <x>0</x>
      <y>0</y>
      <width>800</width>
-     <height>23</height>
+     <height>34</height>
     </rect>
    </property>
    <widget class="QMenu" name="menuFile">
@@ -64,7 +64,6 @@
     <addaction name="separator"/>
     <addaction name="actionExportAsVCD"/>
     <addaction name="separator"/>
-    <addaction name="actionTest"/>
     <addaction name="actionMetrics"/>
     <addaction name="separator"/>
     <addaction name="actionClose"/>
@@ -234,7 +233,8 @@
   </action>
   <action name="actionSimulate">
    <property name="icon">
-    <iconset theme="system-run"/>
+    <iconset theme="system-run">
+     <normaloff>.</normaloff>.</iconset>
    </property>
    <property name="text">
     <string>&amp;Simulate...</string>

DRAMSys/traceAnalyzer/tracefiletab.cpp

@@ -44,6 +44,7 @@
 #include "businessObjects/pythoncaller.h"
 #include "businessObjects/traceplotlinemodel.h"
 #include "businessObjects/tracetime.h"
+#include "businessObjects/dramTimeDependencies/phasedependenciestracker.h"
 #include "qmessagebox.h"
 #include "queryeditor.h"
 #include "qwt_legend.h"
@@ -100,6 +101,8 @@ TraceFileTab::TraceFileTab(QWidget *parent, const QString &path)
     setUpTraceplotScrollbar();
     setUpCommentView();
 
+    setUpPossiblePhases();
+
     tracefileChanged();
 }
 
@@ -212,6 +215,18 @@ void TraceFileTab::setUpCommentView()
                      commentModel, &CommentModel::rowDoubleClicked);
 }
 
+void TraceFileTab::setUpPossiblePhases() {
+    const auto possiblePhases = ConfigurationFactory::possiblePhases(navigator->TraceFile());
+    for (auto p : possiblePhases) {
+        auto item = new QListWidgetItem(p, ui->depTabPossiblePhases);
+        item->setFlags(item->flags() | Qt::ItemIsUserCheckable); // set checkable flag
+        item->setCheckState(Qt::Unchecked); // AND initialize check state
+
+    }
+
+    ui->calculateDependencies->setEnabled(ConfigurationFactory::deviceSupported(navigator->TraceFile()));
+}
+
 void TraceFileTab::tracefileChanged()
 {
     if (savingChangesToDB == true) {
@@ -356,6 +371,22 @@ bool TraceFileTab::eventFilter(QObject *object, QEvent *event)
     return QWidget::eventFilter(object, event);
 }
 
+void TraceFileTab::on_calculateDependencies_clicked() {
+    std::vector<QString> dependencyFilter;
+    for (int row = 0; row < ui->depTabPossiblePhases->count(); row++) {
+        auto item = ui->depTabPossiblePhases->item(row);
+        if (item->checkState() == Qt::Checked)
+            dependencyFilter.push_back(item->text());
+    }
+    
+    savingChangesToDB = true;
+    PhaseDependenciesTracker::calculateDependencies(navigator->TraceFile(), dependencyFilter);
+    depInfosView = new DependencyInfosModel(navigator->TraceFile(), this);
+    ui->depInfosView->setModel(depInfosView);
+    ui->depInfosView->header()->setSectionResizeMode(QHeaderView::ResizeToContents);
+
+}
+
 void TraceFileTab::on_startLatencyAnalysis_clicked()
 {
     // Setup Database:
@@ -454,6 +485,7 @@ void TraceFileTab::on_startPowerAnalysis_clicked()
     data->setSamples(*samples);
     cur->setData(data);
     cur->attach(ui->powerPlot);
+    cur->setPen(QPen(QColor(255,0,0)));
 
     QwtPlotMagnifier *mag1 = new QwtPlotMagnifier(ui->powerPlot->canvas());
     mag1->setAxisEnabled(QwtPlot::xBottom, true);
@@ -482,6 +514,7 @@ void TraceFileTab::on_startPowerAnalysis_clicked()
     data2->setSamples(*samples2);
     cur2->setData(data2);
     cur2->attach(ui->bandwidthPlot);
+    cur2->setPen(QPen(QColor(255,0,0)));
 
     ui->bandwidthPlot->setAxisTitle(0,"Bandwidth [%]");
     ui->bandwidthPlot->setAxisScale(0,0.0,100.0);
@@ -526,6 +559,7 @@ void TraceFileTab::on_startPowerAnalysis_clicked()
     data3->setSamples(*samples3);
     cur3->setData(data3);
     cur3->attach(ui->bufferPlot);
+    cur3->setPen(QPen(QColor(255,0,0)));
 
     ui->bufferPlot->setAxisTitle(0,"Buffer Utilization");
     ui->bufferPlot->setAxisScale(0,0.0, maxBufferDepth);

DRAMSys/traceAnalyzer/tracefiletab.h

@@ -49,6 +49,8 @@
 #include <QString>
 #include <QTreeWidget>
 #include <QWidget>
+#include "businessObjects/configmodels.h"
+#include "businessObjects/dependencymodels.h"
 
 class CommentModel;
 class McConfigModel;
@@ -70,6 +72,8 @@ public:
     void setUpTraceplotScrollbar();
     void setUpCommentView();
     void setUpTraceSelector();
+    void setUpPossiblePhases();
+
     void initNavigatorAndItsDependentWidgets(QString path);
     QString getPathToTraceFile()
     {
@@ -125,6 +129,7 @@ Q_SIGNALS:
 
 private Q_SLOTS:
     void on_latencyTreeView_doubleClicked(const QModelIndex &index);
+    void on_calculateDependencies_clicked();
     void on_startLatencyAnalysis_clicked();
     void on_startPowerAnalysis_clicked();
 };

DRAMSys/traceAnalyzer/tracefiletab.ui

@@ -274,6 +274,17 @@
           </property>
          </widget>
         </item>
+        <item>
+         <widget class="QListWidget" name="depTabPossiblePhases">
+         </widget>
+        </item>
+        <item>
+         <widget class="QPushButton" name="calculateDependencies">
+          <property name="text">
+           <string>Calculate Dependencies</string>
+          </property>
+         </widget>
+        </item>
        </layout>
       </widget>
       
@@ -306,6 +317,7 @@
         </item>
        </layout>
       </widget>
+
       <widget class="QWidget" name="tabLatencyAnalysis">
        <property name="sizePolicy">
         <sizepolicy hsizetype="Ignored" vsizetype="Ignored">
@@ -354,6 +366,7 @@
         </item>
        </layout>
       </widget>
+     
       <widget class="QWidget" name="tabPowerAnalysis">
        <property name="enabled">
         <bool>true</bool>

README.md

@@ -19,11 +19,11 @@ If you decide to use DRAMSys in your research please cite the papers [2] [3]. To
 
 - **standalone** simulator with trace players, **gem5**-coupled simulator and **TLM-AT-compliant library**
 - support for **DDR3/4**, **LPDDR4**, **Wide I/O 1/2**, **GDDR5/5X/6** and **HBM1/2**
-- support for **DDR5** and **LPDDR5** under development (contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de) for more information) 
+- support for **DDR5**, **LPDDR5** and **HBM3** under development (contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de) for more information) 
 - automatic source code generation for new JEDEC standards [3] [9] from the domain-specific language DRAMml
 - FIFO, FR-FCFS and FR-FCFS with read/write grouping scheduling policies
 - open, closed, open adaptive and closed adaptive page policy [8]
-- all-bank refresh and per-bank refresh with pulled-in and postponed refresh commands
+- all-bank refresh, same-bank refresh and per-bank refresh with pulled-in and postponed refresh commands
 - staggered power down [5]
 - coupling to **DRAMPower** [4] and **3D-ICE** [8] for power and thermal simulation
 - **Trace Analyzer** for visual and metric-based result analysis
@@ -42,23 +42,22 @@ All requests, responses and DRAM commands can be recorded in an SQLite trace dat
 
 The Trace Analyzer's main window is shown below.
 
-If you are interested in the database recording feature and the Trace Analyzer, if you need support on how to setup DRAMSys in a virtual platform of your company, or if you require custom modifications of the simulator please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de).
+If you are interested in the Trace Analyzer, if you need support with the setup of DRAMSys in a virtual platform of your company, or if you require custom modifications of the simulator please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de).
 
 ![Trace Analyzer Main Window](DRAMSys/docs/images/traceanalyzer.png) 
 
 ## Basic Setup
 
 Start using DRAMSys by cloning the repository.
-Use the `--recursive` flag to initialize all submodules within the repository, namely **DRAMPower**, **SystemC** and **nlohmann json**.
+Use the `--recursive` flag to initialize all submodules within the repository, namely **DRAMPower**, **SystemC**, **nlohmann JSON** and **SQLite Amalgamation**.
 
 ### Dependencies
 
-DRAMSys is based on the SystemC library. SystemC is included as a submodule and will be build automatically with the DRAMSys project. If you want to use an external SystemC version, export the environment variables `SYSTEMC_HOME` (SystemC root directory) and `SYSTEMC_TARGET_ARCH` (e.g. linux64) and add the path of the library to `LD_LIBRARY_PATH`.
+DRAMSys requires a **C++17** compiler. The build process is based on **CMake** (minimum version **3.10**). Furthermore, the simulator is based on **SystemC**. SystemC is included as a submodule and will be build automatically with the project. If you want to use an external SystemC version, export the environment variables `SYSTEMC_HOME` (SystemC root directory) and `SYSTEMC_TARGET_ARCH` (e.g., linux64).
 
 ### Building DRAMSys
-DRAMSys uses CMake for the build process, the minimum required version is **CMake 3.10**.
 
-To build the standalone simulator for running memory trace files, create a build folder in the project root directory, then run CMake and make:
+To build the standalone simulator for running memory trace files or a traffic generator, create a build folder in the project root directory, then run CMake and make:
 
 ```bash
 $ cd DRAMSys
@@ -91,7 +90,7 @@ $ cd simulator
 $ ./DRAMSys
 ```
 
-The default base config file is *ddr3-example.json* and located in *DRAMSys/library/resources/simulations*, the default resource folder for all nested config files is *DRAMSys/library/resources*.
+The default base config file is *ddr3-example.json* located in *DRAMSys/library/resources/simulations*, the default resource folder for all nested config files is *DRAMSys/library/resources*.
 
 To run DRAMSys with a specific base config file:
 
@@ -107,7 +106,7 @@ $ ./DRAMSys ../../DRAMSys/tests/example_ddr3/simulations/ddr3-example.json ../..
 
 ### DRAMSys Configuration
 
-The DRAMSys executable supports one argument which is a JSON file that contains certain arguments and the path of other configuration files for the desired simulation.
+The DRAMSys executable supports one argument, which is a JSON file that contains certain arguments and the name of nested configuration files for the desired simulation. Alternatively, the contents of nested configuration files can also be added directly to the top configuration file instead of the file name.
 
 The JSON code below shows an example configuration:
 
@@ -150,7 +149,7 @@ The JSON code below shows an example configuration:
     }
 }
 ```
-Fields Description:
+Field Descriptions:
 - "simulationid": simulation file identifier
 - "simconfig": configuration file for the DRAMSys simulator
 - "thermalconfig": thermal simulation configuration file
@@ -162,9 +161,9 @@ Fields Description:
 Each **trace setup** device configuration can be a **trace player** ("type": "player"), a **traffic generator** ("type": "generator") or a **row hammer generator** ("type": "hammer"). By not specifing the **type** parameter, the device will act as a **trace player**.
 All device configurations must define a **clkMhz** (operation frequency of the **traffic initiator**) and a **name** (in case of a trace player this specifies the **trace file** to play; in case of a generator this field is only for identification purposes).
 The optional parameter **addLengthConverter** adds a transaction length converter between initiator and DRAMSys. This unit divides a large transaction up into several smaller transactions with the maximum length of one DRAM burst access.
-The **maxPendingReadRequests** and **maxPendingWriteRequests** parameters define the maximum number of outstanding read/write requests. The current implementation delays all memory accesses when one limit is reached. The default value (0) disables the limit.
+The **maxPendingReadRequests** and **maxPendingWriteRequests** parameters define the maximum number of outstanding read/write requests. The current implementation delays all memory accesses if one limit is reached. The default value (0) disables the limit.
 
-A **traffic generator** can be configured to generate **numRequests** requests in total, of which the **rwRatio** field defines the probability of one request being a read request. The **seed** parameter can be used to produce identical results for all simulations. **minAddress** and **maxAddress** specify the address range, by default the whole address range is used. The parameter **addressDistribution** can either be set to **"random"** or **"sequential"**. In case of **"sequential"** the additional **addressIncrement** field must be specified, defining the address increment after each request.
+A **traffic generator** can be configured to generate **numRequests** requests in total, of which the **rwRatio** field defines the probability of one request being a read request. The length of a request (in bytes) can be specified with the **dataLength** parameter. The **seed** parameter can be used to produce identical results for all simulations. **minAddress** and **maxAddress** specify the address range, by default the whole address range is used. The parameter **addressDistribution** can either be set to **random** or **sequential**. In case of **sequential** the additional **addressIncrement** field must be specified, defining the address increment after each request.
 
 The **row hammer generator** is a special traffic generator that mimics a row hammer attack. It generates **numRequests** alternating read requests to two different addresses. The first address is 0x0, the second address is specified by the **rowIncrement** parameter and should decode to a different row in the same bank. Since only one outstanding request is allowed, the controller cannot perform any reordering, forcing a row switch (precharge and activate) for each access. That way the number of activations on the target rows are maximized.
 
@@ -567,6 +566,7 @@ The content of [config.json](DRAMSys/library/resources/configs/thermalsim/config
 The development of DRAMSys was supported by the German Research Foundation (DFG) as part of the priority program [Dependable Embedded Systems SPP1500](http://spp1500.itec.kit.edu) and the DFG grant no. [WE2442/10-1](https://www.uni-kl.de/en/3d-dram/). Furthermore, it was supported within the Fraunhofer and DFG cooperation program (grant no. [WE2442/14-1](https://www.iese.fraunhofer.de/en/innovation_trends/autonomous-systems/memtonomy.html)) and by the [Fraunhofer High Performance Center for Simulation- and Software-Based Innovation](https://www.leistungszentrum-simulation-software.de/en.html). Special thanks go to all listed contributors for their work and commitment during seven years of development. 
 
 Shama Bhosale  
+Derek Christ  
 Luiza Correa  
 Peter Ehses  
 Johannes Feldmann  
@@ -576,7 +576,8 @@ Matthias Jung
 Frederik Lauer  
 Ana Mativi  
 Felipe S. Prado  
-Tran Anh Quoc   
+Iron Prando  
+Tran Anh Quoc  
 Janik Schlemminger  
 Lukas Steiner  
 Thanh C. Tran  
@@ -611,4 +612,4 @@ M. Jung, I. Heinrich, M. Natale, D. M. Mathew, C. Weis, S. Krumke, N. Wehn. Inte
 A. Hansson, N. Agarwal, A. Kolli, T. Wenisch, A. N. Udipi. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014, Monterey, USA.
 
 [9] Fast Validation of DRAM Protocols with Timed Petri Nets  
-M. Jung, K. Kraft, T. Soliman, C. Sudarshan, C. Weis, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2019), October, 2019, Washington, DC, USA.
+M. Jung, K. Kraft, T. Soliman, C. Sudarshan, C. Weis, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2019), October, 2019, Washington, DC, USA.