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checkers, added RDA/WRA support, changed default time unit to PS

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This commit is contained in:
robert
2014-04-08 23:12:11 +02:00
parent 9c6fcee6b8
commit 15944fe743
30 changed files with 240 additions and 175 deletions
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16
dram/.cproject
View File

@@ -19,7 +19,7 @@
<builder autoBuildTarget="all" buildPath="${workspace_loc:/dram}/build-simulation" cleanBuildTarget="clean" enableAutoBuild="false" id="org.eclipse.cdt.build.core.internal.builder.1698165306" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="org.eclipse.cdt.build.core.internal.builder"/>
<tool id="cdt.managedbuild.tool.gnu.archiver.base.1509734096" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug.789860529" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug">
<option id="gnu.cpp.compiler.exe.debug.option.optimization.level.2041174282" name="Optimization Level" superClass="gnu.cpp.compiler.exe.debug.option.optimization.level" value="gnu.cpp.compiler.optimization.level.most" valueType="enumerated"/>
<option id="gnu.cpp.compiler.exe.debug.option.optimization.level.2041174282" name="Optimization Level" superClass="gnu.cpp.compiler.exe.debug.option.optimization.level" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>
<option id="gnu.cpp.compiler.exe.debug.option.debugging.level.2092267417" name="Debug Level" superClass="gnu.cpp.compiler.exe.debug.option.debugging.level" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
<option id="gnu.cpp.compiler.option.include.paths.1823643375" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="/opt/systemc-2.3.0/include"/>
@@ -61,8 +61,8 @@
<option id="gnu.cpp.link.option.paths.1916142213" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
<listOptionValue builtIn="false" value="/opt/systemc-2.3.0/lib-linux64"/>
</option>
<option id="gnu.cpp.link.option.debugging.prof.631946268" name="Generate prof information (-p)" superClass="gnu.cpp.link.option.debugging.prof" value="true" valueType="boolean"/>
<option id="gnu.cpp.link.option.debugging.gprof.1817867753" name="Generate gprof information (-pg)" superClass="gnu.cpp.link.option.debugging.gprof" value="true" valueType="boolean"/>
<option id="gnu.cpp.link.option.debugging.prof.631946268" name="Generate prof information (-p)" superClass="gnu.cpp.link.option.debugging.prof" value="false" valueType="boolean"/>
<option id="gnu.cpp.link.option.debugging.gprof.1817867753" name="Generate gprof information (-pg)" superClass="gnu.cpp.link.option.debugging.gprof" value="false" valueType="boolean"/>
<inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.1335058803" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
@@ -96,24 +96,24 @@
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="refreshScope" versionNumber="2">
<configuration configurationName="unit_test"/>
<configuration configurationName="Release">
<resource resourceType="PROJECT" workspacePath="/DRAM-Model"/>
</configuration>
<configuration configurationName="unit_test"/>
<configuration configurationName="platformArchitect">
<resource resourceType="PROJECT" workspacePath="/DRAM"/>
</configuration>
<configuration configurationName="build-simulation"/>
<configuration configurationName="testing"/>
<configuration configurationName="Debug">
<resource resourceType="PROJECT" workspacePath="/DRAM-Model"/>
</configuration>
<configuration configurationName="simulation-build">
<resource resourceType="PROJECT" workspacePath="/dram"/>
</configuration>
<configuration configurationName="Debug">
<resource resourceType="PROJECT" workspacePath="/DRAM-Model"/>
</configuration>
<configuration configurationName="standalone"/>
<configuration configurationName="build-testing"/>
<configuration configurationName="simulation"/>
<configuration configurationName="build-testing"/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings">
<doc-comment-owner id="org.eclipse.cdt.internal.ui.text.doctools.NullDocCommentOwner">

2
dram/.settings/language.settings.xml
View File

@@ -4,7 +4,7 @@
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-2055719358" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot; -std=c++11">
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-64906255729110141" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot; -std=c++11">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>

2
dram/resources/configs/memspecs/MatzesWideIO.xml
View File

@@ -26,7 +26,7 @@
<parameter id="WR" type="uint" value="2" />
<parameter id="XP" type="uint" value="2" />
<!--<parameter id="XPDLL" type="uint" value="2" />-->
<parameter id="XS" type="uint" value="24" /><!--tRFC+2clk-->
<parameter id="XS" type="uint" value="2" /><!--tRFC+2clk-->
<!--<parameter id="XSDLL" type="uint" value="20" />-->
<parameter id="REFI" type="uint" value="3120" />
<!--<parameter id="CL" type="uint" value="3" />-->

23
dram/resources/scripts/metrics.py
View File

@@ -73,34 +73,31 @@ def timeInPowerStates(connection):
cursor.execute("SELECT SUM(PhaseEnd-PhaseBegin) from Phases where PhaseName = 'PDNA'")
timeInPDNA = cursor.fetchone()
if(timeInPDNA != None):
totalTimeInPDNA = timeInPDNA[0]
else:
totalTimeInPDNA = 0
totalTimeInPDNA = timeInPDNA[0]
if(totalTimeInPDNA == None):
totalTimeInPDNA = 0.0
fractionInPDNA = totalTimeInPDNA*1.0/totalTimeAllBanks
result.append(("Time in PDNA (%)", fractionInPDNA*100))
print("{0} {1}".format(result[-1][0],result[-1][1]))
cursor.execute("SELECT SUM(PhaseEnd-PhaseBegin) from Phases where PhaseName = 'PDNP'")
timeInPDNP = cursor.fetchone()
if(timeInPDNP != None):
totalTimeInPDNP = timeInPDNP[0]
else:
totalTimeInPDNP = 0
totalTimeInPDNP = timeInPDNP[0]
if(totalTimeInPDNP == None):
totalTimeInPDNP = 0.0
fractionInPDNP = totalTimeInPDNP*1.0/totalTimeAllBanks
result.append(("Time in PDNP (%)", fractionInPDNP*100))
print("{0} {1}".format(result[-1][0],result[-1][1]))
cursor.execute("SELECT SUM(PhaseEnd-PhaseBegin) from Phases where PhaseName = 'SREF'")
timeInSREF = cursor.fetchone()
if(timeInSREF != None):
totalTimeInSREF = timeInSREF[0]
else:
totalTimeInSREF = 0
totalTimeInSREF = timeInSREF[0]
if(totalTimeInSREF == None):
totalTimeInSREF = 0.0
fractionInSREF = totalTimeInSREF*1.0/totalTimeAllBanks
result.append(("Time in SREF (%)", fractionInSREF*100))
print("{0} {1}".format(result[-1][0],result[-1][1]))
result.insert(0,("Active time (%)", 1-fractionInPDNA-fractionInPDNP-fractionInSREF))
result.insert(0,("Active time (%)", (1-fractionInPDNA-fractionInPDNP-fractionInSREF)*100))
print("{0} {1}".format(result[0][0],result[0][1]))
return result

2
dram/resources/scripts/tests.py
View File

@@ -146,7 +146,9 @@ def row_buffer_is_used_correctly(connection):
cursor.execute(query,{"bank": bankNumber})
rowBufferIsClosed = True
#phases that precharge the bank
prechargingPhases = set(['PRE','PRE_ALL','RDA','WRA'])
#phases that require the bank to be precharged
accessingPhases = set(['RD,RDA,WR,WRA,SREF,AUTO_REFRESH'])
for currentRow in cursor:

5
dram/src/common/TlmRecorder.cpp
View File

@@ -3,6 +3,7 @@
#include "dramExtension.h"
#include "xmlAddressdecoder.h"
#include "Utils.h"
#include "../core/configuration/Configuration.h"
#include <iostream>
using namespace std;
@@ -130,8 +131,8 @@ void TlmRecorder::insertGeneralInfo()
sqlite3_bind_int(insertGeneralInfoStatement, 3,
xmlAddressDecoder::getInstance().getNumberOfBanks());
sqlite3_bind_text(insertGeneralInfoStatement, 4, "", 0, NULL);
sqlite3_bind_int(insertGeneralInfoStatement, 5, 6);
sqlite3_bind_text(insertGeneralInfoStatement, 6, "NS", 2, NULL);
sqlite3_bind_int(insertGeneralInfoStatement, 5, core::Configuration::getInstance().Timings.clk.value());
sqlite3_bind_text(insertGeneralInfoStatement, 6, "PS", 2, NULL);
executeSqlStatement(insertGeneralInfoStatement);
}
void TlmRecorder::insertTransactionInDB(unsigned int id, tlm::tlm_generic_payload& trans)

6
dram/src/core/ControllerCore.cpp
View File

@@ -33,7 +33,9 @@ ControllerCore::ControllerCore(IWrapperConnector& wrapperConnector, std::map<Ban
commandChecker[Command::Precharge] = new PrechargeChecker(config, state);
commandChecker[Command::PrechargeAll] = new PrechargeAllChecker(config, state);
commandChecker[Command::Read] = new ReadChecker(config, state);
commandChecker[Command::ReadA] = commandChecker[Command::Read];
commandChecker[Command::Write] = new WriteChecker(config, state);
commandChecker[Command::WriteA] = commandChecker[Command::Write];
if (config.BankwiseLogic)
{
@@ -134,6 +136,10 @@ bool ControllerCore::isBusy(sc_time time, Bank bank)
{
return (time < lastScheduledCommand.getStart());
}
else if(lastScheduledCommand.commandIsIn({Command::WriteA, Command::ReadA}))
{
return (time < lastScheduledCommand.getEnd());
}
else if (lastScheduledCommand.getCommand() == Command::AutoRefresh)
{
return (time < lastScheduledCommand.getEnd());

4
dram/src/core/configuration/Configuration.cpp
View File

@@ -12,8 +12,8 @@ using namespace std;
namespace core{
string Configuration::memspecUri = "/home/jonny/git/dram/dram/resources/configs/memspecs/MatzesWideIO.xml";
string Configuration::memconfigUri = "/home/jonny/git/dram/dram/resources/configs/memconfigs/memconfig.xml";
string Configuration::memspecUri = "/home/robert/git/dram/dram/resources/configs/memspecs/MatzesWideIO.xml";
string Configuration::memconfigUri = "/home/robert/git/dram/dram/resources/configs/memconfigs/memconfig.xml";
Configuration::Configuration()
{

12
dram/src/core/configuration/TimingConfiguration.h
View File

@@ -30,17 +30,17 @@ struct TimingConfiguration
sc_time tRP; //precharge-time (pre -> act same bank)
sc_time tRAS; //active-time (act -> pre same bank)
sc_time tRC; //RAS-cycle-time (min time bw 2 succesive ACT to same bank)
sc_time tCCD_S; //TODO: relevant? max(bl, tCCD)
sc_time tCCD_L;
sc_time tRRD_S; //min time bw 2 succesive ACT to different banks (different bank group)
sc_time tRRD_L; //.. (same bank group)
sc_time tCCD; //TODO: relevant? max(bl, tCCD)
//sc_time tCCD_L;
sc_time tRRD; //min time bw 2 succesive ACT to different banks (different bank group)
//sc_time tRRD_L; //.. (same bank group)
sc_time tRCD; //act -> read/write
sc_time tNAW; //n activate window
sc_time tRL; //read latency (read command start to data strobe)
sc_time tWL; //write latency
sc_time tWR; //write recovery (write to precharge)
sc_time tWTR_S; //write to read (different bank group)
sc_time tWTR_L; //.. (same bank group)
sc_time tWTR; //write to read (different bank group)
//sc_time tWTR; //.. (same bank group)
sc_time tCKESR; //min time in sref
sc_time tCKE; //min time in pdna or pdnp
sc_time tXP; //min delay to row access command after pdnpx pdnax

2
dram/src/core/powerdown/PowerDownManager.cpp
View File

@@ -210,7 +210,7 @@ void PowerDownManager::sendPowerDownPayload(sc_time time, Bank bank, Command cmd
time = clkAlign(time, controller.config.Timings.clk); //TODO is clkaligned already?
tlm_generic_payload& payload = getPayload(bank);
ScheduledCommand pdn(cmd, time, SC_ZERO_TIME, DramExtension::getExtension(payload));
ScheduledCommand pdn(cmd, time, controller.config.Timings.clk, DramExtension::getExtension(payload));
controller.state.bus.moveCommandToNextFreeSlot(pdn);
controller.state.change(pdn);
controller.wrapper.send(pdn, payload);

4
dram/src/core/powerdown/PowerDownManagerGrouped.cpp
View File

@@ -116,14 +116,14 @@ void PowerDownManagerGrouped::sendPowerDownPayload(sc_time time, Command cmd)
//just to find slot
tlm_generic_payload& payload = getPayload(Bank(0));
ScheduledCommand pdn(cmd, time, SC_ZERO_TIME, DramExtension::getExtension(payload));
ScheduledCommand pdn(cmd, time, controller.config.Timings.clk, DramExtension::getExtension(payload));
controller.state.bus.moveCommandToNextFreeSlot(pdn);
for (Bank bank : controller.getBanks())
{
tlm_generic_payload& payloadToSend = getPayload(bank);
ScheduledCommand pdnToSend(cmd, pdn.getStart(), SC_ZERO_TIME, DramExtension::getExtension(payloadToSend));
ScheduledCommand pdnToSend(cmd, pdn.getStart(), controller.config.Timings.clk, DramExtension::getExtension(payloadToSend));
controller.state.change(pdnToSend);
controller.wrapper.send(pdnToSend, payloadToSend);
}

13
dram/src/core/scheduling/CommandSequenceGenerator.cpp
View File

@@ -7,6 +7,7 @@
#include "CommandSequenceGenerator.h"
#include "../../common/dramExtension.h"
#include "../configuration/Configuration.h"
using namespace std;
@@ -66,14 +67,20 @@ CommandSequence CommandSequenceGenerator::getRowHitCommandSequence(tlm::tlm_gene
Command CommandSequenceGenerator::getReadWriteCommand(tlm::tlm_generic_payload& transaction)
{
if (transaction.get_command() == tlm::TLM_READ_COMMAND)
{
//TODO READA
return Command::Read;
if(Configuration::getInstance().OpenPagePolicy)
return Command::Read;
else
return Command::ReadA;
}
else
{
return Command::Write;
if(Configuration::getInstance().OpenPagePolicy)
return Command::Write;
else
return Command::WriteA;
}
}

2
dram/src/core/scheduling/ScheduledCommand.cpp
View File

@@ -67,7 +67,7 @@ Row ScheduledCommand::getRow() const
return extension.getRow();
}
unsigned int ScheduledCommand::getBurstLength()
unsigned int ScheduledCommand::getBurstLength() const
{
return extension.getBurstlength();
}

2
dram/src/core/scheduling/ScheduledCommand.h
View File

@@ -47,7 +47,7 @@ public:
Bank getBank() const;
Row getRow() const;
unsigned int getBurstLength();
unsigned int getBurstLength() const;
bool operator ==(const ScheduledCommand& b) const;
bool commandIsIn(const std::vector<Command>& commandSet) const;

42
dram/src/core/scheduling/checker/ActivateChecker.cpp
View File

@@ -23,27 +23,32 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
if (lastCommandOnBank.isValidCommand())
{
if (isIn(lastCommandOnBank.getCommand(), { Command::Precharge, Command::PrechargeAll,
Command::AutoRefresh, Command::ReadA, Command::WriteA }))
if (isIn(lastCommandOnBank.getCommand(), { Command::Precharge, Command::AutoRefresh,
Command::ReadA, Command::WriteA }))
{
if (command.getStart() < lastCommandOnBank.getEnd())
{
command.setStart(lastCommandOnBank.getEnd());
}
command.delayToMeetConstraint(lastCommandOnBank.getEnd(), SC_ZERO_TIME);
}
else if (lastCommandOnBank.getCommand() == Command::SREFX ||lastCommandOnBank.getCommand() == Command::PDNPX||lastCommandOnBank.getCommand() == Command::PDNAX)
else if (lastCommandOnBank.getCommand() == Command::PDNPX
|| lastCommandOnBank.getCommand() == Command::PDNAX)
{
command.delayToMeetConstraint(lastCommandOnBank.getEnd(), config.Timings.tXP);
}
else if(lastCommandOnBank.getCommand() == Command::SREFX)
{
command.delayToMeetConstraint(lastCommandOnBank.getEnd(), config.Timings.tXSR);
}
else
reportFatal("Activate Checker", "Activate can not follow " + commandToString(lastCommandOnBank.getCommand()));
reportFatal("Activate Checker",
"Activate can not follow " + commandToString(lastCommandOnBank.getCommand()));
}
delay_to_satisfy_activateToActivate_sameBank(command);
while (!(state.bus.isFree(command.getStart()) && satsfies_activateToActivate_differentBank(command) && satisfies_nActivateWindow(command)))
while (!(state.bus.isFree(command.getStart())
&& satsfies_activateToActivate_differentBank(command)
&& satisfies_nActivateWindow(command)))
{
command.delayStart(config.Timings.clk);
command.delayStart(config.Timings.clk);
}
}
@@ -67,19 +72,18 @@ void ActivateChecker::delay_to_satisfy_activateToActivate_sameBank(ScheduledComm
bool ActivateChecker::satsfies_activateToActivate_differentBank(ScheduledCommand& command) const
{
for(sc_time time : state.lastActivates)
for (sc_time time : state.lastActivates)
{
if((time < command.getStart() && command.getStart()-time<config.Timings.tRRD)
||(command.getStart() <= time && time - command.getStart() < config.Timings.tRRD))
return false;
if ((time < command.getStart() && command.getStart() - time < config.Timings.tRRD)
|| (command.getStart() <= time && time - command.getStart() < config.Timings.tRRD))
return false;
}
return true;
}
bool ActivateChecker::satisfies_nActivateWindow(ScheduledCommand& command) const
{
if(state.lastActivates.size() >= config.nActivate)
if (state.lastActivates.size() >= config.nActivate)
{
set<sc_time> lastActivates = state.lastActivates;
lastActivates.emplace(command.getStart());
@@ -87,9 +91,9 @@ bool ActivateChecker::satisfies_nActivateWindow(ScheduledCommand& command) const
advance(upper, config.nActivate);
auto lower = lastActivates.begin();
while(upper != lastActivates.end())
while (upper != lastActivates.end())
{
if(*upper-*lower < config.Timings.tNAW)
if (*upper - *lower < config.Timings.tNAW)
return false;
++upper;
++lower;

14
dram/src/core/scheduling/checker/PrechargeAllChecker.cpp
View File

@@ -28,13 +28,17 @@ void PrechargeAllChecker::delayToSatisfyConstraints(ScheduledCommand& command) c
{
command.delayToMeetConstraint(lastCommand.getEnd(), config.Timings.tWR);
}
else if (lastCommand.commandIsIn( { Command::PDNAX, Command::PDNPX, Command::SREFX,
else if(lastCommand.getCommand() == Command::WriteA)
{
command.delayToMeetConstraint(lastCommand.getEnd(), SC_ZERO_TIME);
if(config.Timings.tWR > config.Timings.tRP)
command.delayToMeetConstraint(lastCommand.getEnd(), config.Timings.tWR - config.Timings.tRP);
}
else if (lastCommand.commandIsIn( {Command::ReadA, Command::PDNAX, Command::PDNPX, Command::SREFX,
Command::AutoRefresh }))
{
if (command.getStart() < lastCommand.getEnd())
{
command.setStart(lastCommand.getEnd());
}
command.delayToMeetConstraint(lastCommand.getEnd(), SC_ZERO_TIME);
}
else
reportFatal("Precharge All Checker",

2
dram/src/core/scheduling/checker/PrechargeChecker.cpp
View File

@@ -31,7 +31,7 @@ void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand& command) cons
}
else if (lastCommand.getCommand() == Command::PDNAX)
{
command.delayToMeetConstraint(lastCommand.getEnd(), SC_ZERO_TIME);
}
else
reportFatal("Precharge Checker",

27
dram/src/core/scheduling/checker/ReadChecker.cpp
View File

@@ -21,18 +21,14 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
{
if (lastCommand.getCommand() == Command::Activate)
{
if (command.getStart() < lastCommand.getEnd())
{
command.setStart(lastCommand.getEnd());
}
command.delayToMeetConstraint(lastCommand.getEnd(), SC_ZERO_TIME);
}
else if (lastCommand.getCommand() == Command::Read
|| lastCommand.getCommand() == Command::Write)
else if (lastCommand.getCommand() == Command::Read || lastCommand.getCommand() == Command::Write)
{
}
else if (lastCommand.getCommand() == Command::PDNAX)
{
command.delayToMeetConstraint(lastCommand.getEnd(), config.Timings.tXP);
}
else
reportFatal("Read Checker",
@@ -56,8 +52,7 @@ sc_time ReadChecker::getExecutionTime(const tlm::tlm_generic_payload& payload,
}
else
{
return config.Timings.tRL + config.Timings.clk * payload.get_streaming_width()
+ config.Timings.tRP;
return config.Timings.clk * payload.get_streaming_width() + max(config.Timings.tRP,config.Timings.tRL);
}
}
@@ -77,15 +72,7 @@ bool ReadChecker::collidesWithStrobeCommand(ScheduledCommand& read,
{
if (strobeCommand.getCommand() == Command::Read || strobeCommand.getCommand() == Command::ReadA)
{
//read to read
if(read.getStart() < strobeCommand.getStart())
{
return (strobeCommand.getStart() - read.getStart() < read.getBurstLength()*config.Timings.clk);
}
else
{
return (read.getStart() - strobeCommand.getStart() < strobeCommand.getBurstLength()*config.Timings.clk);
}
return getIntervalOnDataStrobe(read).intersects(getIntervalOnDataStrobe(strobeCommand));
}
else if (strobeCommand.getCommand() == Command::Write
|| strobeCommand.getCommand() == Command::WriteA)
@@ -93,12 +80,12 @@ bool ReadChecker::collidesWithStrobeCommand(ScheduledCommand& read,
//read to write
if (strobeCommand.getStart() >= read.getStart())
{
return !(strobeCommand.getStart() >= getIntervalOnDataStrobe(read, config.Timings).end);
return !(strobeCommand.getStart() >= getIntervalOnDataStrobe(read).end);
}
//write to read
else
{
return !(read.getStart()>= getIntervalOnDataStrobe(strobeCommand, config.Timings).end + config.Timings.tWTR);
return !(read.getStart()>= getIntervalOnDataStrobe(strobeCommand).end + config.Timings.tWTR);
}
}
else

32
dram/src/core/scheduling/checker/WriteChecker.cpp
View File

@@ -21,15 +21,16 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
{
if (lastCommand.getCommand() == Command::Activate)
{
if (command.getStart() < lastCommand.getEnd())
{
command.setStart(lastCommand.getEnd());
}
command.delayToMeetConstraint(lastCommand.getEnd(), SC_ZERO_TIME);
}
else if (lastCommand.getCommand() == Command::Read
|| lastCommand.getCommand() == Command::Write
|| lastCommand.getCommand() == Command::PDNAX)
|| lastCommand.getCommand() == Command::Write)
{
}
else if (lastCommand.getCommand() == Command::PDNAX)
{
command.delayToMeetConstraint(lastCommand.getEnd(), config.Timings.tXP);
}
else
reportFatal("Write Checker",
@@ -52,8 +53,7 @@ sc_time WriteChecker::getExecutionTime(const tlm::tlm_generic_payload& payload,
}
else
{
return config.Timings.tWL + config.Timings.clk * (payload.get_streaming_width() - 1)
+ config.Timings.tRP;
return config.Timings.tWL + config.Timings.clk * payload.get_streaming_width() + config.Timings.tWR;
}
}
@@ -74,17 +74,7 @@ bool WriteChecker::collidesWithStrobeCommand(ScheduledCommand& write,
if (strobeCommand.getCommand() == Command::Write
|| strobeCommand.getCommand() == Command::WriteA)
{
//write to write
if (write.getStart() < strobeCommand.getStart())
{
return (strobeCommand.getStart() - write.getStart()
< write.getBurstLength() * config.Timings.clk);
}
else
{
return (write.getStart() - strobeCommand.getStart()
< strobeCommand.getBurstLength() * config.Timings.clk);
}
return getIntervalOnDataStrobe(write).intersects(getIntervalOnDataStrobe(strobeCommand));
}
else if (strobeCommand.getCommand() == Command::Read
|| strobeCommand.getCommand() == Command::ReadA)
@@ -93,13 +83,13 @@ bool WriteChecker::collidesWithStrobeCommand(ScheduledCommand& write,
if (strobeCommand.getStart() >= write.getStart())
{
return !(strobeCommand.getStart()
>= getIntervalOnDataStrobe(write, config.Timings).end + config.Timings.tWTR);
>= getIntervalOnDataStrobe(write).end + config.Timings.tWTR);
}
//read to write
else
{
return !(write.getStart() >= getIntervalOnDataStrobe(strobeCommand, config.Timings).end);
return !(write.getStart() >= getIntervalOnDataStrobe(strobeCommand).end);
}
}
else

27
dram/src/core/utils/Utils.cpp
View File

@@ -9,6 +9,7 @@
#include "../configuration/TimingConfiguration.h"
#include "../ControllerCore.h"
#include "../../common/DebugManager.h"
#include "../configuration/Configuration.h"
namespace core
{
@@ -35,15 +36,22 @@ const sc_time clkAlign(sc_time time, sc_time clk, Alignment alignment)
return floor(time / clk) * clk;
}
TimeInterval getIntervalOnDataStrobe(const ScheduledCommand& command, const TimingConfiguration& config)
TimeInterval getIntervalOnDataStrobe(const ScheduledCommand& command)
{
sc_assert(command.getCommand() == Command::Read || command.getCommand() == Command::ReadA ||
command.getCommand() == Command::Write ||command.getCommand() == Command::WriteA);
if(command.getCommand() == Command::ReadA || command.getCommand() == Command::WriteA)
return TimeInterval(command.getStart(), command.getEnd() - config.tRP);
TimingConfiguration& timings = Configuration::getInstance().Timings;
if(command.getCommand() == Command::Read || command.getCommand() == Command::ReadA)
{
return TimeInterval(command.getStart() + timings.tRL, command.getStart() + timings.tRL + timings.clk * command.getBurstLength());
}
else
return TimeInterval(command.getStart(),command.getEnd());
{
//centered data strobe for write
return TimeInterval(command.getStart() + timings.tWL, command.getStart() + timings.tWL + timings.clk * (command.getBurstLength()-1));
}
}
bool isClkAligned(sc_time time, sc_time clk)
@@ -51,4 +59,15 @@ bool isClkAligned(sc_time time, sc_time clk)
return !((time / clk) - ceil(time / clk));
}
bool TimeInterval::timeIsInInterval(sc_time time)
{
return (start < time && time < end);
}
bool TimeInterval::intersects(TimeInterval other)
{
return other.timeIsInInterval(this->start) || this->timeIsInInterval(other.start);
}
}

10
dram/src/core/utils/Utils.h
View File

@@ -21,19 +21,19 @@ struct TimeInterval
{
sc_time start,end;
TimeInterval(sc_time start,sc_time end) : start(start), end(end){}
bool timeIsInInterval(sc_time time)
{
return (start<=time && time<=end);
}
bool timeIsInInterval(sc_time time);
bool intersects(TimeInterval other);
};
struct TimingConfiguration;
sc_time getDelayToMeetConstraint(sc_time previous, sc_time start, sc_time constraint);
TimeInterval getIntervalOnDataStrobe(const ScheduledCommand& command, const TimingConfiguration& config);
TimeInterval getIntervalOnDataStrobe(const ScheduledCommand& command);
enum Alignment {UP, DOWN};
const sc_time clkAlign(sc_time time, sc_time clk, Alignment alignment = UP);
bool isClkAligned(sc_time time, sc_time clk);
};
#endif /* UTILS_H_ */

16
dram/src/scheduler/Fifo.cpp
View File

@@ -10,27 +10,27 @@
namespace scheduler {
bool scheduler::Fifo::hasTransactionForBank(Bank bank)
bool Fifo::hasTransactionForBank(Bank bank)
{
return (!buffer.at(bank.ID()).empty());
return !buffer[bank].empty();
}
void scheduler::Fifo::schedule(gp* payload)
void Fifo::schedule(gp* payload)
{
buffer.at(DramExtension::getExtension(payload).getBank().ID()).push_back(payload);
buffer[DramExtension::getExtension(payload).getBank()].push_back(payload);
}
gp* scheduler::Fifo::getTransactionForBank(Bank bank)
gp* Fifo::getTransactionForBank(Bank bank)
{
sc_assert(hasTransactionForBank(bank));
gp* result = buffer.at(bank.ID()).front();
gp* result = buffer[bank].front();
return result;
}
void scheduler::Fifo::popTransactionForBank(Bank bank)
void Fifo::popTransactionForBank(Bank bank, gp* payload)
{
sc_assert(hasTransactionForBank(bank));
buffer.at(bank.ID()).pop_front();
buffer[bank].pop_front();
}
} /* namespace scheduler */

9
dram/src/scheduler/Fifo.h
View File

@@ -11,14 +11,15 @@
#include "Scheduler.h"
#include "../core/ControllerCore.h"
#include <deque>
#include <vector>
#include <map>
namespace scheduler {
class Fifo : public Scheduler
{
public:
Fifo(const core::ControllerCore& controller) : buffer(controller.getBanks().size())
Fifo(const core::ControllerCore& controller)
{}
virtual ~Fifo()
{}
@@ -26,10 +27,10 @@ public:
virtual bool hasTransactionForBank(Bank bank) override;
virtual void schedule(gp* payload) override;
virtual gp* getTransactionForBank(Bank bank) override;
virtual void popTransactionForBank(Bank bank) override;
virtual void popTransactionForBank(Bank bank, gp* payload) override;
private:
std::vector<std::deque<gp*>> buffer;
std::map<Bank, std::deque<gp*>> buffer;
};
} /* namespace scheduler */

71
dram/src/scheduler/Fr_Fcfs.cpp
View File

@@ -1,50 +1,73 @@
#include "Fr_Fcfs.h"
#include "../common/dramExtension.h"
#include "../core/configuration/Configuration.h"
#include <algorithm>
using namespace std;
using namespace core;
namespace scheduler {
bool scheduler::FR_FCFS::hasTransactionForBank(Bank bank)
bool FR_FCFS::hasTransactionForBank(Bank bank)
{
return (buffer.at(bank.ID()).size() > 0);
return !buffer[bank].empty();
}
void scheduler::FR_FCFS::schedule(gp* payload)
void FR_FCFS::schedule(gp* payload)
{
buffer.at(DramExtension::getExtension(payload).getBank().ID()).emplace_back(payload);
buffer[DramExtension::getExtension(payload).getBank()].emplace_back(payload);
}
gp* scheduler::FR_FCFS::getTransactionForBank(Bank bank)
gp* FR_FCFS::getTransactionForBank(Bank bank)
{
sc_assert(hasTransactionForBank(bank));
list<gp*>& payloads = buffer.at(bank.ID());
auto found =
find_if(payloads.begin(), payloads.end(),
[&](gp* payload)
{ return DramExtension::getExtension(payload).getRow() == bankstates.getRowInRowBuffer(bank);});
auto rowHits = findRowHits(bank, bankstates.getRowInRowBuffer(bank));
gp* result = rowHits.empty() ? buffer[bank].front() : rowHits.front();
rowHits = findRowHits(bank, DramExtension::getExtension(result).getRow());
if (!core::Configuration::getInstance().AdaptiveOpenPagePolicy)
return result;
if (found != payloads.end())
return *found;
else
return payloads.front();
{
if(rowHits.size() > 1)
Configuration::getInstance().OpenPagePolicy = true;
else
Configuration::getInstance().OpenPagePolicy = false;
//other row hits are still in buffer, leave page open
// if(findRowHits(bank,DramExtension::getExtension(result).getRow()).size() > 1)
// Configuration::getInstance().OpenPagePolicy = true;
// else
// Configuration::getInstance().OpenPagePolicy = false;
//no other hit in buffer, but row miss is waiting
// if(findRowHits(bank,DramExtension::getExtension(result).getRow()).size() == 1 && buffer[bank].size() > 2 )
// Configuration::getInstance().OpenPagePolicy = false;
// else
// Configuration::getInstance().OpenPagePolicy = true;
return result;
}
}
void scheduler::FR_FCFS::popTransactionForBank(Bank bank)
std::vector<gp*> FR_FCFS::findRowHits(Bank bank, Row row)
{
vector<gp*> found;
for (gp* payload : buffer[bank])
{
if (DramExtension::getExtension(payload).getRow() == row)
found.push_back(payload);
}
return found;
}
void FR_FCFS::popTransactionForBank(Bank bank, gp* payload)
{
sc_assert(hasTransactionForBank(bank));
list<gp*>& payloads = buffer.at(bank.ID());
auto found =
find_if(payloads.begin(), payloads.end(),
[&](gp* payload)
{ return DramExtension::getExtension(payload).getRow() == bankstates.getRowInRowBuffer(bank);});
if (found != payloads.end())
payloads.erase(found);
else
payloads.erase(payloads.begin());
buffer[bank].remove(payload);
}
}

9
dram/src/scheduler/Fr_Fcfs.h
View File

@@ -4,14 +4,14 @@
#include "Scheduler.h"
#include "../core/ControllerCore.h"
#include <list>
#include <vector>
#include <map>
namespace scheduler {
class FR_FCFS : public Scheduler
{
public:
FR_FCFS(core::ControllerCore& controller) : bankstates(controller.getBankStates()), buffer(controller.getBanks().size())
FR_FCFS(core::ControllerCore& controller) : bankstates(controller.getBankStates())
{}
virtual ~FR_FCFS()
{}
@@ -19,10 +19,11 @@ public:
virtual bool hasTransactionForBank(Bank bank) override;
virtual void schedule(gp* payload) override;
virtual gp* getTransactionForBank(Bank bank) override;
virtual void popTransactionForBank(Bank bank) override;
virtual void popTransactionForBank(Bank bank, gp* payload) override;
private:
std::vector<std::list<gp*>> buffer;
std::vector<gp*> findRowHits(Bank bank, Row row);
std::map<Bank,std::list<gp*>> buffer;
const core::BankStates& bankstates;
};

2
dram/src/scheduler/Scheduler.h
View File

@@ -17,7 +17,7 @@ public:
//TODO Rename to payload
virtual bool hasTransactionForBank(Bank bank) = 0;
virtual gp* getTransactionForBank(Bank bank) = 0;
virtual void popTransactionForBank(Bank bank) = 0;
virtual void popTransactionForBank(Bank bank, gp* payload) = 0;
};
}

32
dram/src/simulation/Controller.h
View File

@@ -50,7 +50,6 @@ public:
inputBufferDelay = controller->config.Timings.clk;
iSocket.register_nb_transport_bw(this, &Controller::nb_transport_bw);
tSocket.register_nb_transport_fw(this, &Controller::nb_transport_fw);
}
~Controller()
@@ -77,10 +76,18 @@ public:
dramPEQ.notify(payload, BEGIN_RD, command.getStart() - sc_time_stamp());
dramPEQ.notify(payload, END_RD, command.getEnd() - sc_time_stamp());
break;
case Command::ReadA:
dramPEQ.notify(payload, BEGIN_RDA, command.getStart() - sc_time_stamp());
dramPEQ.notify(payload, END_RDA, command.getEnd() - sc_time_stamp());
break;
case Command::Write:
dramPEQ.notify(payload, BEGIN_WR, command.getStart() - sc_time_stamp());
dramPEQ.notify(payload, END_WR, command.getEnd() - sc_time_stamp());
break;
case Command::WriteA:
dramPEQ.notify(payload, BEGIN_WRA, command.getStart() - sc_time_stamp());
dramPEQ.notify(payload, END_WRA, command.getEnd() - sc_time_stamp());
break;
case Command::AutoRefresh:
dramPEQ.notify(payload, BEGIN_AUTO_REFRESH, command.getStart() - sc_time_stamp());
dramPEQ.notify(payload, END_AUTO_REFRESH, command.getEnd() - sc_time_stamp());
@@ -116,7 +123,7 @@ public:
dramPEQ.notify(payload, END_SREF, command.getStart() - sc_time_stamp());
break;
default:
SC_REPORT_FATAL(0, "unsupported command in controller wrapper");
SC_REPORT_FATAL(0, "unsupported command in controller");
break;
}
@@ -155,8 +162,8 @@ private:
void payloadEntersSystem(tlm_generic_payload& payload)
{
printDebugMessage("Transaction enters system");
Bank bank = DramExtension::getExtension(payload).getBank();
printDebugMessage("Transaction enters system on bank " + to_string(bank.ID()));
numberOfPayloadsInSystem[bank] = numberOfPayloadsInSystem[bank] + 1;
scheduler->schedule(&payload);
}
@@ -177,6 +184,12 @@ private:
void scheduleNextPayload(Bank bank)
{
if(bank.ID() == 5)
{
int i = 5;
++i;
}
printDebugMessage("Triggering schedule next payload on bank " + to_string(bank.ID()));
if (scheduler->hasTransactionForBank(bank))
{
@@ -200,7 +213,7 @@ private:
tlm_generic_payload* nextTransaction = scheduler->getTransactionForBank(bank);
if (controller->scheduleRequest(sc_time_stamp(), *nextTransaction))
{
scheduler->popTransactionForBank(bank);
scheduler->popTransactionForBank(bank, nextTransaction);
printDebugMessage("\t-> payload was scheduled by core");
}
else
@@ -266,13 +279,20 @@ private:
scheduleNextPayload(bank);
sendToDram(payload, phase, SC_ZERO_TIME);
}
else if (phase == END_RD || phase == END_WR || phase == END_RDA || phase == END_WRA)
else if (phase == END_RD || phase == END_WR)
{
TlmRecorder::getInstance().recordPhase(payload, BEGIN_RESP, sc_time_stamp());
sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
payloadLeavesSystem(payload);
}
else if (isIn(phase, { BEGIN_ACT, BEGIN_PRE, BEGIN_PRE_ALL }))
else if (phase == END_RDA || phase == END_WRA)
{
TlmRecorder::getInstance().recordPhase(payload, BEGIN_RESP, sc_time_stamp());
sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
payloadLeavesSystem(payload);
scheduleNextPayload(bank);
}
else if (isIn(phase, { BEGIN_ACT, BEGIN_PRE, BEGIN_PRE_ALL, BEGIN_RDA,BEGIN_WRA }))
{
sendToDram(payload, phase, SC_ZERO_TIME);
}

19
dram/src/simulation/SimulationManager.cpp
View File

@@ -19,7 +19,7 @@ namespace simulation {
SimulationManager::SimulationManager(sc_module_name name, std::string stl1,
unsigned int burstlength1, std::string stl2, unsigned int burstlenght2,
std::string traceName, std::string pathToResources) :
std::string traceName, std::string pathToResources, bool silent) :
dram("dram"), arbiter("arbiter"), controller("controller"), player1("player1",
pathToResources + string("traces/") + stl1,burstlength1, this), player2("player2",
pathToResources + string("traces/") + stl2,burstlenght2, this), traceName(traceName)
@@ -37,13 +37,16 @@ SimulationManager::SimulationManager(sc_module_name name, std::string stl1,
controller.iSocket.bind(dram.tSocket);
vector<string> whiteList;
whiteList.push_back(controller.name());
whiteList.push_back(player2.name());
whiteList.push_back(player1.name());
whiteList.push_back(this->name());
whiteList.push_back(TlmRecorder::senderName);
whiteList.push_back(ControllerCore::senderName);
whiteList.push_back(PowerDownManager::senderName);
if(!silent)
{
whiteList.push_back(controller.name());
whiteList.push_back(player2.name());
whiteList.push_back(player1.name());
whiteList.push_back(this->name());
whiteList.push_back(TlmRecorder::senderName);
whiteList.push_back(ControllerCore::senderName);
whiteList.push_back(PowerDownManager::senderName);
}
DebugManager::getInstance().addToWhiteList(whiteList);
}

2
dram/src/simulation/SimulationManager.h
View File

@@ -24,7 +24,7 @@ public:
SC_HAS_PROCESS(SimulationManager);
SimulationManager(sc_module_name name, std::string stl1,
unsigned int burstlength1, std::string stl2, unsigned int burstlenght2,
std::string traceName, std::string pathToResources);
std::string traceName, std::string pathToResources, bool silent=false);
void startSimulation();
void tracePlayerFinishedCallback(string name) override;

6
dram/src/simulation/main.cpp
View File

@@ -26,15 +26,15 @@ void startTraceAnalyzer(string traceName)
int sc_main(int argc, char **argv)
{
sc_set_time_resolution(1, SC_NS);
sc_set_time_resolution(1, SC_PS);
string resources = pathOfFile(argv[0]) + string("/../resources/");
string stl1 = "chstone-mips_32.stl";
string stl1 = "chstone-sha_32.stl";
unsigned int burstlength1 = 4;
string stl2 = "empty.stl";
unsigned int burstlength2 = 2;
string traceName = "tpr.tdb";
SimulationManager simulationManager("sim", stl1,burstlength1, stl2,burstlength2, traceName, resources);
SimulationManager simulationManager("sim", stl1,burstlength1, stl2,burstlength2, traceName, resources,false);
simulationManager.startSimulation();
startTraceAnalyzer(traceName);
return 0;