Correct bandwidth calculation, move Trace Analyzer to top of readme.
This commit is contained in:
@@ -60,35 +60,35 @@ public:
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/ Configuration::getInstance().memSpec->dataRate
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* Configuration::getInstance().memSpec->tCK;
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double bandwidth = (activeTime / sc_time_stamp() * 100);
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double bandwidthWoIdle = ((activeTime) / (sc_time_stamp() - idleTimeCollector.getIdleTime()) * 100);
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double bandwidth = activeTime / sc_time_stamp();
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double bandwidthWoIdle = activeTime / (sc_time_stamp() - idleTimeCollector.getIdleTime());
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double maxBandwidth = (
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// fCK in Mhz e.g. 800 [MHz]:
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(1000000 / Configuration::getInstance().memSpec->tCK.to_double())
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// fCK in GHz e.g. 1 [GHz] (tCK in ps):
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(1000 / Configuration::getInstance().memSpec->tCK.to_double())
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// DataRate e.g. 2
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* Configuration::getInstance().memSpec->dataRate
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// BusWidth e.g. 8 or 64
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* Configuration::getInstance().memSpec->bitWidth
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// Number of devices on a DIMM e.g. 8
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* Configuration::getInstance().memSpec->numberOfDevicesOnDIMM ) / ( 1024 );
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* Configuration::getInstance().memSpec->numberOfDevicesOnDIMM );
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std::cout << name() << std::string(" Total Time: ")
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<< sc_time_stamp().to_string()
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<< std::endl;
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std::cout << name() << std::string(" AVG BW: ")
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<< std::fixed << std::setprecision(2)
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<< ((bandwidth / 100) * maxBandwidth)
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<< " Gibit/s (" << bandwidth << " %)"
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<< (bandwidth * maxBandwidth)
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<< " Gb/s (" << (bandwidth * 100) << " %)"
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<< std::endl;
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std::cout << name() << std::string(" AVG BW\\IDLE: ")
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<< std::fixed << std::setprecision(2)
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<< ((bandwidthWoIdle / 100) * maxBandwidth)
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<< " Gibit/s (" << bandwidthWoIdle << " %)"
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<< (bandwidthWoIdle * maxBandwidth)
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<< " Gb/s (" << (bandwidthWoIdle * 100) << " %)"
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<< endl;
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std::cout << name() << std::string(" MAX BW: ")
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<< std::fixed << std::setprecision(2)
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<< maxBandwidth << " Gibit/s"
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<< maxBandwidth << " Gb/s"
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<< std::endl;
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}
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26
README.md
26
README.md
@@ -31,6 +31,18 @@ A UML diagram of the software architecture is presented below; different compone
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<img src="DRAMSys/docs/images/dramsys_uml.png" alt="UML" />
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## Trace Analyzer Consulting and Custom-Tailored Modifications
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To provide better analysis capabilities for DRAM subsystem design space exploration than the usual performance-related outputs to the console, DRAMSys offers the Trace Analyzer.
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All requests, responses and DRAM commands can be recorded in an SQLite trace database during a simulation and visualized with the tool afterwards. An evaluation of the trace databases can be performed with the powerful Python interface of the Trace Analyzer. Different metrics are described as SQL statements and formulas in Python, which can be customized or extended without recompilation.
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The Trace Analyzer's main window is shown below.
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If you are interested in the database recording feature and the Trace Analyzer, if you need support on how to setup DRAMSys in a virtual platform of your company, or if you require custom modifications of the simulator please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de).
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## Basic Setup
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Start using DRAMSys by cloning the repository.
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@@ -342,7 +354,7 @@ An example follows.
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## DRAMSys with Thermal Simulation
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The thermal simulation is performed by a **3D-ICE** [8] server accessed through the network. Therefore users interested in thermal simulation during their DRAMSys simulations need to make sure they have a 3D-ICE server up and running before starting. For more information about 3D-ICE visit the [official website](https://www.epfl.ch/labs/esl/open-source-software-projects/3d-ice/).
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The thermal simulation is performed by a **3D-ICE** [8] server accessed through the network. Therefore users interested in thermal simulation during their DRAMSys simulations need to make sure they have a 3D-ICE server up and running before starting. For more information about 3D-ICE visit the [official website](https://www.epfl.ch/labs/esl/open-source-software-projects/3d-ice/). An example video that visualizes the results of a thermal simulation is provided on [Youtube](https://www.youtube.com/watch?v=Eacsq71hHtY).
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#### Installing 3D-ICE
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@@ -506,18 +518,6 @@ The content of [config.json](DRAMSys/library/resources/configs/thermalsim/config
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- true: generate power map files during thermal simulation
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- false: do not generate power map files during thermal simulation
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## Trace Analyzer Consulting and Custom-Tailored Modifications
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To provide better analysis capabilities for DRAM subsystem design space exploration than the usual performance-related outputs to the console, DRAMSys offers the Trace Analyzer.
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All requests, responses and DRAM commands can be recorded in an SQLite trace database during a simulation and visualized with the tool afterwards. An evaluation of the trace databases can be performed with the powerful Python interface of the Trace Analyzer. Different metrics are described as SQL statements and formulas in Python, which can be customized or extended without recompilation.
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The Trace Analyzer's main window is shown below.
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If you are interested in the database recording feature and the Trace Analyzer, if you need support on how to setup DRAMSys in a virtual platform of your company, or if you require custom modifications of the simulator please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de).
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## Acknowledgements
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The development of DRAMSys was supported by the German Research Foundation (DFG) as part of the priority program [Dependable Embedded Systems SPP1500](http://spp1500.itec.kit.edu) and the DFG grant no. [WE2442/10-1](https://www.uni-kl.de/en/3d-dram/). Furthermore, it was supported within the Fraunhofer and DFG cooperation program (grant no. [WE2442/14-1](https://www.iese.fraunhofer.de/en/innovation_trends/autonomous-systems/memtonomy.html)) and by the [Fraunhofer High Performance Center for Simulation- and Software-Based Innovation](https://www.leistungszentrum-simulation-software.de/en.html). Special thanks go to all listed contributors for their work and commitment during seven years of development.
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