Readme file updated

This commit is contained in:
Éder Ferreira Zulian
2015-05-21 17:03:25 +02:00
parent 30661b607b
commit 14deacd665

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@@ -132,14 +132,14 @@ Below are listed the configuration sections and configuration fields.
- **Simulator configuration**
- *Debug* (boolean)
- "1": Enables debug output on console
- "0": Disables debug output
- "1": enables debug output on console
- "0": disables debug output
- *DatabaseRecording* (boolean)
- "1": Enables trace file recording for the trace analyser tool
- "0": Disables trace file recording
- "1": enables trace file recording for the trace analyser tool
- "0": disables trace file recording
- *PowerAnalysis* (boolean)
- "1": Enables live power analysis with the DRAMPower tool
- "0": Disables power analysis
- "1": enables live power analysis with the DRAMPower tool
- "0": disables power analysis
- **Memory specification**
@@ -150,6 +150,9 @@ Below are listed the configuration sections and configuration fields.
XML files describe the address mapping to be used in the simulation.
The file [am_wideio.xml](dram/resources/configs/amconfigs/am_wideio.xml) is
a good example.
```
<addressmapping>
<channel from="27" to="28"/>
@@ -161,7 +164,8 @@ Below are listed the configuration sections and configuration fields.
```
![Address Mapping Sample 1](docs/images/am_sample1.png)
![Address Mapping Sample 1 SVG](docs/images/am_sample1.svg)
![Address Mapping Sample 1 svg file](docs/images/am_sample1.svg)
```
<addressmapping>
@@ -174,23 +178,73 @@ Below are listed the configuration sections and configuration fields.
```
![Address Mapping Sample 2](docs/images/am_sample2.png)
![Address Mapping Sample 2 SVG](docs/images/am_sample2.svg)
![Address Mapping Sample 2 svg file](docs/images/am_sample2.svg)
- **Memory Configuration**
The content of [fifo.xml](dram/resources/configs/memconfigs/fifo.xml) is
presented below as an example.
```
<memconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1"/>
<MaxNrOfTransactions value="8"/>
<Scheduler value="FR_FCFS"/>
<Capsize value="5"/>
<PowerDownMode value="TimeoutSREF"/>
<PowerDownTimeout value="100"/>
<!-- Error Modelling -->
<ErrorChipSeed value="42"/>
<ErrorCSVFile value="../src/error/error_new.csv"/>
<ErrorStoreMode value="NoStorage"/>
</memconfig>
```
- *BankwiseLogic* (boolean)
- "1": perform bankwise operations such as refresh and powerdown
- "0": do not perform bankwise operations
- *OpenPagePolicy* (boolean)
- "1": use open page precharge policy
- "0": do not use open page precharge policy
- *MaxNrOfTransactions* (unsigned int)
- Maximum number of transactions.
- *Scheduler* (string)
- Scheduler algorithm to be applied on memory transactions. Different
schedulers can order transactions based on different factors such as
latency, power savings, etc.
- *Capsize* (unsigned int)
- Capacitor cell size.
- *PowerDownMode* (enum EPowerDownMode)
- "NoPowerDown": no power down mode (active idle)
- "Staggered": staggered power down policy
- "TimeoutPDN": precharge idle
- "TimeoutSREF": self refresh
- *Buswidth* (unsigned int)
- Bus width in bits.
- *ReadWriteGrouping* (boolean)
- "1":
- "0":
- *ReorderBuffer* (boolean)
- "1":
- "0":
- *ErrorChipSeed* (unsigned int)
- Seed to initialize the random error generator.
- *ErrorCSVFile* (string)
- CSV file with error injection information.
- *ErrorStoreMode* (enum ErrorStorageMode)
- "NoStorage": no storage
- "Store": store data without error model
- "ErrorModel": store data with error model
- **Trace setups**
<tracesetup id="fifo">
<device clkMhz="200">voco2.stl</device>
- *id*
- *clkMhz*
Some attributes are self-explanatory while others require some previous
knowhow of memory technologies or some knowledge of the simulator source code.
## DRAMSys Resources
Some resources of the simulator are available in the **resources** directory
its sub-directories.