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This commit is contained in:
Janik Schlemminger
2014-04-08 10:46:38 +02:00
parent 6fdfcf402e c1841e4102
commit 131c5dff41
51 changed files with 5117 additions and 240 deletions
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2
dram/.settings/language.settings.xml
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@@ -4,7 +4,7 @@
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-2055719358" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot; -std=c++11">
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-64906255729110141" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} -E -P -v -dD &quot;${INPUTS}&quot; -std=c++11">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>

8
dram/resources/configs/memconfigs/memconfig.xml Normal file
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@@ -0,0 +1,8 @@
<memspec>
<memconfig>
<parameter id="bankwiseRefresh" type="bool" value="0" />
<parameter id="bankwisePowerDown" type="bool" value="0" />
<parameter id="openPagePolicy" type="bool" value="1" />
<parameter id="adaptiveOpenPagePolicy" type="bool" value="1" />
</memconfig>
</memspec>

66
dram/resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-200_128bit.xml Normal file
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@@ -0,0 +1,66 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="JEDEC_256Mb_WIDEIO_SDR-200_128bit" />
<parameter id="memoryType" type="string" value="WIDEIO_SDR" />
<memarchitecturespec>
<parameter id="width" type="uint" value="128" />
<parameter id="nbrOfBanks" type="uint" value="4" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="128" />
<parameter id="nbrOfRows" type="uint" value="2048" />
<parameter id="dataRate" type="uint" value="1" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="200" />
<parameter id="RC" type="uint" value="12" />
<parameter id="RCD" type="uint" value="4" />
<parameter id="RL" type="uint" value="3" />
<parameter id="RP" type="uint" value="4" />
<parameter id="RFC" type="uint" value="18" />
<parameter id="RAS" type="uint" value="9" />
<parameter id="WL" type="uint" value="1" />
<parameter id="AL" type="uint" value="0" />
<parameter id="DQSCK" type="uint" value="1" />
<parameter id="RTP" type="uint" value="4" />
<parameter id="WR" type="uint" value="3" />
<parameter id="XP" type="uint" value="2" />
<parameter id="XPDLL" type="uint" value="2" />
<parameter id="XS" type="uint" value="20" />
<parameter id="XSDLL" type="uint" value="20" />
<parameter id="REFI" type="uint" value="3120" />
<parameter id="CL" type="uint" value="3" />
<parameter id="TAW" type="uint" value="10" />
<parameter id="RRD" type="uint" value="2" />
<parameter id="CCD" type="uint" value="1" />
<parameter id="WTR" type="uint" value="4" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="CKESR" type="uint" value="3" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="5.88" />
<parameter id="idd02" type="double" value="21.18" />
<parameter id="idd2p0" type="double" value="0.05" />
<parameter id="idd2p02" type="double" value="0.17" />
<parameter id="idd2p1" type="double" value="0.05" />
<parameter id="idd2p12" type="double" value="0.17" />
<parameter id="idd2n" type="double" value="0.13" />
<parameter id="idd2n2" type="double" value="4.04" />
<parameter id="idd3p0" type="double" value="0.25" />
<parameter id="idd3p02" type="double" value="1.49" />
<parameter id="idd3p1" type="double" value="0.25" />
<parameter id="idd3p12" type="double" value="1.49" />
<parameter id="idd3n" type="double" value="0.52" />
<parameter id="idd3n2" type="double" value="6.55" />
<parameter id="idd4r" type="double" value="1.41" />
<parameter id="idd4r2" type="double" value="85.73" />
<parameter id="idd4w" type="double" value="1.42" />
<parameter id="idd4w2" type="double" value="60.79" />
<parameter id="idd5" type="double" value="14.43" />
<parameter id="idd52" type="double" value="48.17" />
<parameter id="idd6" type="double" value="0.07" />
<parameter id="idd62" type="double" value="0.27" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.2" />
</mempowerspec>
</memspec>

67
dram/resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-266_128bit.xml Normal file
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@@ -0,0 +1,67 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="JEDEC_256Mb_WIDEIO_SDR-266_128bit" />
<parameter id="memoryType" type="string" value="WIDEIO_SDR" />
<memarchitecturespec>
<parameter id="width" type="uint" value="128" />
<parameter id="nbrOfBanks" type="uint" value="4" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="128" />
<parameter id="nbrOfRows" type="uint" value="2048" />
<parameter id="dataRate" type="uint" value="1" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="266" />
<parameter id="RC" type="uint" value="16" />
<parameter id="RCD" type="uint" value="5" />
<parameter id="RL" type="uint" value="3" />
<parameter id="RP" type="uint" value="5" />
<parameter id="RFC" type="uint" value="24" />
<parameter id="RAS" type="uint" value="12" />
<parameter id="WL" type="uint" value="1" />
<parameter id="AL" type="uint" value="0" />
<parameter id="DQSCK" type="uint" value="1" />
<parameter id="RTP" type="uint" value="4" />
<parameter id="WR" type="uint" value="4" />
<parameter id="XP" type="uint" value="3" />
<parameter id="XPDLL" type="uint" value="3" />
<parameter id="XS" type="uint" value="27" />
<parameter id="XSDLL" type="uint" value="27" />
<parameter id="REFI" type="uint" value="3120" />
<parameter id="CL" type="uint" value="3" />
<parameter id="TAW" type="uint" value="14" />
<parameter id="RRD" type="uint" value="3" />
<parameter id="CCD" type="uint" value="1" />
<parameter id="WTR" type="uint" value="6" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="CKESR" type="uint" value="6" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="6.06" />
<parameter id="idd02" type="double" value="21.82" />
<parameter id="idd2p0" type="double" value="0.05" />
<parameter id="idd2p02" type="double" value="0.17" />
<parameter id="idd2p1" type="double" value="0.05" />
<parameter id="idd2p12" type="double" value="0.17" />
<parameter id="idd2n" type="double" value="0.16" />
<parameter id="idd2n2" type="double" value="4.76" />
<parameter id="idd3p0" type="double" value="0.25" />
<parameter id="idd3p02" type="double" value="1.49" />
<parameter id="idd3p1" type="double" value="0.25" />
<parameter id="idd3p12" type="double" value="1.49" />
<parameter id="idd3n" type="double" value="0.58" />
<parameter id="idd3n2" type="double" value="7.24" />
<parameter id="idd4r" type="double" value="1.82" />
<parameter id="idd4r2" type="double" value="111.22" />
<parameter id="idd4w" type="double" value="1.82" />
<parameter id="idd4w2" type="double" value="78.0" />
<parameter id="idd5" type="double" value="14.48" />
<parameter id="idd52" type="double" value="48.34" />
<parameter id="idd6" type="double" value="0.07" />
<parameter id="idd62" type="double" value="0.27" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.2" />
</mempowerspec>
</memspec>

62
dram/resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.xml Normal file
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@@ -0,0 +1,62 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="MICRON_4Gb_DDR4-1866_8bit_A" />
<parameter id="memoryType" type="string" value="DDR4" />
<memarchitecturespec>
<parameter id="width" type="uint" value="8" />
<parameter id="nbrOfBankGroups" type="uint" value="4" />
<parameter id="nbrOfBanks" type="uint" value="16" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="32768" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="8" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="933" />
<parameter id="REFI" type="uint" value="3644" />
<parameter id="RFC" type="uint" value="243" />
<parameter id="RL" type="uint" value="13" />
<parameter id="WL" type="uint" value="12" />
<parameter id="CL" type="uint" value="13" />
<parameter id="AL" type="uint" value="0" />
<parameter id="RP" type="uint" value="13" />
<parameter id="RAS" type="uint" value="32" />
<parameter id="RCD" type="uint" value="13" />
<parameter id="RC" type="uint" value="45" />
<parameter id="FAW" type="uint" value="22" />
<parameter id="RTP" type="uint" value="8" />
<parameter id="WR" type="uint" value="14" />
<parameter id="RRD_S" type="uint" value="4" />
<parameter id="RRD_L" type="uint" value="5" />
<parameter id="CCD_S" type="uint" value="4" />
<parameter id="CCD_L" type="uint" value="5" />
<parameter id="WTR_S" type="uint" value="3" />
<parameter id="WTR_L" type="uint" value="7" />
<parameter id="DQSCK" type="uint" value="2" />
<parameter id="XP" type="uint" value="8" />
<parameter id="XPDLL" type="uint" value="255" />
<parameter id="XS" type="uint" value="252" />
<parameter id="XSDLL" type="uint" value="512" />
<parameter id="CKE" type="uint" value="6" />
<parameter id="CKESR" type="uint" value="7" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="56.25" />
<parameter id="idd02" type="double" value="4.05" />
<parameter id="idd2p0" type="double" value="17.0" />
<parameter id="idd2p1" type="double" value="17.0" />
<parameter id="idd2n" type="double" value="33.75" />
<parameter id="idd3p0" type="double" value="22.5" />
<parameter id="idd3p1" type="double" value="22.5" />
<parameter id="idd3n" type="double" value="39.5" />
<parameter id="idd4r" type="double" value="157.5" />
<parameter id="idd4w" type="double" value="135.0" />
<parameter id="idd5" type="double" value="118.0" />
<parameter id="idd6" type="double" value="20.25" />
<parameter id="idd62" type="double" value="2.6" />
<parameter id="vdd" type="double" value="1.2" />
<parameter id="vdd2" type="double" value="2.5" />
</mempowerspec>
</memspec>

62
dram/resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.xml Normal file
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@@ -0,0 +1,62 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="MICRON_4Gb_DDR4-2400_8bit_A" />
<parameter id="memoryType" type="string" value="DDR4" />
<memarchitecturespec>
<parameter id="width" type="uint" value="8" />
<parameter id="nbrOfBankGroups" type="uint" value="4" />
<parameter id="nbrOfBanks" type="uint" value="16" />
<parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="1024" />
<parameter id="nbrOfRows" type="uint" value="32768" />
<parameter id="dataRate" type="uint" value="2" />
<parameter id="burstLength" type="uint" value="8" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="1200" />
<parameter id="REFI" type="uint" value="4680" />
<parameter id="RFC" type="uint" value="313" />
<parameter id="RL" type="uint" value="16" />
<parameter id="WL" type="uint" value="16" />
<parameter id="CL" type="uint" value="16" />
<parameter id="AL" type="uint" value="0" />
<parameter id="RP" type="uint" value="16" />
<parameter id="RAS" type="uint" value="39" />
<parameter id="RCD" type="uint" value="16" />
<parameter id="RC" type="uint" value="55" />
<parameter id="FAW" type="uint" value="26" />
<parameter id="RTP" type="uint" value="12" />
<parameter id="WR" type="uint" value="18" />
<parameter id="RRD_S" type="uint" value="4" />
<parameter id="RRD_L" type="uint" value="6" />
<parameter id="CCD_S" type="uint" value="4" />
<parameter id="CCD_L" type="uint" value="6" />
<parameter id="WTR_S" type="uint" value="3" />
<parameter id="WTR_L" type="uint" value="9" />
<parameter id="DQSCK" type="uint" value="2" />
<parameter id="XP" type="uint" value="8" />
<parameter id="XPDLL" type="uint" value="325" />
<parameter id="XS" type="uint" value="324" />
<parameter id="XSDLL" type="uint" value="512" />
<parameter id="CKE" type="uint" value="6" />
<parameter id="CKESR" type="uint" value="7" />
</memtimingspec>
<mempowerspec>
<parameter id="idd0" type="double" value="60.75" />
<parameter id="idd02" type="double" value="4.05" />
<parameter id="idd2p0" type="double" value="17.0" />
<parameter id="idd2p1" type="double" value="17.0" />
<parameter id="idd2n" type="double" value="38.25" />
<parameter id="idd3p0" type="double" value="22.5" />
<parameter id="idd3p1" type="double" value="22.5" />
<parameter id="idd3n" type="double" value="44.0" />
<parameter id="idd4r" type="double" value="184.5" />
<parameter id="idd4w" type="double" value="168.75" />
<parameter id="idd5" type="double" value="118.0" />
<parameter id="idd6" type="double" value="20.25" />
<parameter id="idd62" type="double" value="2.6" />
<parameter id="vdd" type="double" value="1.2" />
<parameter id="vdd2" type="double" value="2.5" />
</mempowerspec>
</memspec>

66
dram/resources/configs/memspecs/MatzesWideIO.xml Normal file
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@@ -0,0 +1,66 @@
<!DOCTYPE memspec SYSTEM "memspec.dtd">
<memspec>
<parameter id="memoryId" type="string" value="JEDEC_256Mb_WIDEIO_SDR-200_128bit" />
<parameter id="memoryType" type="string" value="WIDEIO_SDR" />
<memarchitecturespec>
<parameter id="width" type="uint" value="128" />
<parameter id="nbrOfBanks" type="uint" value="8" />
<!-- <parameter id="nbrOfRanks" type="uint" value="1" />
<parameter id="nbrOfColumns" type="uint" value="128" />-->
<parameter id="nbrOfRows" type="uint" value="2048" />
<parameter id="dataRate" type="uint" value="1" />
<parameter id="burstLength" type="uint" value="4" />
</memarchitecturespec>
<memtimingspec>
<parameter id="clkMhz" type="double" value="166" />
<parameter id="RC" type="uint" value="9" /><!--tRP+tRAS-->
<parameter id="RCD" type="uint" value="3" />
<parameter id="RL" type="uint" value="3" />
<parameter id="RP" type="uint" value="3" />
<parameter id="RFC" type="uint" value="22" />
<parameter id="RAS" type="uint" value="6" />
<parameter id="WL" type="uint" value="1" />
<parameter id="AL" type="uint" value="0" />
<!--<parameter id="DQSCK" type="uint" value="1" />
<parameter id="RTP" type="uint" value="4" />-->
<parameter id="WR" type="uint" value="2" />
<parameter id="XP" type="uint" value="2" />
<!--<parameter id="XPDLL" type="uint" value="2" />-->
<parameter id="XS" type="uint" value="24" /><!--tRFC+2clk-->
<!--<parameter id="XSDLL" type="uint" value="20" />-->
<parameter id="REFI" type="uint" value="3120" />
<!--<parameter id="CL" type="uint" value="3" />-->
<parameter id="TAW" type="uint" value="10" />
<parameter id="RRD" type="uint" value="2" />
<!--<parameter id="CCD" type="uint" value="1" />-->
<parameter id="WTR" type="uint" value="3" />
<parameter id="CKE" type="uint" value="3" />
<parameter id="CKESR" type="uint" value="3" />
</memtimingspec>
<mempowerspec>
<!-- <parameter id="idd0" type="double" value="5.88" />
<parameter id="idd02" type="double" value="21.18" />
<parameter id="idd2p0" type="double" value="0.05" />
<parameter id="idd2p02" type="double" value="0.17" />
<parameter id="idd2p1" type="double" value="0.05" />
<parameter id="idd2p12" type="double" value="0.17" />
<parameter id="idd2n" type="double" value="0.13" />
<parameter id="idd2n2" type="double" value="4.04" />
<parameter id="idd3p0" type="double" value="0.25" />
<parameter id="idd3p02" type="double" value="1.49" />
<parameter id="idd3p1" type="double" value="0.25" />
<parameter id="idd3p12" type="double" value="1.49" />
<parameter id="idd3n" type="double" value="0.52" />
<parameter id="idd3n2" type="double" value="6.55" />
<parameter id="idd4r" type="double" value="1.41" />
<parameter id="idd4r2" type="double" value="85.73" />
<parameter id="idd4w" type="double" value="1.42" />
<parameter id="idd4w2" type="double" value="60.79" />
<parameter id="idd5" type="double" value="14.43" />
<parameter id="idd52" type="double" value="48.17" />
<parameter id="idd6" type="double" value="0.07" />
<parameter id="idd62" type="double" value="0.27" />
<parameter id="vdd" type="double" value="1.8" />
<parameter id="vdd2" type="double" value="1.2" />-->
</mempowerspec>
</memspec>

1
dram/resources/scripts/createTraceDB.sql
View File

@@ -43,6 +43,7 @@ CREATE TABLE Transactions(
ID INTEGER PRIMARY KEY,
Range INTEGER,
Address INTEGER,
Burstlength INTEGER,
TThread INTEGER,
TChannel INTEGER,
TBank INTEGER,

58
dram/resources/scripts/metrics.py
View File

@@ -26,6 +26,11 @@ def getNumberOfBanks(connection):
result = cursor.fetchone()
return result[0]
def getTraceLength(connection):
cursor = connection.cursor()
cursor.execute("SELECT TraceEnd FROM GeneralInfo")
result = cursor.fetchone()
return result[0]
@metric
def average_response_latency_in_ns(connection):
@@ -60,6 +65,46 @@ def number_of_precharges(connection):
result = cursor.fetchone()
return result[0]
def timeInPowerStates(connection):
totalTimeAllBanks = getTraceLength(connection)*getNumberOfBanks(connection)
cursor = connection.cursor()
result = []
cursor.execute("SELECT SUM(PhaseEnd-PhaseBegin) from Phases where PhaseName = 'PDNA'")
timeInPDNA = cursor.fetchone()
if(timeInPDNA != None):
totalTimeInPDNA = timeInPDNA[0]
else:
totalTimeInPDNA = 0
fractionInPDNA = totalTimeInPDNA*1.0/totalTimeAllBanks
result.append(("Time in PDNA (%)", fractionInPDNA*100))
print("{0} {1}".format(result[-1][0],result[-1][1]))
cursor.execute("SELECT SUM(PhaseEnd-PhaseBegin) from Phases where PhaseName = 'PDNP'")
timeInPDNP = cursor.fetchone()
if(timeInPDNP != None):
totalTimeInPDNP = timeInPDNP[0]
else:
totalTimeInPDNP = 0
fractionInPDNP = totalTimeInPDNP*1.0/totalTimeAllBanks
result.append(("Time in PDNP (%)", fractionInPDNP*100))
print("{0} {1}".format(result[-1][0],result[-1][1]))
cursor.execute("SELECT SUM(PhaseEnd-PhaseBegin) from Phases where PhaseName = 'SREF'")
timeInSREF = cursor.fetchone()
if(timeInSREF != None):
totalTimeInSREF = timeInSREF[0]
else:
totalTimeInSREF = 0
fractionInSREF = totalTimeInSREF*1.0/totalTimeAllBanks
result.append(("Time in SREF (%)", fractionInSREF*100))
print("{0} {1}".format(result[-1][0],result[-1][1]))
result.insert(0,("Active time (%)", 1-fractionInPDNA-fractionInPDNP-fractionInSREF))
print("{0} {1}".format(result[0][0],result[0][1]))
return result
def passRatio(connection):
numberOfPassWins = {}
@@ -95,9 +140,14 @@ def passRatio(connection):
result = []
for thread in getThreads(connection):
print("Thread {0} passed other threads {1} times and was passed {2} times. Ratio is {3}".format
(thread, numberOfPassWins[thread], numberOfPassLosses[thread], numberOfPassWins[thread]*1.0/(numberOfPassWins[thread]+numberOfPassLosses[thread])))
result.append(("Thread {0} pass ratio".format(thread), numberOfPassWins[thread]*1.0/(numberOfPassWins[thread]+numberOfPassLosses[thread])))
totalPassedInvolved = numberOfPassWins[thread]+numberOfPassLosses[thread]
if(totalPassedInvolved > 0):
passRatio = numberOfPassWins[thread]*1.0/(numberOfPassWins[thread]+numberOfPassLosses[thread])
else:
passRatio = 0.5
print("Thread {0} passed other threads {1} times and was passed {2} times. Pass ratio is {3}".format
(thread, numberOfPassWins[thread], numberOfPassLosses[thread],passRatio))
result.append(("Thread {0} pass ratio".format(thread), passRatio))
return result
@@ -122,7 +172,7 @@ def calculateMetrics(pathToTrace):
calculatedMetrics.append(res)
calculatedMetrics.extend(passRatio(connection))
calculatedMetrics.extend(timeInPowerStates(connection))
connection.close()
return calculatedMetrics

79
dram/resources/scripts/tests.py
View File

@@ -7,10 +7,11 @@ class DramConfig(object):
unitOfTime = "ns"
nActivateWindow = 0
burstLengtht = 2
clk = numberOfBanks = 0
tRP = tRAS = tRC = tRRD = tRCD = tTAW = tRL = tWL = tWTR = tRFC = tWR = 0
tReadLength = tWriteLength = 0
bankwiseRefresh = False
bankwisePowerdown = False
def clkAlign(self, value):
return math.ceil(1.0*value/self.clk)*self.clk
@@ -32,15 +33,21 @@ class DramConfig(object):
self.tWR = 2*self.clk
self.tTAW = self.clkAlign(50)
self.tRFC = self.clkAlign(130)
self.tReadLength = self.tRL + self.burstLength * self.clk
self.tWriteLength = self.tWL + (self.burstLength - 1) *self.clk
self.tCKESR = self.clkAlign(max(3*self.clk, 15))
def __init__(self):
self.parseFromXml()
dramconfig = DramConfig()
def calculateReadLength(burstLength):
return dramconfig.tRL + burstLength * dramconfig.clk
def calculateWriteLength(burstLength):
return dramconfig.tWL + burstLength * dramconfig.clk
# ----------- test utils ---------------------------------------
@@ -88,11 +95,23 @@ def commands_are_clockaligned(connection):
def commandbus_slots_are_used_once(connection):
"""Checks that no two phases on the command bus start at the same time"""
cursor = connection.cursor()
cursor.execute("SELECT PhaseBegin,count FROM (SELECT phaseBegin,count(phasebegin) AS count FROM Phases WHERE PhaseName NOT IN ('RESP','REQ') GROUP BY phaseBegin) WHERE count>1")
result = cursor.fetchone()
if dramconfig.bankwisePowerdown and dramconfig.bankwiseRefresh:
excludedPhases = "('REQ','RESP','PRE_ALL')"
elif (not dramconfig.bankwisePowerdown and dramconfig.bankwiseRefresh):
excludedPhases = "('REQ','RESP','PRE_ALL','PDNA','PDNP','SREF')"
elif dramconfig.bankwisePowerdown and not dramconfig.bankwiseRefresh:
excludedPhases = "('REQ','RESP','PRE_ALL','AUTO_REFRESH')"
else:
excludedPhases = "('REQ','RESP','PRE_ALL','PDNA','PDNP','SREF','AUTO_REFRESH')"
query = """SELECT PhaseBegin,count FROM (SELECT phaseBegin,count(phasebegin) AS count
FROM Phases WHERE PhaseName NOT IN """ + excludedPhases + """ AND phasebegin>0 GROUP BY phaseBegin) WHERE count>1"""
cursor.execute(query)
result = cursor.fetchone()
if(result != None):
return TestFailed("Slot on commandbus at time {0} is used twice".format(formatTime(result[0])))
return TestFailed("Slot on commandbus at time {0} is used multiple times".format(formatTime(result[0])))
return TestSuceeded()
@@ -171,29 +190,23 @@ def phases_on_bank_are_sequential(connection):
@test
def phase_lengths_are_correct(connection):
query = """SELECT ID,PhaseEnd-PhaseBegin FROM Phases WHERE PhaseName = :command and (PhaseEnd-PhaseBegin)!= :length"""
commandLengths = [('RD', dramconfig.tReadLength),
('RDA', dramconfig.tReadLength + dramconfig.tRP),
('WR', dramconfig.tWriteLength),
('WRA', dramconfig.tWriteLength + dramconfig.tRP),
('PRE', dramconfig.tRP),
('ACT', dramconfig.tRCD),
('AUTO_REFRESH', dramconfig.tRFC)]
for commandLength in commandLengths:
command = commandLength[0]
length = commandLength[1]
cursor = connection.cursor()
cursor.execute(query, {"command":command, "length" : length})
result = cursor.fetchone()
if(result != None):
return TestFailed("Phase with ID {0}({1}) has invalid length {2}".format(result[0],command,formatTime(result[1])))
query = """SELECT phases.ID,PhaseName, PhaseEnd-PhaseBegin,Burstlength FROM Phases INNER JOIN transactions ON transactions.ID = phases.transact """
cursor = connection.cursor()
cursor.execute(query)
for currentRow in cursor:
command = currentRow[1]
commandLength = currentRow[2]
burstlength = currentRow[3]
if(command == "RD" and commandLength != calculateReadLength(burstlength) or
command == "WR" and commandLength != calculateWriteLength(burstLength) or
command == "RDA" and commandLength != calculateReadLength(burstlength)+dramconfig.tRP or
command == "WRA" and commandLength != calculateReadLength(burstlength)+dramconfig.tRP or
(command == "PRE" or command=="PRE_ALL") and commandLength != dramconfig.tRP or
command == "AUTO_REFRESH" and commandLength != dramconfig.tRFC):
return TestFailed("Phase with ID {0}({1}) has invalid length of {2}".format(currentRow[0],command,formatTime(commandLength)))
return TestSuceeded()
#----------- activate checks ---------------------------------------
@test
@@ -325,6 +338,16 @@ def write_or_read_to_precharge(connection):
lastRow = currentRow
return TestSuceeded()
@test
def sref_active_for_minimal_time(connection):
"""Checks if SREF is active for at least a minimal time (JEDEC 229, P. 41)"""
cursor = connection.cursor()
cursor.execute("SELECT ID, PhaseEnd-PhaseBegin FROM Phases WHERE PhaseName = 'SREF'")
for currentRow in cursor:
if(currentRow[1] < dramconfig.tCKESR):
return TestFailed("SREF with ID {0} is {1} long. Minimal time in SREF is {2}".format(currentRow[0], formatTime(currentRow[1]), dramconfig.tCKESR))
return TestSuceeded()
# -------------------------- interface methods --------------------
def runTests(pathToTrace):

16
dram/src/common/TlmRecorder.cpp
View File

@@ -88,7 +88,7 @@ void TlmRecorder::setUpTransactionTerminatingPhases()
void TlmRecorder::prepareSqlStatements()
{
insertTransactionString =
"INSERT INTO Transactions VALUES (:id,:rangeID,:address,:thread,:channel,:bank,:row,:column,:command)";
"INSERT INTO Transactions VALUES (:id,:rangeID,:address,:burstlength,:thread,:channel,:bank,:row,:column,:command)";
insertRangeString = "INSERT INTO Ranges VALUES (:id,:begin,:end)";
updateRangeString = "UPDATE Ranges SET End = :end WHERE ID = :id";
insertPhaseString =
@@ -139,15 +139,16 @@ void TlmRecorder::insertTransactionInDB(unsigned int id, tlm::tlm_generic_payloa
sqlite3_bind_int(insertTransactionStatement, 1, id);
sqlite3_bind_int(insertTransactionStatement, 2, id);
sqlite3_bind_int(insertTransactionStatement, 3, trans.get_address());
sqlite3_bind_text(insertTransactionStatement, 9,
sqlite3_bind_int(insertTransactionStatement, 4, trans.get_streaming_width());
sqlite3_bind_text(insertTransactionStatement, 10,
trans.get_command() == tlm::TLM_READ_COMMAND ? "R" : "W", 1, 0);
const DramExtension& extension = DramExtension::getExtension(trans);
sqlite3_bind_int(insertTransactionStatement, 4, extension.getThread().ID());
sqlite3_bind_int(insertTransactionStatement, 5, extension.getChannel().ID());
sqlite3_bind_int(insertTransactionStatement, 6, extension.getBank().ID());
sqlite3_bind_int(insertTransactionStatement, 7, extension.getRow().ID());
sqlite3_bind_int(insertTransactionStatement, 8, extension.getColumn().ID());
sqlite3_bind_int(insertTransactionStatement, 5, extension.getThread().ID());
sqlite3_bind_int(insertTransactionStatement, 6, extension.getChannel().ID());
sqlite3_bind_int(insertTransactionStatement, 7, extension.getBank().ID());
sqlite3_bind_int(insertTransactionStatement, 8, extension.getRow().ID());
sqlite3_bind_int(insertTransactionStatement, 9, extension.getColumn().ID());
executeSqlStatement(insertTransactionStatement);
}
@@ -258,3 +259,4 @@ void TlmRecorder::closeConnection()
sqlite3_close(db);
db = NULL;
}

36
dram/src/common/Utils.cpp
View File

@@ -19,7 +19,7 @@ std::string phaseNameToString(tlm::tlm_phase phase)
return str;
}
unsigned int queryIntParameter(XMLElement* node, string name) {
unsigned int queryUIntParameter(XMLElement* node, string name) {
int result;
XMLElement* element;
for (element = node->FirstChildElement("parameter"); element != NULL;
@@ -34,10 +34,24 @@ unsigned int queryIntParameter(XMLElement* node, string name) {
}
}
std::cout << "error: " + name + " element not found" << endl;
reportFatal("Query XML","Parameter '" + name +"' does not exist.");
return 0;
}
bool parameterExists(tinyxml2::XMLElement* node, std::string name)
{
XMLElement* element;
for (element = node->FirstChildElement("parameter"); element != NULL;
element = element->NextSiblingElement("parameter"))
{
if (element->Attribute("id") == name)
{
return true;
}
}
return false;
}
double queryDoubleParameter(XMLElement* node, string name) {
double result;
XMLElement* element;
@@ -53,7 +67,7 @@ double queryDoubleParameter(XMLElement* node, string name) {
}
}
std::cout << "error: " + name + " element not found" << endl;
reportFatal("Query XML","Parameter '" + name +"' does not exist.");
return 0;
}
@@ -65,14 +79,14 @@ bool queryBoolParameter(XMLElement* node, string name) {
{
if (element->Attribute("id") == name)
{
assert(!strcmp(element->Attribute("type"), "double"));
assert(!strcmp(element->Attribute("type"), "bool"));
XMLError error = element->QueryBoolAttribute("value", &result);
assert(!error);
return result;
}
}
std::cout << "error: " + name + " element not found" << endl;
reportFatal("Query XML","Parameter '" + name +"' does not exist.");
return 0;
}
@@ -87,6 +101,16 @@ string queryStringParameter(XMLElement* node, string name) {
}
}
std::cout << "error: element not found" << endl;
reportFatal("Query XML","Parameter '" + name +"' does not exist.");
return 0;
}
void loadXML(string uri, XMLDocument& doc)
{
XMLError error = doc.LoadFile(uri.c_str());
if (error) {
reportFatal("Configuration", "Error loading xml from: " + uri);
}
}

5
dram/src/common/Utils.h
View File

@@ -41,7 +41,10 @@ bool isIn(const T& value, const std::vector<T>& collection)
void reportFatal(std::string sender, std::string message);
std::string phaseNameToString(tlm::tlm_phase phase);
unsigned int queryIntParameter(tinyxml2::XMLElement* node, std::string name);
void loadXML(std::string uri, tinyxml2::XMLDocument& doc);
bool parameterExists(tinyxml2::XMLElement* node, std::string name);
unsigned int queryUIntParameter(tinyxml2::XMLElement* node, std::string name);
std::string queryStringParameter(tinyxml2::XMLElement* node, std::string name);
bool queryBoolParameter(tinyxml2::XMLElement* node, std::string name);
double queryDoubleParameter(tinyxml2::XMLElement* node, std::string name);

16
dram/src/common/dramExtension.h
View File

@@ -103,20 +103,20 @@ private:
Bank bank;
Row row;
Column column;
unsigned int burstlength;
public:
DramExtension():thread(0),channel(0),bank(0),row(0),column(0){}
DramExtension(const Thread& thread, const Bank& bank, const Row& row, const Column& column) :
thread(thread),channel(0),bank(bank),row(row),column(column){}
DramExtension(const Thread& thread,const Channel& channel, const Bank& bank, const Row& row, const Column& column) :
thread(thread),channel(channel),bank(bank),row(row),column(column){}
DramExtension():thread(0),channel(0),bank(0),row(0),column(0),burstlength(0){}
DramExtension(const Thread& thread, const Bank& bank, const Row& row, const Column& column, unsigned int burstlength=0) :
thread(thread),channel(0),bank(bank),row(row),column(column), burstlength(burstlength){}
DramExtension(const Thread& thread,const Channel& channel, const Bank& bank, const Row& row, const Column& column, unsigned int burstlength=0) :
thread(thread),channel(channel),bank(bank),row(row),column(column), burstlength(burstlength){}
~DramExtension(){}
virtual tlm_extension_base* clone() const
{
return new DramExtension(thread, bank, row, column);
return new DramExtension(thread, bank, row, column, burstlength);
}
virtual void copy_from(const tlm_extension_base& ext)
{
@@ -125,6 +125,7 @@ public:
bank = cpyFrom.bank;
row = cpyFrom.row;
column = cpyFrom.column;
burstlength = cpyFrom.burstlength;
}
const Thread& getThread() const{return thread;}
@@ -132,6 +133,7 @@ public:
const Bank& getBank() const{return bank;}
const Row& getRow() const{return row;}
const Column& getColumn() const{return column;}
const unsigned int getBurstlength() const{return burstlength;}
static const DramExtension& getExtension(const tlm::tlm_generic_payload *payload);

2186
dram/src/common/third_party/tinyxml2.cpp vendored Normal file
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File diff suppressed because it is too large Load Diff

2076
dram/src/common/third_party/tinyxml2.h vendored Normal file
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File diff suppressed because it is too large Load Diff

1
dram/src/common/xmlAddressdecoder.cpp
View File

@@ -19,6 +19,7 @@ xmlAddressDecoder::xmlAddressDecoder(string addressConfigURI)
// get channel:
TiXmlElement* channel = addressmap->FirstChildElement("channel");
from = getAttribute<unsigned int>(channel, "from");
to = getAttribute<unsigned int>(channel, "to");

4
dram/src/core/BankStates.cpp
View File

@@ -6,6 +6,8 @@
*/
#include "BankStates.h"
#include "ControllerCore.h"
#include "../common/DebugManager.h"
using namespace std;
@@ -34,11 +36,13 @@ Row BankStates::getRowInRowBuffer(const Bank &bank) const
void BankStates::openRowInRowBuffer(const Bank &bank, const Row &row)
{
DebugManager::getInstance().printDebugMessage(ControllerCore::senderName, "Row buffer for bank " + to_string(bank.ID()) + " is now open");
rowsInRowBuffers.at(bank.ID()) = row;
}
void BankStates::closeRowBuffer(const Bank &bank)
{
DebugManager::getInstance().printDebugMessage(ControllerCore::senderName, "Row buffer for bank " + to_string(bank.ID()) + " is now closed");
rowsInRowBuffers.at(bank.ID()) = Row::NO_ROW;
}

11
dram/src/core/ControllerCore.cpp
View File

@@ -25,7 +25,7 @@ namespace core {
std::string ControllerCore::senderName = "Controller Core";
ControllerCore::ControllerCore(IWrapperConnector& wrapperConnector, std::map<Bank, int>& numberOfPayloads) :
config(), state(&config), wrapper(wrapperConnector), commandChecker(), numberOfPayloads(numberOfPayloads), savedState(
config(Configuration::getInstance()), state(&config), wrapper(wrapperConnector), commandChecker(), numberOfPayloads(numberOfPayloads), savedState(
&config), commandSequenceGenerator(state), commandSequenceScheduler(*this)
{
@@ -79,9 +79,15 @@ void ControllerCore::triggerRefresh(tlm::tlm_generic_payload& payload, sc_time t
if (!powerDownManager->isInSelfRefresh(bank))
{
if(config.BankwiseRefresh)
powerDownManager->wakeUpForRefresh(bank, time);//expect PDNA and PDNP to exit without delay
{
printDebugMessage("Waking up bank " + to_string(bank.ID()) + " for refresh");
powerDownManager->wakeUpForRefresh(bank, time);//expects PDNA and PDNP to exit without delay
}
else
{
printDebugMessage("Waking up all banks for refresh");
powerDownManager->wakeUpAllForRefresh(time);
}
refreshManager->scheduleRefresh(payload, time);
}
@@ -96,7 +102,6 @@ bool ControllerCore::scheduleRequest(sc_time start, tlm::tlm_generic_payload& pa
{
start = clkAlign(start, config.Timings.clk);
state.cleanUp(start);
payload.set_streaming_width(config.Burstlength);
saveState();

2
dram/src/core/ControllerCore.h
View File

@@ -11,7 +11,7 @@
#include <tlm.h>
#include <map>
#include "IWrapperConnector.h"
#include "Configuration.h"
#include "configuration/Configuration.h"
#include "powerdown/PowerDownManager.h"
#include "refresh/IRefreshManager.h"
#include "scheduling/CommandSequenceGenerator.h"

4
dram/src/core/ControllerState.cpp
View File

@@ -86,8 +86,8 @@ void ControllerState::change(const ScheduledCommand& scheduledCommand)
void ControllerState::cleanUp(sc_time time)
{
bus.cleanUpSlots(time);
lastDataStrobeCommands.remove_if([&](ScheduledCommand command){return command.getEnd() < time - config->Timings.tStrobeHistory;});
lastActivates.erase(lastActivates.begin(), lastActivates.lower_bound(time - config->Timings.tActHistory));
lastDataStrobeCommands.remove_if([&](ScheduledCommand command){return command.getEnd() < time - config->Timings.tDataStrobeHistory();});
lastActivates.erase(lastActivates.begin(), lastActivates.lower_bound(time - config->Timings.tActHistory()));
}
} /* namespace controller */

2
dram/src/core/ControllerState.h
View File

@@ -13,7 +13,7 @@
#include "utils/RingBuffer.h"
#include "scheduling/ScheduledCommand.h"
#include "Slots.h"
#include "Configuration.h"
#include "configuration/Configuration.h"
#include <map>
#include <set>
#include <list>

81
dram/src/core/TimingConfiguration.h
View File

@@ -1,81 +0,0 @@
/*
* TimingConfiguration.h
*
* Created on: Mar 6, 2014
* Author: jonny
*/
#ifndef TIMINGS_H_
#define TIMINGS_H_
#include <systemc.h>
#include "utils/Utils.h"
namespace core{
struct RefreshTiming
{
RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {}
sc_time tRFC;
sc_time tREFI;
};
struct TimingConfiguration
{
TimingConfiguration(unsigned int numberOfBanks)
{
clk = sc_time(6, SC_NS); // 166MHz
for (unsigned int i = 0; i < numberOfBanks; ++i)
{
sc_time tRFC = clkAlign(sc_time(130,SC_NS),clk);
//sc_time tREFI = 100*clk;
sc_time tREFI = clkAlign(sc_time(15.6, SC_US), clk);
refreshTimings.push_back(RefreshTiming(tRFC, tREFI));
}
refreshTimings.at(1).tREFI = clkAlign(sc_time(15.6 / 2, SC_US), clk);
refreshTimings.at(0).tREFI = clkAlign(sc_time(15.6 / 4, SC_US), clk);
tRP = 3*clk; //precharge-time (pre -> act same bank)
tRAS = 6*clk; //active-time (act -> pre same bank)
tRC = tRP + tRAS; //RAS-cycle-time (min time bw 2 succesive ACT to same bank)
tRRD = 2*clk; //(min time bw 2 succesive ACT to different banks)
tRCD = 3*clk; //act -> read/write
tRL = 3*clk; //read latency (read command start to data strobe)
tWL = 1*clk; //write latency
tTAW = clkAlign(sc_time(50,SC_NS), clk); //two activate window
tWTR = 3*clk;//write to read
tWR = 2*clk; //write recovery (write to precharge)
tActHistory = tTAW;
tStrobeHistory = tWTR;
tCKESR = clkAlign(max(3*clk, sc_time(15, SC_NS)), clk); //min time in sref
}
sc_time clk;
sc_time tRP;
sc_time tRAS;
sc_time tRC;
sc_time tRRD;
sc_time tRCD;
sc_time tTAW;
sc_time tRL;
sc_time tWL;
sc_time tWR;
sc_time tWTR;
sc_time tCKESR;
sc_time tActHistory, tStrobeHistory;
std::vector<RefreshTiming> refreshTimings;
};
} /* namespace controller */
#endif /* TimingConfiguration_H_ */

31
dram/src/core/configuration/Configuration.cpp Normal file
View File

@@ -0,0 +1,31 @@
/*
* Configuration.cpp
*
* Created on: Apr 7, 2014
* Author: jonny
*/
#include "Configuration.h"
#include "MemSpecLoader.h"
using namespace std;
namespace core{
string Configuration::memspecUri = "/home/jonny/git/dram/dram/resources/configs/memspecs/MatzesWideIO.xml";
string Configuration::memconfigUri = "/home/jonny/git/dram/dram/resources/configs/memconfigs/memconfig.xml";
Configuration::Configuration()
{
MemSpecLoader loader;
loader.loadConfiguration(*this, Configuration::memspecUri, Configuration::memconfigUri);
}
Configuration& Configuration::getInstance()
{
static Configuration configuration;
return configuration;
}
} /* namespace core */

29
dram/src/core/Configuration.h → dram/src/core/configuration/Configuration.h
View File

@@ -9,8 +9,10 @@
#define CONFIGURATION_H_
#include <systemc.h>
#include <string>
#include "TimingConfiguration.h"
namespace core{
struct Configuration
@@ -18,29 +20,30 @@ struct Configuration
static std::string memspecUri;
static std::string memconfigUri;
Configuration(): NumberOfBanks(8), NumberOfBankGroups(4), Burstlength(2), Timings(NumberOfBanks), BankwiseRefresh(true),BankwisePowerDown(true),
nActivate(2)
{
readMemSpec();
}
static Configuration& getInstance();
string MemoryId;
string MemmoryType;
string MemoryType;
//MemSpecification
unsigned int NumberOfBanks;
unsigned int NumberOfBankGroups;
unsigned int Burstlength;
unsigned int BurstLength;
unsigned int nActivate;
unsigned int DataRate;
unsigned int NumberOfRows;
//MemTimings
TimingConfiguration Timings;
//MemConfiguration
bool BankwiseRefresh;
bool BankwisePowerDown;
unsigned int nActivate;
bool OpenPagePolicy;
bool adaptiveOpenPagePolicy;
void readMemSpec();
void readMemConfig();
private:
Configuration();
};
} /* namespace core */

105
dram/src/core/configuration/MemSpecLoader.cpp Normal file
View File

@@ -0,0 +1,105 @@
/*
* MemSpecLoader.cpp
*
* Created on: Apr 7, 2014
* Author: jonny
*/
#include "MemSpecLoader.h"
#include "TimingConfiguration.h"
using namespace tinyxml2;
using namespace std;
namespace core {
void MemSpecLoader::loadConfiguration(Configuration& config, string memspecUri, string memconfigUri)
{
tinyxml2::XMLDocument doc;
loadXML(memspecUri, doc);
XMLElement* memspec = doc.FirstChildElement("memspec");
config.MemoryId = queryStringParameter(memspec, "memoryId");
config.MemoryType = queryStringParameter(memspec, "memoryType");
if (config.MemoryType == "DDR4")
{
loadDDR4(config, memspec);
}
else if (config.MemoryType == "WIDEIO_SDR")
{
loadWideIO(config, memspec);
}
else
{
reportFatal("ConfigurationLoader", "Unsupported Configuration");
}
loadXML(memconfigUri, doc);
memspec = doc.FirstChildElement("memspec");
loadConfig(config, memspec);
}
void MemSpecLoader::loadConfig(Configuration& config, XMLElement* memspec)
{
//MemConfiguration
XMLElement* configuration = memspec->FirstChildElement("memconfig");
config.BankwiseRefresh = queryBoolParameter(configuration, "bankwiseRefresh");
config.BankwisePowerDown = queryBoolParameter(configuration, "bankwisePowerDown");
config.OpenPagePolicy = queryBoolParameter(configuration, "openPagePolicy");
config.adaptiveOpenPagePolicy = queryBoolParameter(configuration, "adaptiveOpenPagePolicy");
}
void MemSpecLoader::loadDDR4(Configuration& config, XMLElement* memspec)
{
}
void MemSpecLoader::loadWideIO(Configuration& config, XMLElement* memspec)
{
//MemSpecification
XMLElement* architecture = memspec->FirstChildElement("memarchitecturespec");
config.NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks");
config.NumberOfBankGroups = 1;
config.BurstLength = queryUIntParameter(architecture, "burstLength");
config.nActivate = 2;
config.DataRate = queryUIntParameter(architecture, "dataRate");
config.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows");
//MemTimings
XMLElement* timings = memspec->FirstChildElement("memtimingspec");
double clkMhz = queryDoubleParameter(timings, "clkMhz");
sc_time clk = sc_time(1 / clkMhz, SC_US);
config.Timings.clk = clk;
config.Timings.tRP = clk * queryUIntParameter(timings, "RP");
config.Timings.tRAS = clk * queryUIntParameter(timings, "RAS");
config.Timings.tRC = clk * queryUIntParameter(timings, "RC");
config.Timings.tRRD = clk * queryUIntParameter(timings, "RRD");
config.Timings.tRCD = clk * queryUIntParameter(timings, "RCD");
config.Timings.tNAW = clk * queryUIntParameter(timings, "TAW");
config.Timings.tRL = clk * queryUIntParameter(timings, "RL");
config.Timings.tWL = clk * queryUIntParameter(timings, "WL");
config.Timings.tWR = clk * queryUIntParameter(timings, "WR");
config.Timings.tWTR = clk * queryUIntParameter(timings, "WTR");
config.Timings.tCKESR = clk * queryUIntParameter(timings, "CKESR");
config.Timings.tCKE = clk * queryUIntParameter(timings, "CKE");
config.Timings.tXP = clk * queryUIntParameter(timings, "XP");
config.Timings.tXSR = clk * queryUIntParameter(timings, "XS");
config.Timings.tAL = clk * queryUIntParameter(timings, "AL");
config.Timings.tRFC = clk * queryUIntParameter(timings, "RFC");
config.Timings.tREFI = clk * queryUIntParameter(timings, "REFI");
config.Timings.refreshTimings.clear();
for (unsigned int i = 0; i < config.NumberOfBanks; ++i)
{
config.Timings.refreshTimings.push_back(
RefreshTiming(config.Timings.tRFC, config.Timings.tREFI));
}
}
} /* namespace core */

32
dram/src/core/configuration/MemSpecLoader.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* MemSpecLoader.h
*
* Created on: Apr 7, 2014
* Author: jonny
*/
#ifndef MEMSPECLOADER_H_
#define MEMSPECLOADER_H_
#include <string>
#include "../../common/third_party/tinyxml2.h"
#include "../../common/Utils.h"
#include "Configuration.h"
namespace core {
class MemSpecLoader
{
public:
void loadConfiguration(Configuration& config, std::string memspec, std::string memconfig);
private:
void loadDDR4(Configuration& config, tinyxml2::XMLElement* memspec);
void loadWideIO(Configuration& config, tinyxml2::XMLElement* memspec);
void loadConfig(Configuration& config, tinyxml2::XMLElement* memspec);
};
} /* namespace core */
#endif /* MEMSPECLOADER_H_ */

61
dram/src/core/configuration/TimingConfiguration.h Normal file
View File

@@ -0,0 +1,61 @@
/*
* TimingConfiguration.h
*
* Created on: Mar 6, 2014
* Author: jonny
*/
#ifndef TIMINGS_H_
#define TIMINGS_H_
#include <systemc.h>
#include "../utils/Utils.h"
namespace core{
struct RefreshTiming
{
RefreshTiming(sc_time tRFC, sc_time tREFI) : tRFC(tRFC), tREFI(tREFI) {}
sc_time tRFC;
sc_time tREFI;
};
struct TimingConfiguration
{
TimingConfiguration()
{
}
unsigned int numberOfBanks;
sc_time clk;
sc_time tRP; //precharge-time (pre -> act same bank)
sc_time tRAS; //active-time (act -> pre same bank)
sc_time tRC; //RAS-cycle-time (min time bw 2 succesive ACT to same bank)
sc_time tRRD; //(min time bw 2 succesive ACT to different banks)
sc_time tRCD; //act -> read/write
sc_time tNAW; //two activate window
sc_time tRL; //read latency (read command start to data strobe)
sc_time tWL; //write latency
sc_time tWR; //write recovery (write to precharge)
sc_time tWTR; //write to read
sc_time tCKESR; //min time in sref
sc_time tCKE;
sc_time tXP;
sc_time tXSR;
sc_time tAL;
sc_time tRFC;
sc_time tREFI;
std::vector<RefreshTiming> refreshTimings;
//act and read/write commands remain for this timespan in history
sc_time tActHistory(){return tNAW;}
sc_time tDataStrobeHistory(){return tWTR;}
};
} /* namespace core */
#endif /* TimingConfiguration_H_ */

5
dram/src/core/powerdown/PowerDownManager.cpp
View File

@@ -45,10 +45,6 @@ void PowerDownManager::sleep(Bank bank, sc_time time)
sendPowerDownPayload(time, bank, getSleepCommand(getPowerDownState(bank)));
}
else
{
SC_REPORT_FATAL("Power Down Manager", "Sleep triggered even though already in sleep");
}
}
void PowerDownManager::wakeUp(Bank bank, sc_time time)
@@ -260,7 +256,6 @@ void PowerDownManager::init()
controller.state.change(pdn);
controller.wrapper.send(pdn, payload);
powerDownStates[bank] = PowerDownState::PDNPrecharge;
//setState(PowerDownState::PDNPrecharge, bank);
}
}

30
dram/src/core/powerdown/PowerDownManagerGrouped.cpp
View File

@@ -25,9 +25,7 @@ PowerDownManagerGrouped::~PowerDownManagerGrouped()
void PowerDownManagerGrouped::sleep(Bank bank, sc_time time)
{
assert(!isInPowerDown());//cause nobody calls sleep if already sleeping on all banks
//all banks can sleep and no pending refresh
//all banks can sleep and no pending refresh in system
if (!canSleep() || (controller.state.getLastCommand(Command::AutoRefresh).getEnd() > time))
return;
@@ -43,19 +41,20 @@ void PowerDownManagerGrouped::sleep(Bank bank, sc_time time)
}
else if (state == PowerDownState::AwakeForRefresh)//coming from refresh interrupting power down
{
//last running refresh triggers sleep
if (controller.state.getLastCommand(Command::PDNA).getStart()
> controller.state.getLastCommand(Command::PDNP).getStart())
setState(PowerDownState::PDNPrecharge);
if(controller.state.bankStates.allRowBuffersAreClosed())
{
if (controller.state.getLastCommand(Command::PDNA).getStart()
> controller.state.getLastCommand(Command::PDNP).getStart())
setState(PowerDownState::PDNPrecharge);
else
setState(PowerDownState::PDNSelfRefresh);
}
else
setState(PowerDownState::PDNSelfRefresh);
{
setState(PowerDownState::PDNActive);
}
sendPowerDownPayload(time, getSleepCommand(getPowerDownState()));
}
else
{
SC_REPORT_FATAL("PowerDownManagerGrouped", "Sleep triggered even though already in sleep");
}
}
void PowerDownManagerGrouped::wakeUp(Bank bank, sc_time time)
@@ -105,10 +104,7 @@ void PowerDownManagerGrouped::wakeUpAllForRefresh(sc_time time)
{
if(isInPowerDown())
{
for (Bank bank : controller.getBanks())
{
sendPowerDownPayload(time, getWakeUpCommand(getPowerDownState()));
}
sendPowerDownPayload(time, getWakeUpCommand(getPowerDownState()));
setState(PowerDownState::AwakeForRefresh);
}

2
dram/src/core/refresh/RefreshManager.h
View File

@@ -9,7 +9,7 @@
#define REFRESHMANAGER_H_
#include "IRefreshManager.h"
#include "../TimingConfiguration.h"
#include "../configuration/TimingConfiguration.h"
namespace core {

2
dram/src/core/refresh/RefreshManagerBankwise.h
View File

@@ -10,7 +10,7 @@
#include "../scheduling/CommandSchedule.h"
#include "../../common/dramExtension.h"
#include "../TimingConfiguration.h"
#include "../configuration/TimingConfiguration.h"
#include "IRefreshManager.h"
namespace core {

5
dram/src/core/scheduling/CommandSchedule.h
View File

@@ -18,7 +18,7 @@ class CommandSchedule
{
public:
CommandSchedule(tlm::tlm_generic_payload& transaction) :
extension(DramExtension::getExtension(&transaction)), burstLength(transaction.get_streaming_width())
extension(DramExtension::getExtension(&transaction))
{
}
@@ -28,7 +28,7 @@ public:
ScheduledCommand& add(Command command, sc_time start, sc_time executionTime)
{
scheduledCommands.push_back(ScheduledCommand(command, start, executionTime, extension, burstLength));
scheduledCommands.push_back(ScheduledCommand(command, start, executionTime, extension));
return scheduledCommands.back();
}
@@ -59,7 +59,6 @@ public:
private:
std::vector<ScheduledCommand> scheduledCommands;
unsigned int burstLength;
DramExtension extension;
};

2
dram/src/core/scheduling/ScheduledCommand.cpp
View File

@@ -69,7 +69,7 @@ Row ScheduledCommand::getRow() const
unsigned int ScheduledCommand::getBurstLength()
{
return burstLength;
return extension.getBurstlength();
}
bool ScheduledCommand::operator ==(const ScheduledCommand& b) const

7
dram/src/core/scheduling/ScheduledCommand.h
View File

@@ -20,15 +20,15 @@ class ScheduledCommand
{
public:
ScheduledCommand(Command command, sc_time start, sc_time executionTime, const DramExtension& extension, unsigned int burstLength = 0) :
command(command), start(start), executionTime(executionTime),end(start+executionTime), burstLength(burstLength),
ScheduledCommand(Command command, sc_time start, sc_time executionTime, const DramExtension& extension) :
command(command), start(start), executionTime(executionTime),end(start+executionTime),
extension(extension)
{
}
ScheduledCommand() :
command(Command::NOP), start(SC_ZERO_TIME), executionTime(SC_ZERO_TIME), end(SC_ZERO_TIME), burstLength(0), extension()
command(Command::NOP), start(SC_ZERO_TIME), executionTime(SC_ZERO_TIME), end(SC_ZERO_TIME), extension()
{
}
@@ -58,7 +58,6 @@ private:
sc_time start;
sc_time executionTime;
sc_time end;
unsigned int burstLength;
DramExtension extension;
};
} /* namespace controller */

2
dram/src/core/scheduling/checker/ActivateChecker.cpp
View File

@@ -89,7 +89,7 @@ bool ActivateChecker::satisfies_nActivateWindow(ScheduledCommand& command) const
while(upper != lastActivates.end())
{
if(*upper-*lower < config.Timings.tTAW)
if(*upper-*lower < config.Timings.tNAW)
return false;
++upper;
++lower;

2
dram/src/core/scheduling/checker/ActivateChecker.h
View File

@@ -10,7 +10,7 @@
#include <map>
#include "ICommandChecker.h"
#include "../../Configuration.h"
#include "../../configuration/Configuration.h"
#include "../../utils/RingBuffer.h"
#include "../../ControllerState.h"

2
dram/src/core/scheduling/checker/PrechargeAllChecker.h
View File

@@ -9,7 +9,7 @@
#define PRECHARGEALLCHECKER_H_
#include "ICommandChecker.h"
#include "../../Configuration.h"
#include "../../configuration/Configuration.h"
#include "../../ControllerState.h"
namespace core {

2
dram/src/core/scheduling/checker/PrechargeChecker.h
View File

@@ -9,7 +9,7 @@
#define PRECHARGECHECKER_H_
#include "ICommandChecker.h"
#include "../../Configuration.h"
#include "../../configuration/Configuration.h"
#include "../../ControllerState.h"
namespace core {

15
dram/src/core/scheduling/checker/ReadChecker.cpp
View File

@@ -78,22 +78,13 @@ bool ReadChecker::collidesWithStrobeCommand(ScheduledCommand& read,
if (strobeCommand.getCommand() == Command::Read || strobeCommand.getCommand() == Command::ReadA)
{
//read to read
TimeInterval readOnStrobe = getIntervalOnDataStrobe(read, config.Timings);
TimeInterval otherReadOnStrobe = getIntervalOnDataStrobe(strobeCommand, config.Timings);
if (readOnStrobe.timeIsInInterval(otherReadOnStrobe.start))
if(read.getStart() < strobeCommand.getStart())
{
return !isClkAligned(otherReadOnStrobe.start - readOnStrobe.start,
2 * config.Timings.clk);
}
else if (otherReadOnStrobe.timeIsInInterval(readOnStrobe.start))
{
return !isClkAligned(readOnStrobe.start - otherReadOnStrobe.start,
2 * config.Timings.clk);
return (strobeCommand.getStart() - read.getStart() < read.getBurstLength()*config.Timings.clk);
}
else
{
return false;
return (read.getStart() - strobeCommand.getStart() < strobeCommand.getBurstLength()*config.Timings.clk);
}
}
else if (strobeCommand.getCommand() == Command::Write

2
dram/src/core/scheduling/checker/ReadChecker.h
View File

@@ -9,7 +9,7 @@
#define READCHECKER_H_
#include "ICommandChecker.h"
#include "../../Configuration.h"
#include "../../configuration/Configuration.h"
#include "../../ControllerState.h"
namespace core {

16
dram/src/core/scheduling/checker/WriteChecker.cpp
View File

@@ -27,7 +27,8 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand& command) const
}
}
else if (lastCommand.getCommand() == Command::Read
|| lastCommand.getCommand() == Command::Write || lastCommand.getCommand() == Command::PDNAX)
|| lastCommand.getCommand() == Command::Write
|| lastCommand.getCommand() == Command::PDNAX)
{
}
else
@@ -73,8 +74,17 @@ bool WriteChecker::collidesWithStrobeCommand(ScheduledCommand& write,
if (strobeCommand.getCommand() == Command::Write
|| strobeCommand.getCommand() == Command::WriteA)
{
//write to write (implicitly checked by checking the command bus first)
return false;
//write to write
if (write.getStart() < strobeCommand.getStart())
{
return (strobeCommand.getStart() - write.getStart()
< write.getBurstLength() * config.Timings.clk);
}
else
{
return (write.getStart() - strobeCommand.getStart()
< strobeCommand.getBurstLength() * config.Timings.clk);
}
}
else if (strobeCommand.getCommand() == Command::Read
|| strobeCommand.getCommand() == Command::ReadA)

2
dram/src/core/scheduling/checker/WriteChecker.h
View File

@@ -9,7 +9,7 @@
#define WRITECHECKER_H_
#include "ICommandChecker.h"
#include "../../Configuration.h"
#include "../../configuration/Configuration.h"
#include "../../ControllerState.h"
namespace core {

2
dram/src/core/utils/Utils.cpp
View File

@@ -6,7 +6,7 @@
*/
#include "Utils.h"
#include "../TimingConfiguration.h"
#include "../configuration/TimingConfiguration.h"
#include "../ControllerCore.h"
#include "../../common/DebugManager.h"

3
dram/src/simulation/Arbiter.h
View File

@@ -132,9 +132,10 @@ private:
void appendDramExtension(int socketId, tlm_generic_payload& payload)
{
unsigned int burstlength = payload.get_streaming_width();
node n;
xmlAddressDecoder::getInstance().getNode(static_cast<unsigned int>(payload.get_address()), &n);
DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(n.channel), Bank(n.bank), Row(n.row), Column(n.colum));
DramExtension* extension = new DramExtension(Thread(socketId+1), Channel(n.channel), Bank(n.bank), Row(n.row), Column(n.colum),burstlength);
payload.set_auto_extension(extension);
}
};

7
dram/src/simulation/Controller.h
View File

@@ -177,7 +177,7 @@ private:
void scheduleNextPayload(Bank bank)
{
printDebugMessage("Try to schedule next payload on bank " + to_string(bank.ID()));
printDebugMessage("Triggering schedule next payload on bank " + to_string(bank.ID()));
if (scheduler->hasTransactionForBank(bank))
{
@@ -188,8 +188,8 @@ private:
}
if (controller->powerDownManager->isInPowerDown(bank))
{
printDebugMessage("\t-> break: wake up bank first");
controller->powerDownManager->wakeUp(bank, sc_time_stamp());
printDebugMessage("\t-> break: wake up power down");
return;
}
else if (controller->powerDownManager->isAwakeForRefresh(bank))
@@ -302,7 +302,10 @@ private:
{
printDebugMessage("Finished auto refresh on bank " + to_string(bank.ID()));
if (numberOfPayloadsInSystem[bank] == 0)
{
printDebugMessage("\t -> Triggering sleep on bank " + to_string(bank.ID()));
controller->powerDownManager->sleep(bank, sc_time_stamp());
}
scheduleNextPayload(DramExtension::getExtension(payload).getBank());
}
else if (isIn(phase, { END_PRE, END_PRE_ALL, END_ACT }))

2
dram/src/simulation/ISimulationManager.h
View File

@@ -8,7 +8,7 @@ class ISimulationManager
{
public:
virtual ~ISimulationManager(){}
virtual void tracePlayerFinishedCallback() = 0;
virtual void tracePlayerFinishedCallback(string name) = 0;
};
} // namespace simulation

28
dram/src/simulation/SimulationManager.cpp
View File

@@ -17,13 +17,15 @@ using namespace std;
namespace simulation {
SimulationManager::SimulationManager(sc_module_name name, std::string stl1, std::string stl2,
SimulationManager::SimulationManager(sc_module_name name, std::string stl1,
unsigned int burstlength1, std::string stl2, unsigned int burstlenght2,
std::string traceName, std::string pathToResources) :
dram("dram"), arbiter("arbiter"), controller("controller"), player1("player1",
pathToResources + string("traces/") + stl1, this), player2("player2",
pathToResources + string("traces/") + stl2, this), traceName(traceName)
pathToResources + string("traces/") + stl1,burstlength1, this), player2("player2",
pathToResources + string("traces/") + stl2,burstlenght2, this), traceName(traceName)
{
SC_THREAD(terminationThread);
xmlAddressDecoder::addressConfigURI = pathToResources + string("configs/addressConfig.xml");
TlmRecorder::dbName = traceName;
@@ -38,6 +40,7 @@ SimulationManager::SimulationManager(sc_module_name name, std::string stl1, std:
whiteList.push_back(controller.name());
whiteList.push_back(player2.name());
whiteList.push_back(player1.name());
whiteList.push_back(this->name());
whiteList.push_back(TlmRecorder::senderName);
whiteList.push_back(ControllerCore::senderName);
whiteList.push_back(PowerDownManager::senderName);
@@ -49,21 +52,21 @@ void SimulationManager::startSimulation()
clock_t begin = clock();
cout << "Toplevel: simulation start" << std::endl;
DebugManager::getInstance().printDebugMessage(name(), "Starting simulation");
player1.start();
player2.start();
sc_start();
clock_t end = clock();
double elapsed_secs = double(end - begin) / CLOCKS_PER_SEC;
cout << "Simulation took " << elapsed_secs << " seconds." << endl;
cout << this->name();
string p = getenv("trace");
string run_tpr = p + " " + traceName;
system(run_tpr.c_str());
DebugManager::getInstance().printDebugMessage(name(),
"Simulation took " + to_string(elapsed_secs) + " seconds");
}
void SimulationManager::tracePlayerFinishedCallback()
void SimulationManager::tracePlayerFinishedCallback(string name)
{
DebugManager::getInstance().printDebugMessage(this->name(), "Traceplayer " + name + " finshed");
static int finishedPlayers = 0;
finishedPlayers++;
if (finishedPlayers == numberOfTracePlayers)
@@ -75,9 +78,10 @@ void SimulationManager::tracePlayerFinishedCallback()
void SimulationManager::terminationThread()
{
wait(terminateSimulation);
DebugManager::getInstance().printDebugMessage(this->name(), "Terminating simulation");
controller.terminateSimulation();
//waits for the termination of all pending powerdown phases in the dram system
wait(sc_time(50,SC_NS));
wait(sc_time(50, SC_NS));
TlmRecorder::getInstance().closeConnection();
sc_stop();
}

7
dram/src/simulation/SimulationManager.h
View File

@@ -22,10 +22,11 @@ class SimulationManager : public ISimulationManager, public sc_module
{
public:
SC_HAS_PROCESS(SimulationManager);
SimulationManager(sc_module_name name,std::string stl1, std::string stl2,
std::string traceName, std::string pathToResources);
SimulationManager(sc_module_name name, std::string stl1,
unsigned int burstlength1, std::string stl2, unsigned int burstlenght2,
std::string traceName, std::string pathToResources);
void startSimulation();
void tracePlayerFinishedCallback() override;
void tracePlayerFinishedCallback(string name) override;
private:
void terminationThread();

28
dram/src/simulation/TracePlayer.h
View File

@@ -28,28 +28,36 @@ struct TracePlayer: public sc_module
{
public:
tlm_utils::simple_initiator_socket<TracePlayer, BUSWIDTH, tlm::tlm_base_protocol_types> iSocket;
TracePlayer(sc_module_name name, string pathToTrace,
TracePlayer(sc_module_name name, string pathToTrace, unsigned int burstlength,
simulation::ISimulationManager* simulationManager) :
payloadEventQueue(this, &TracePlayer::peqCallback), file(pathToTrace), numberOfPendingTransactions(
payloadEventQueue(this, &TracePlayer::peqCallback), file(pathToTrace), burstlenght(burstlength), numberOfPendingTransactions(
0), transactionsSent(0), transactionsReceived(0), simulationManager(
simulationManager)
{
if (!file.is_open())
SC_REPORT_FATAL(0, (string("Could not open trace ") + pathToTrace).c_str());
if (!file)
{
SC_REPORT_FATAL(0, "trace is empty! Simulation stops");
}
iSocket.register_nb_transport_bw(this, &TracePlayer::nb_transport_bw);
scheduleNextPayload();
}
void start()
{
bool fileIsEmpty = file.peek() == std::ifstream::traits_type::eof();
if (fileIsEmpty)
{
simulationManager->tracePlayerFinishedCallback(name());
}
else
{
scheduleNextPayload();
}
}
private:
tlm_utils::peq_with_cb_and_phase<TracePlayer> payloadEventQueue;
MemoryManager memoryManager;
ifstream file;
unsigned int burstlenght;
unsigned int numberOfPendingTransactions;
unsigned int transactionsSent;
unsigned int transactionsReceived;
@@ -89,7 +97,7 @@ private:
payload->set_response_status(TLM_INCOMPLETE_RESPONSE);
payload->set_dmi_allowed(false);
payload->set_byte_enable_length(0);
payload->set_streaming_width(0);
payload->set_streaming_width(burstlenght);
sc_time sendingTime = sc_time(std::stoi(time.c_str()), SC_NS);
if (sendingTime <= sc_time_stamp())
@@ -137,7 +145,7 @@ private:
+ std::to_string(transactionsSent - transactionsReceived));
if (numberOfPendingTransactions == 0)
simulationManager->tracePlayerFinishedCallback();
simulationManager->tracePlayerFinishedCallback(name());
}
else if (phase == END_RESP)

15
dram/src/simulation/main.cpp
View File

@@ -17,15 +17,26 @@ string pathOfFile(string file)
return file.substr(0, file.find_last_of('/'));
}
void startTraceAnalyzer(string traceName)
{
string p = getenv("trace");
string run_tpr = p + " " + traceName;
system(run_tpr.c_str());
}
int sc_main(int argc, char **argv)
{
sc_set_time_resolution(1, SC_NS);
string resources = pathOfFile(argv[0]) + string("/../resources/");
string stl1 = "chstone-mips_32.stl";
string stl2 = "chstone-motion_32.stl";
SimulationManager simulationManager("sim",stl1,stl2,"tpr.tdb", resources);
unsigned int burstlength1 = 4;
string stl2 = "empty.stl";
unsigned int burstlength2 = 2;
string traceName = "tpr.tdb";
SimulationManager simulationManager("sim", stl1,burstlength1, stl2,burstlength2, traceName, resources);
simulationManager.startSimulation();
startTraceAnalyzer(traceName);
return 0;
}