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Merge branch 'test_improvement' into 'develop'

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Updates to readme for GitHub.

See merge request ems/astdm/dram.sys!262
This commit is contained in:
Lukas Steiner
2020-07-22 10:06:23 +02:00
parent 9e403d5887 4379390473
commit 12a4163afc
15 changed files with 172 additions and 69 deletions
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41
DRAMSys/library/resources/configs/amconfigs/am_wideio_thermal.json Normal file
View File

@@ -0,0 +1,41 @@
{
"CONGEN": {
"BANK_BIT": [
4,
5
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
25,
26
],
"COLUMN_BIT": [
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24
]
}
}

2
DRAMSys/library/resources/configs/simulator/wideio_thermal.json
View File

@@ -10,7 +10,7 @@
"PowerAnalysis": true,
"SimulationName": "wideio",
"SimulationProgressBar": true,
"StoreMode": "ErrorModel",
"StoreMode": "Store",
"ThermalSimulation": true,
"UseMalloc": false,
"WindowSize": 1000

2
DRAMSys/library/resources/simulations/ddr3-example.json
View File

@@ -1,7 +1,7 @@
{
"simulation": {
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json",
"mcconfig": "fifoStrict.json",
"mcconfig": "fr_fcfs.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "ddr3.json",
"simulationid": "ddr3-example",

2
DRAMSys/library/resources/simulations/ddr3-example2.json
View File

@@ -1,7 +1,7 @@
{
"simulation": {
"addressmapping": "am_ddr3_8x1Gbx8_dimm_p1KB_brc.json",
"mcconfig": "fifoStrict.json",
"mcconfig": "fr_fcfs.json",
"memspec": "MICRON_1Gb_DDR3-1600_8bit_G.json",
"simconfig": "ddr3.json",
"simulationid": "ddr3-example2",

2
DRAMSys/library/resources/simulations/ddr4-example.json
View File

@@ -1,7 +1,7 @@
{
"simulation": {
"addressmapping": "am_ddr4_8x4Gbx8_dimm_p1KB_brc.json",
"mcconfig": "fifoStrict.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_4Gb_DDR4-1866_8bit_A.json",
"simconfig": "ddr4.json",
"simulationid": "ddr4-example",

2
DRAMSys/library/resources/simulations/hbm2-example.json
View File

@@ -1,7 +1,7 @@
{
"simulation": {
"addressmapping": "am_hbm2_8Gb_pc_brc.json",
"mcconfig": "fifoStrict.json",
"mcconfig": "fr_fcfs.json",
"memspec": "HBM2.json",
"simconfig": "hbm2.json",
"simulationid": "hbm2-example",

2
DRAMSys/library/resources/simulations/lpddr4-example.json
View File

@@ -1,7 +1,7 @@
{
"simulation": {
"addressmapping": "am_lpddr4_8Gbx16_brc.json",
"mcconfig": "fifoStrict.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_8Gb_LPDDR4-3200_16bit.json",
"simconfig": "lpddr4.json",
"simulationid": "lpddr4-example",

2
DRAMSys/library/resources/simulations/ranktest.json
View File

@@ -1,7 +1,7 @@
{
"simulation": {
"addressmapping": "am_ranktest.json",
"mcconfig": "fifoStrict.json",
"mcconfig": "fr_fcfs.json",
"memspec": "memspec_ranktest.json",
"simconfig": "ddr3.json",
"simulationid": "ranktest",

2
DRAMSys/library/resources/simulations/wideio-example.json
View File

@@ -1,7 +1,7 @@
{
"simulation": {
"addressmapping": "am_wideio_4x256Mb_rbc.json",
"mcconfig": "fifoStrict.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_256Mb_WIDEIO-200_128bit.json",
"simconfig": "wideio.json",
"simulationid": "wideio-example",

2
DRAMSys/library/resources/simulations/wideio-thermal.json
View File

@@ -1,6 +1,6 @@
{
"simulation": {
"addressmapping": "am_wideio_4x256Mb_rbc.json",
"addressmapping": "am_wideio_thermal.json",
"mcconfig": "fr_fcfs.json",
"memspec": "JEDEC_256Mb_WIDEIO-200_128bit.json",
"simconfig": "wideio_thermal.json",

97
DRAMSys/library/resources/traces/generateErrorTest.pl
View File

@@ -33,35 +33,72 @@
# Authors:
# Matthias Jung
# Eder F. Zulian
# Lukas Steiner
use warnings;
use strict;
# Assuming this address mapping:
# <addressmapping>
# <channel from="27" to="28" />
# <row from="14" to="26" />
# <column from="7" to="13" />
# <bank from="4" to="6" />
# <bytes from="0" to="3" />
# </addressmapping>
# {
# "CONGEN": {
# "BYTE_BIT": [
# 0,
# 1,
# 2,
# 3
# ],
# "BANK_BIT": [
# 4,
# 5
# ],
# "COLUMN_BIT": [
# 6,
# 7,
# 8,
# 9,
# 10,
# 11,
# 12
# ],
# "ROW_BIT": [
# 13,
# 14,
# 15,
# 16,
# 17,
# 18,
# 19,
# 20,
# 21,
# 22,
# 23,
# 24
# ],
# "CHANNEL_BIT": [
# 25,
# 26
# ]
# }
# }
# This is how it should look like later:
# 31: write 0x0 ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
# 31: write 0x0 0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
my $numberOfRows = 8192;
my $numberOfColumnsPerRow = 128;
my $numberOfChannels = 4;
my $numberOfRows = 4096;
my $numberOfColumns = 128;
my $bytesPerColumn = 16;
my $burstLength = 4; # burst length of 4 columns --> 4 columns written or read per access
my $dataLength = $bytesPerColumn * $burstLength;
my $rowOffset = 0x4000;
my $colOffset = 0x80;
my $channelOffset = 0x2000000;
my $rowOffset = 0x2000;
my $columnOffset = 0x40;
# Generate Data Pattern:
my $dataPatternByte = "ff";
my $dataPattern = "";
my $dataPattern = "0x";
for(my $i = 0; $i < $dataLength; $i++)
{
$dataPattern .= $dataPatternByte;
@@ -71,28 +108,34 @@ my $clkCounter = 0;
my $addr = 0;
# Generate Trace file (writes):
for(my $row = 0; $row < ($numberOfRows * $rowOffset); $row = $row + $rowOffset)
for(my $cha = 0; $cha < ($numberOfChannels * $channelOffset); $cha = $cha + $channelOffset)
{
for(my $col = 0; $col < ($numberOfColumnsPerRow * $colOffset); $col = $col + ($colOffset * $burstLength))
for(my $row = 0; $row < ($numberOfRows * $rowOffset); $row = $row + $rowOffset)
{
my $addrHex = sprintf("0x%x", $addr);
print "$clkCounter:\twrite\t$addrHex\t$dataPattern\n";
$clkCounter++;
$addr += $colOffset * $burstLength;
for(my $col = 0; $col < ($numberOfColumns * $columnOffset); $col = $col + ($columnOffset * $burstLength))
{
my $addrHex = sprintf("0x%x", $addr);
print "$clkCounter:\twrite\t$addrHex\t$dataPattern\n";
$clkCounter++;
$addr += $columnOffset * $burstLength;
}
}
}
$clkCounter = 350000000;
$clkCounter = 50000000;
$addr = 0;
# Generate Trace file (reads):
for(my $row = 0; $row < ($numberOfRows * $rowOffset); $row = $row + $rowOffset)
for(my $cha = 0; $cha < ($numberOfChannels * $channelOffset); $cha = $cha + $channelOffset)
{
for(my $col = 0; $col < ($numberOfColumnsPerRow * $colOffset); $col = $col + ($colOffset * $burstLength))
for(my $row = 0; $row < ($numberOfRows * $rowOffset); $row = $row + $rowOffset)
{
my $addrHex = sprintf("0x%x", $addr);
print "$clkCounter:\tread\t$addrHex\t$dataPattern\n";
$clkCounter++;
$addr += $colOffset * $burstLength;
for(my $col = 0; $col < ($numberOfColumns * $columnOffset); $col = $col + ($columnOffset * $burstLength))
{
my $addrHex = sprintf("0x%x", $addr);
print "$clkCounter:\tread\t$addrHex\n";
$clkCounter++;
$addr += $columnOffset * $burstLength;
}
}
}
}

6
DRAMSys/library/src/simulation/dram/Dram.cpp
View File

@@ -117,11 +117,9 @@ Dram::~Dram()
void Dram::reportPower()
{
static bool alreadyCalled = false;
if (!alreadyCalled)
if (!powerReported)
{
alreadyCalled = true;
powerReported = true;
DRAMPower->calcEnergy();
// Print the final total energy and the average power for

1
DRAMSys/library/src/simulation/dram/Dram.h
View File

@@ -51,6 +51,7 @@ class Dram : public sc_module
{
private:
unsigned int bytesPerBurst = Configuration::getInstance().getBytesPerBurst();
bool powerReported = false;
protected:
Dram(sc_module_name);

6
DRAMSys/simulator/StlPlayer.h
View File

@@ -140,15 +140,15 @@ public:
("Malformed trace file. Data information could not be found (line " + std::to_string(
lineCnt) + ").").c_str());
// Check if data length in the trace file is correct. We need two characters to represent 1 byte in hexadecimal.
if (dataStr.length() != (dataLength * 2))
// Check if data length in the trace file is correct. We need two characters to represent 1 byte in hexadecimal. Offset for 0x prefix.
if (dataStr.length() != (dataLength * 2 + 2))
SC_REPORT_FATAL("StlPlayer",
("Data in the trace file has an invalid length (line " + std::to_string(
lineCnt) + ").").c_str());
// Set data
for (unsigned i = 0; i < dataLength; i++)
data[i] = (unsigned char)std::stoi(dataStr.substr(i * 2, 2).c_str(), 0, 16);
data[i] = (unsigned char)std::stoi(dataStr.substr(i * 2 + 2, 2).c_str(), 0, 16);
}
// Fill up the payload.

72
README.md
View File

@@ -1,11 +1,18 @@
DRAMSys4.0
===========
<img src="DRAMSys/docs/images/dramsys4_0.png" width="350" style="float: left;"/>
**DRAMSys4.0** [1] [2] [3] is a flexible DRAM subsystem design space exploration framework based on SystemC TLM-2.0.
**DRAMSys4.0** is a flexible DRAM subsystem design space exploration framework based on SystemC TLM-2.0. It was developed at the [Microelectronic Systems Design Research Group](https://ems.eit.uni-kl.de/en/start/) and [Fraunhofer IESE](https://www.iese.fraunhofer.de/en.html).
Pipeline Status: [![pipeline status](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/pipeline.svg)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master)
[![Coverage report](https://git.eit.uni-kl.de/ems/astdm/dram.sys/badges/master/coverage.svg?job=coverage)](https://git.eit.uni-kl.de/ems/astdm/dram.sys/commits/master)
## Disclaimer
This is the public read-only mirror of an internal DRAMSys repository. Pull requests will not be merged but the changes might be added internally and published with a future commit. Both repositories are synchronized from time to time.
The user DOES NOT get ANY WARRANTIES when using this tool. This software is released under the BSD 3-Clause License. By using this software, the user implicitly agrees to the licensing terms.
If you decide to use DRAMSys in your research please cite the papers [2] [3]. To cite the TLM methodology of DRAMSys use the paper [1].
## Key Features
- **standalone** simulator with trace players, **gem5**-coupled simulator and **TLM-AT-compliant library**
@@ -18,10 +25,16 @@ Pipeline Status: [![pipeline status](https://git.eit.uni-kl.de/ems/astdm/dram.sy
- coupling to **DRAMPower** [4] and **3D-ICE** [8] for power and thermal simulation
- **Trace Analyzer** for visual and metric-based result analysis
## Architecture and Functionality
A UML diagram of the software architecture is presented below; different component implementations are left out for simplicity. More information about the architecture and functionality can be found in the papers [1] [2] [3] and in the introduction video on [Youtube](https://www.youtube.com/watch?v=8EkC3mYWpQY).
<img src="DRAMSys/docs/images/dramsys_uml.png" alt="UML" />
## Basic Setup
Start using DRAMSys by cloning the repository.
Use the *--recursive* flag to initialize all submodules within the repository, namely **DRAMPower**, **SystemC** and **nlohmann json**.
Use the `--recursive` flag to initialize all submodules within the repository, namely **DRAMPower**, **SystemC** and **nlohmann json**.
### Dependencies
@@ -134,7 +147,7 @@ Syntax example:
# [clock-cyle]: [write|read] [hex-address] [hex-data (optional)]
31: read 0x400140
33: read 0x400160
56: write 0x7fff8000 0x123456789abcdef
56: write 0x7fff8000 0x123456789abcdef...
81: read 0x400180
```
@@ -149,7 +162,7 @@ Syntax example:
# [clock-cyle]: [write|read] [hex-address] [hex-data (optional)]
31: read 0x400140
2: read 0x400160
23: write 0x7fff8000 0x123456789abcdef
23: write 0x7fff8000 0x123456789abcdef...
25: read 0x400180
```
@@ -184,8 +197,8 @@ The content of [ddr3.json](DRAMSys/library/resources/configs/simulator/ddr3.json
"ECCControllerMode": "Disabled",
"UseMalloc": false,
"AddressOffset": 0,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"ErrorCSVFile": "",
"StoreMode": "NoStorage"
}
}
@@ -222,10 +235,10 @@ The content of [ddr3.json](DRAMSys/library/resources/configs/simulator/ddr3.json
- *UseMalloc* (boolean)
- false: model storage using mmap() (DEFAULT)
- true: allocate memory for modeling storage using malloc()
- *AddressOffset* (unsigned int)
- Address offset of the DRAM subsystem (required for the gem5 coupling).
- *ErrorChipSeed* (unsigned int)
- Seed to initialize the random error generator.
- *AddressOffset* (unsigned int)
- Address offset of the DRAM subsystem (required for the gem5 coupling).
- *ErrorChipSeed* (unsigned int)
- Seed to initialize the random error generator.
- *ErrorCSVFile* (string)
- CSV file with error injection information.
- *StoreMode* (string)
@@ -380,13 +393,24 @@ $ unzip 3d-ice-latest.zip
$ cd 3d-ice-latest/3d-ice-2.2.6
```
Open the file makefile.def and set some variables.
Open the makefile.def and set the following variables properly, e.g.:
```bash
SLU_MAIN = $(HOME)/SuperLU_$(SLU_VERSION)
YACC = bison-2.4.1
SYSTEMC_ARCH = linux64
SYSTEMC_MAIN = $(HOME)/systemc-2.3.x
SYSTEMC_VERSION = 2.3.4
SYSTEMC_ARCH = linux64
SYSTEMC_MAIN = $(HOME)/systemc-$(SYSTEMC_VERSION)
SYSTEMC_INCLUDE = $(SYSTEMC_MAIN)/include
SYSTEMC_LIB = $(SYSTEMC_MAIN)/lib-$(SYSTEMC_ARCH)
```
In case you are using the SystemC submodule and DRAMSys is located in your home directory the variables should be set as follows:
```bash
SYSTEMC_INCLUDE = $(HOME)/DRAMSys/DRAMSys/library/src/common/third_party/systemc/src
SYSTEMC_LIB = $(HOME)/DRAMSys/build/library/src/common/third_party/systemc/src
```
Compile 3D-ICE with SystemC TLM-2.0 support:
@@ -482,7 +506,7 @@ The content of [config.json](DRAMSys/library/resources/configs/thermalsim/config
- true: generate power map files during thermal simulation
- false: do not generate power map files during thermal simulation
## Trace Analyzer
## Trace Analyzer Consulting and Custom-Tailored Modifications
To provide better analysis capabilities for DRAM subsystem design space exploration than the usual performance-related outputs to the console, DRAMSys offers the Trace Analyzer.
@@ -490,11 +514,13 @@ All requests, responses and DRAM commands can be recorded in an SQLite trace dat
The Trace Analyzer's main window is shown below.
If you are interested in the database recording feature and the Trace Analyzer please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de).
If you are interested in the database recording feature and the Trace Analyzer, if you need support on how to setup DRAMSys in a virtual platform of your company, or if you require custom modifications of the simulator please contact [Matthias Jung](mailto:matthias.jung@iese.fraunhofer.de).
![Trace Analyzer Main Window](DRAMSys/docs/images/traceanalyzer.png)
## List of Contributors
## Acknowledgements
The development of DRAMSys was supported by the German Research Foundation (DFG) as part of the priority program [Dependable Embedded Systems SPP1500](http://spp1500.itec.kit.edu) and the DFG grant no. [WE2442/10-1](https://www.uni-kl.de/en/3d-dram/). Furthermore, it was supported within the Fraunhofer and DFG cooperation program (grant no. [WE2442/14-1](https://www.iese.fraunhofer.de/en/innovation_trends/autonomous-systems/memtonomy.html)) and by the [Fraunhofer High Performance Center for Simulation- and Software-Based Innovation](https://www.leistungszentrum-simulation-software.de/en.html). Special thanks go to all listed contributors for their work and commitment during seven years of development.
Shama Bhosale
Luiza Correa
@@ -506,20 +532,14 @@ Matthias Jung
Frederik Lauer
Ana Mativi
Felipe S. Prado
Tran Anh Quoc
Janik Schlemminger
Lukas Steiner
Thanh C. Tran
Tran Anh Quoc
Norbert Wehn
Christian Weis
Éder F. Zulian
## Disclaimer
This is the public read-only mirror of an internal DRAMSys repository. Pull requests will not be merged but the changes might be added internally and published with a future commit. The repositories are synchronized from time to time.
The user DOES NOT get ANY WARRANTIES when using this tool. This software is released under the BSD 3-Clause License. By using this software, the user implicitly agrees to the licensing terms.
If you decide to use DRAMSys in your research please cite the paper [3].
## References
[1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration