Add LPDDR5 regression test
This commit is contained in:
@@ -1,216 +0,0 @@
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/*
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* Copyright (c) 2021, RPTU Kaiserslautern-Landau
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors:
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* Derek Christ
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*/
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#include <DRAMSys/config/DRAMSysConfiguration.h>
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#include <DRAMSys/util/json.h>
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#include <fstream>
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#include <iostream>
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using namespace DRAMSys::Config;
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DRAMSys::Config::AddressMapping getAddressMapping()
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{
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return DRAMSys::Config::AddressMapping{
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{{0, 1}},
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{{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}},
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{{16}},
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{{13, 14, 15}},
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{{17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}},
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{{33}},
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{{}},
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{{}}
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};
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}
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DRAMSys::Config::McConfig getMcConfig()
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{
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return McConfig{
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PagePolicy::Open,
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Scheduler::FrFcfs,
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0,
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0,
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SchedulerBuffer::Bankwise,
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8,
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CmdMux::Oldest,
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RespQueue::Fifo,
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RefreshPolicy::AllBank,
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0,
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0,
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PowerDownPolicy::NoPowerDown,
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Arbiter::Simple,
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128,
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{}
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};
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}
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DRAMSys::Config::SimConfig getSimConfig()
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{
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return DRAMSys::Config::SimConfig{
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0, false, true, false, false, {"error.csv"},
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42, false, {"ddr5"}, true, DRAMSys::Config::StoreMode::NoStorage, false, false,
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1000};
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}
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DRAMSys::Config::TracePlayer getTracePlayer()
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{
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DRAMSys::Config::TracePlayer player;
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player.clkMhz = 100;
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player.name = "mytrace.stl";
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return player;
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}
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DRAMSys::Config::TraceGenerator getTraceGeneratorOneState()
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{
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DRAMSys::Config::TraceGenerator gen;
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gen.clkMhz = 100;
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gen.name = "MyTestGen";
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DRAMSys::Config::TraceGeneratorTrafficState state0;
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state0.numRequests = 1000;
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state0.rwRatio = 0.5;
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state0.addressDistribution = DRAMSys::Config::AddressDistribution::Random;
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state0.addressIncrement = {};
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state0.minAddress = {};
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state0.maxAddress = {};
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state0.clksPerRequest = {};
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gen.states.emplace(0, state0);
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return gen;
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}
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DRAMSys::Config::TraceGenerator getTraceGeneratorMultipleStates()
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{
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DRAMSys::Config::TraceGenerator gen;
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gen.clkMhz = 100;
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gen.name = "MyTestGen";
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gen.maxPendingReadRequests = 8;
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DRAMSys::Config::TraceGeneratorTrafficState state0;
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state0.numRequests = 1000;
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state0.rwRatio = 0.5;
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state0.addressDistribution = DRAMSys::Config::AddressDistribution::Sequential;
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state0.addressIncrement = 256;
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state0.minAddress = {};
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state0.maxAddress = 1024;
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state0.clksPerRequest = {};
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DRAMSys::Config::TraceGeneratorTrafficState state1;
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state1.numRequests = 100;
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state1.rwRatio = 0.75;
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state1.addressDistribution = DRAMSys::Config::AddressDistribution::Sequential;
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state1.addressIncrement = 512;
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state1.minAddress = 1024;
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state1.maxAddress = 2048;
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state1.clksPerRequest = {};
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gen.states.emplace(0, state0);
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gen.states.emplace(1, state1);
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DRAMSys::Config::TraceGeneratorStateTransition transistion0{1, 1.0};
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gen.transitions.emplace(0, transistion0);
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return gen;
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}
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DRAMSys::Config::TraceHammer getTraceHammer()
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{
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DRAMSys::Config::TraceHammer hammer;
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hammer.clkMhz = 100;
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hammer.name = "MyTestHammer";
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hammer.numRequests = 4000;
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hammer.rowIncrement = 2097152;
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return hammer;
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}
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DRAMSys::Config::TraceSetup getTraceSetup()
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{
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using namespace DRAMSys::Config;
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std::vector<std::variant<TracePlayer, TraceGenerator, TraceHammer>> initiators;
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initiators.emplace_back(getTracePlayer());
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initiators.emplace_back(getTraceGeneratorOneState());
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initiators.emplace_back(getTraceGeneratorMultipleStates());
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initiators.emplace_back(getTraceHammer());
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return DRAMSys::Config::TraceSetup{initiators};
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}
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DRAMSys::Config::Configuration getConfig(const DRAMSys::Config::MemSpec &memSpec)
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{
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return DRAMSys::Config::Configuration{
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getAddressMapping(),
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getMcConfig(),
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memSpec,
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getSimConfig(),
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"std::string_simulationId",
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// {{}, false}, works too
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getTraceSetup(),
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};
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}
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int main()
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{
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DRAMSys::Config::Configuration conf = DRAMSys::Config::from_path("ddr5.json");
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std::ofstream fileout("myjson.json");
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json_t j_my;
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j_my["simulation"] = getConfig(conf.memSpec); // just copy memspec over
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fileout << j_my.dump(4);
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std::ifstream file2("hbm2.json");
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json_t hbm2_j = json_t::parse(file2, nullptr, false);
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json_t hbm2_config = hbm2_j.at("simulation");
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DRAMSys::Config::Configuration hbm2conf = hbm2_config.get<DRAMSys::Config::Configuration>();
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std::ofstream filehbm2("myhbm2.json");
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json_t j_myhbm2;
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j_myhbm2["simulation"] = hbm2conf;
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filehbm2 << j_myhbm2.dump(4);
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std::ifstream file3("myjson.json");
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json_t ddr5_old = json_t::parse(file3, nullptr, false);
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json_t ddr5_old_conf = ddr5_old.at("simulation");
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DRAMSys::Config::Configuration ddr5_old_config = ddr5_old_conf.get<DRAMSys::Config::Configuration>();
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std::ofstream fileoldout("myjson2.json");
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json_t j_oldconfconv;
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j_oldconfconv["simulation"] = ddr5_old_config;
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fileoldout << j_oldconfconv.dump(4);
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}
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@@ -54,6 +54,11 @@ set(TABLES_TO_COMPARE
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)
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function(test_standard standard test_name base_config resource_dir output_filename)
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if(NOT IS_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/${standard})
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message(WARNING "Cannot find regression test ${standard}")
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return()
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endif()
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# Put all the generated files into a subdirectory
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file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${test_name})
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@@ -95,6 +100,7 @@ test_standard(DDR4 DDR4 ${CMAKE_CURRENT_SOURCE_DIR}/DDR4/ddr4-example.json ${CMA
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test_standard(DDR5 DDR5.Ch0 ${CMAKE_CURRENT_SOURCE_DIR}/DDR5/ddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR5 DRAMSys_ddr5-example_ddr5_ch0.tdb)
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test_standard(DDR5 DDR5.Ch1 ${CMAKE_CURRENT_SOURCE_DIR}/DDR5/ddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR5 DRAMSys_ddr5-example_ddr5_ch1.tdb)
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test_standard(LPDDR4 LPDDR4 ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR4/lpddr4-example.json ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR4 DRAMSys_lpddr4-example_lpddr4_ch0.tdb)
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test_standard(LPDDR5 LPDDR5 ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR5/lpddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR5 DRAMSys_lpddr5-example_lpddr5_ch0.tdb)
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test_standard(HBM2 HBM2.Ch0 ${CMAKE_CURRENT_SOURCE_DIR}/HBM2/hbm2-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM2 DRAMSys_hbm2-example_hbm2_ch0.tdb)
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test_standard(HBM2 HBM2.Ch1 ${CMAKE_CURRENT_SOURCE_DIR}/HBM2/hbm2-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM2 DRAMSys_hbm2-example_hbm2_ch1.tdb)
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test_standard(HBM3 HBM3 ${CMAKE_CURRENT_SOURCE_DIR}/HBM3/hbm3-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM3 DRAMSys_hbm3-example_hbm3_ch0.tdb)
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BIN
tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb
LFS
Normal file
BIN
tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb
LFS
Normal file
Binary file not shown.
141
tests/tests_regression/LPDDR5/lpddr5-example.json
Normal file
141
tests/tests_regression/LPDDR5/lpddr5-example.json
Normal file
@@ -0,0 +1,141 @@
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{
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"simulation": {
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"addressmapping": {
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"BANKGROUP_BIT": [
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5,
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6
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],
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"BANK_BIT": [
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7,
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8
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],
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"BYTE_BIT": [
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0
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],
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"COLUMN_BIT": [
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1,
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2,
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3,
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4,
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9,
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10,
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11,
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12,
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13,
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14
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],
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"ROW_BIT": [
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15,
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16,
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17,
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18,
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19,
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20,
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21,
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22,
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23,
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24,
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25,
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26,
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27,
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28,
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29,
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30
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]
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},
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"mcconfig": {
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"Arbiter": "Simple",
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"CmdMux": "Oldest",
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"MaxActiveTransactions": 128,
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"PagePolicy": "Open",
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"PowerDownPolicy": "NoPowerDown",
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"RefreshManagement": false,
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"RefreshMaxPostponed": 0,
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"RefreshMaxPulledin": 0,
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"RefreshPolicy": "Per2Bank",
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"RequestBufferSize": 8,
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"RespQueue": "Fifo",
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"Scheduler": "FrFcfs",
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"SchedulerBuffer": "Bankwise"
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},
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"memspec": {
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"memarchitecturespec": {
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"burstLength": 16,
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"dataRate": 8,
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"nbrOfBankGroups": 4,
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"nbrOfBanks": 16,
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"nbrOfChannels": 1,
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"nbrOfColumns": 1024,
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"nbrOfDevices": 1,
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"nbrOfRanks": 1,
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"nbrOfRows": 65536,
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"per2BankOffset": 8,
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"width": 16
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},
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"memoryId": "JEDEC_1Gbx16_BG_LPDDR5-6400",
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"memoryType": "LPDDR5",
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"memtimingspec": {
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"BL_n_L_16": 4,
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"BL_n_L_32": 8,
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"BL_n_S_16": 2,
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"BL_n_S_32": 2,
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"BL_n_max_16": 4,
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"BL_n_max_32": 8,
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"BL_n_min_16": 2,
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"BL_n_min_32": 6,
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"CCDMW": 16,
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"FAW": 16,
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"PPD": 2,
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"RAS": 34,
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"RBTP": 4,
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"RCD_L": 15,
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"RCD_S": 15,
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"RCab": 51,
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"RCpb": 48,
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"REFI": 3124,
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"REFIpb": 390,
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"RFCab": 224,
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"RFCpb": 112,
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"RL": 17,
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"RPRE": 0,
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"RPST": 0,
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"RPab": 17,
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"RPpb": 15,
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"RRD": 4,
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"RTRS": 1,
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"WCK2CK": 0,
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"WCK2DQI": 0,
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"WCK2DQO": 1,
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"WL": 9,
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"WPRE": 0,
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"WPST": 0,
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"WR": 28,
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"WTR_L": 10,
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"WTR_S": 5,
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"clkMhz": 800,
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"pbR2act": 6,
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"pbR2pbR": 72
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}
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},
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"simconfig": {
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"AddressOffset": 0,
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"CheckTLM2Protocol": false,
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"DatabaseRecording": true,
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"Debug": false,
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"EnableWindowing": false,
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"PowerAnalysis": false,
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"SimulationName": "example",
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"SimulationProgressBar": true,
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"StoreMode": "NoStorage",
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"UseMalloc": false,
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"WindowSize": 1000
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},
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"simulationid": "lpddr5-example",
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"tracesetup": [
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{
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"clkMhz": 1600,
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"name": "trace_lpddr5.stl"
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}
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]
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}
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}
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BIN
tests/tests_regression/LPDDR5/traces/trace_lpddr5.stl
LFS
Normal file
BIN
tests/tests_regression/LPDDR5/traces/trace_lpddr5.stl
LFS
Normal file
Binary file not shown.
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