diff --git a/tests/tests_configuration/simpletest.cpp b/tests/tests_configuration/simpletest.cpp deleted file mode 100644 index 6138808b..00000000 --- a/tests/tests_configuration/simpletest.cpp +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (c) 2021, RPTU Kaiserslautern-Landau - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: - * Derek Christ - */ - -#include - -#include - -#include -#include - -using namespace DRAMSys::Config; - -DRAMSys::Config::AddressMapping getAddressMapping() -{ - return DRAMSys::Config::AddressMapping{ - {{0, 1}}, - {{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}}, - {{16}}, - {{13, 14, 15}}, - {{17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}}, - {{33}}, - {{}}, - {{}} - }; -} - -DRAMSys::Config::McConfig getMcConfig() -{ - return McConfig{ - PagePolicy::Open, - Scheduler::FrFcfs, - 0, - 0, - SchedulerBuffer::Bankwise, - 8, - CmdMux::Oldest, - RespQueue::Fifo, - RefreshPolicy::AllBank, - 0, - 0, - PowerDownPolicy::NoPowerDown, - Arbiter::Simple, - 128, - {} - }; -} - -DRAMSys::Config::SimConfig getSimConfig() -{ - return DRAMSys::Config::SimConfig{ - 0, false, true, false, false, {"error.csv"}, - 42, false, {"ddr5"}, true, DRAMSys::Config::StoreMode::NoStorage, false, false, - 1000}; -} - -DRAMSys::Config::TracePlayer getTracePlayer() -{ - DRAMSys::Config::TracePlayer player; - player.clkMhz = 100; - player.name = "mytrace.stl"; - - return player; -} - -DRAMSys::Config::TraceGenerator getTraceGeneratorOneState() -{ - DRAMSys::Config::TraceGenerator gen; - gen.clkMhz = 100; - gen.name = "MyTestGen"; - - DRAMSys::Config::TraceGeneratorTrafficState state0; - state0.numRequests = 1000; - state0.rwRatio = 0.5; - state0.addressDistribution = DRAMSys::Config::AddressDistribution::Random; - state0.addressIncrement = {}; - state0.minAddress = {}; - state0.maxAddress = {}; - state0.clksPerRequest = {}; - - gen.states.emplace(0, state0); - - return gen; -} - -DRAMSys::Config::TraceGenerator getTraceGeneratorMultipleStates() -{ - DRAMSys::Config::TraceGenerator gen; - - gen.clkMhz = 100; - gen.name = "MyTestGen"; - gen.maxPendingReadRequests = 8; - - DRAMSys::Config::TraceGeneratorTrafficState state0; - state0.numRequests = 1000; - state0.rwRatio = 0.5; - state0.addressDistribution = DRAMSys::Config::AddressDistribution::Sequential; - state0.addressIncrement = 256; - state0.minAddress = {}; - state0.maxAddress = 1024; - state0.clksPerRequest = {}; - - DRAMSys::Config::TraceGeneratorTrafficState state1; - state1.numRequests = 100; - state1.rwRatio = 0.75; - state1.addressDistribution = DRAMSys::Config::AddressDistribution::Sequential; - state1.addressIncrement = 512; - state1.minAddress = 1024; - state1.maxAddress = 2048; - state1.clksPerRequest = {}; - - gen.states.emplace(0, state0); - gen.states.emplace(1, state1); - - DRAMSys::Config::TraceGeneratorStateTransition transistion0{1, 1.0}; - - gen.transitions.emplace(0, transistion0); - - return gen; -} - -DRAMSys::Config::TraceHammer getTraceHammer() -{ - DRAMSys::Config::TraceHammer hammer; - - hammer.clkMhz = 100; - hammer.name = "MyTestHammer"; - hammer.numRequests = 4000; - hammer.rowIncrement = 2097152; - - return hammer; -} - -DRAMSys::Config::TraceSetup getTraceSetup() -{ - using namespace DRAMSys::Config; - - std::vector> initiators; - initiators.emplace_back(getTracePlayer()); - initiators.emplace_back(getTraceGeneratorOneState()); - initiators.emplace_back(getTraceGeneratorMultipleStates()); - initiators.emplace_back(getTraceHammer()); - - return DRAMSys::Config::TraceSetup{initiators}; -} - -DRAMSys::Config::Configuration getConfig(const DRAMSys::Config::MemSpec &memSpec) -{ - return DRAMSys::Config::Configuration{ - getAddressMapping(), - getMcConfig(), - memSpec, - getSimConfig(), - "std::string_simulationId", - // {{}, false}, works too - getTraceSetup(), - }; -} - -int main() -{ - DRAMSys::Config::Configuration conf = DRAMSys::Config::from_path("ddr5.json"); - std::ofstream fileout("myjson.json"); - json_t j_my; - j_my["simulation"] = getConfig(conf.memSpec); // just copy memspec over - fileout << j_my.dump(4); - - std::ifstream file2("hbm2.json"); - json_t hbm2_j = json_t::parse(file2, nullptr, false); - json_t hbm2_config = hbm2_j.at("simulation"); - DRAMSys::Config::Configuration hbm2conf = hbm2_config.get(); - std::ofstream filehbm2("myhbm2.json"); - json_t j_myhbm2; - j_myhbm2["simulation"] = hbm2conf; - filehbm2 << j_myhbm2.dump(4); - - std::ifstream file3("myjson.json"); - json_t ddr5_old = json_t::parse(file3, nullptr, false); - json_t ddr5_old_conf = ddr5_old.at("simulation"); - DRAMSys::Config::Configuration ddr5_old_config = ddr5_old_conf.get(); - std::ofstream fileoldout("myjson2.json"); - json_t j_oldconfconv; - j_oldconfconv["simulation"] = ddr5_old_config; - fileoldout << j_oldconfconv.dump(4); -} diff --git a/tests/tests_regression/CMakeLists.txt b/tests/tests_regression/CMakeLists.txt index 394ecc5c..c87dd68a 100644 --- a/tests/tests_regression/CMakeLists.txt +++ b/tests/tests_regression/CMakeLists.txt @@ -54,6 +54,11 @@ set(TABLES_TO_COMPARE ) function(test_standard standard test_name base_config resource_dir output_filename) + if(NOT IS_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/${standard}) + message(WARNING "Cannot find regression test ${standard}") + return() + endif() + # Put all the generated files into a subdirectory file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${test_name}) @@ -95,6 +100,7 @@ test_standard(DDR4 DDR4 ${CMAKE_CURRENT_SOURCE_DIR}/DDR4/ddr4-example.json ${CMA test_standard(DDR5 DDR5.Ch0 ${CMAKE_CURRENT_SOURCE_DIR}/DDR5/ddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR5 DRAMSys_ddr5-example_ddr5_ch0.tdb) test_standard(DDR5 DDR5.Ch1 ${CMAKE_CURRENT_SOURCE_DIR}/DDR5/ddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR5 DRAMSys_ddr5-example_ddr5_ch1.tdb) test_standard(LPDDR4 LPDDR4 ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR4/lpddr4-example.json ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR4 DRAMSys_lpddr4-example_lpddr4_ch0.tdb) +test_standard(LPDDR5 LPDDR5 ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR5/lpddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR5 DRAMSys_lpddr5-example_lpddr5_ch0.tdb) test_standard(HBM2 HBM2.Ch0 ${CMAKE_CURRENT_SOURCE_DIR}/HBM2/hbm2-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM2 DRAMSys_hbm2-example_hbm2_ch0.tdb) test_standard(HBM2 HBM2.Ch1 ${CMAKE_CURRENT_SOURCE_DIR}/HBM2/hbm2-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM2 DRAMSys_hbm2-example_hbm2_ch1.tdb) test_standard(HBM3 HBM3 ${CMAKE_CURRENT_SOURCE_DIR}/HBM3/hbm3-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM3 DRAMSys_hbm3-example_hbm3_ch0.tdb) diff --git a/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb b/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb new file mode 100644 index 00000000..b2c11196 --- /dev/null +++ b/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:64acfb8c773c65c91a3bcad996419de80cff7780378a663c9ead2e53da0030c2 +size 2826240 diff --git a/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr5-example_lpddr5_ch0.tdb b/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr5-example_lpddr5_ch0.tdb new file mode 100644 index 00000000..e69de29b diff --git a/tests/tests_regression/LPDDR5/lpddr5-example.json b/tests/tests_regression/LPDDR5/lpddr5-example.json new file mode 100644 index 00000000..0c07fa7d --- /dev/null +++ b/tests/tests_regression/LPDDR5/lpddr5-example.json @@ -0,0 +1,141 @@ +{ + "simulation": { + "addressmapping": { + "BANKGROUP_BIT": [ + 5, + 6 + ], + "BANK_BIT": [ + 7, + 8 + ], + "BYTE_BIT": [ + 0 + ], + "COLUMN_BIT": [ + 1, + 2, + 3, + 4, + 9, + 10, + 11, + 12, + 13, + 14 + ], + "ROW_BIT": [ + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30 + ] + }, + "mcconfig": { + "Arbiter": "Simple", + "CmdMux": "Oldest", + "MaxActiveTransactions": 128, + "PagePolicy": "Open", + "PowerDownPolicy": "NoPowerDown", + "RefreshManagement": false, + "RefreshMaxPostponed": 0, + "RefreshMaxPulledin": 0, + "RefreshPolicy": "Per2Bank", + "RequestBufferSize": 8, + "RespQueue": "Fifo", + "Scheduler": "FrFcfs", + "SchedulerBuffer": "Bankwise" + }, + "memspec": { + "memarchitecturespec": { + "burstLength": 16, + "dataRate": 8, + "nbrOfBankGroups": 4, + "nbrOfBanks": 16, + "nbrOfChannels": 1, + "nbrOfColumns": 1024, + "nbrOfDevices": 1, + "nbrOfRanks": 1, + "nbrOfRows": 65536, + "per2BankOffset": 8, + "width": 16 + }, + "memoryId": "JEDEC_1Gbx16_BG_LPDDR5-6400", + "memoryType": "LPDDR5", + "memtimingspec": { + "BL_n_L_16": 4, + "BL_n_L_32": 8, + "BL_n_S_16": 2, + "BL_n_S_32": 2, + "BL_n_max_16": 4, + "BL_n_max_32": 8, + "BL_n_min_16": 2, + "BL_n_min_32": 6, + "CCDMW": 16, + "FAW": 16, + "PPD": 2, + "RAS": 34, + "RBTP": 4, + "RCD_L": 15, + "RCD_S": 15, + "RCab": 51, + "RCpb": 48, + "REFI": 3124, + "REFIpb": 390, + "RFCab": 224, + "RFCpb": 112, + "RL": 17, + "RPRE": 0, + "RPST": 0, + "RPab": 17, + "RPpb": 15, + "RRD": 4, + "RTRS": 1, + "WCK2CK": 0, + "WCK2DQI": 0, + "WCK2DQO": 1, + "WL": 9, + "WPRE": 0, + "WPST": 0, + "WR": 28, + "WTR_L": 10, + "WTR_S": 5, + "clkMhz": 800, + "pbR2act": 6, + "pbR2pbR": 72 + } + }, + "simconfig": { + "AddressOffset": 0, + "CheckTLM2Protocol": false, + "DatabaseRecording": true, + "Debug": false, + "EnableWindowing": false, + "PowerAnalysis": false, + "SimulationName": "example", + "SimulationProgressBar": true, + "StoreMode": "NoStorage", + "UseMalloc": false, + "WindowSize": 1000 + }, + "simulationid": "lpddr5-example", + "tracesetup": [ + { + "clkMhz": 1600, + "name": "trace_lpddr5.stl" + } + ] + } +} \ No newline at end of file diff --git a/tests/tests_regression/LPDDR5/traces/trace_lpddr5.stl b/tests/tests_regression/LPDDR5/traces/trace_lpddr5.stl new file mode 100644 index 00000000..1b3f9958 --- /dev/null +++ b/tests/tests_regression/LPDDR5/traces/trace_lpddr5.stl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:69b0d83057ff4da0f60f8f66e2f253c94f6744efcd71ece8ee2e1eaa5111c634 +size 254470