Add LPDDR5 regression test

2023-07-06 10:46:02 +02:00
parent 81eaccf3d6
commit 0fc74e93c4
6 changed files with 153 additions and 216 deletions
--- a/tests/tests_regression/CMakeLists.txt
+++ b/tests/tests_regression/CMakeLists.txt
@@ -54,6 +54,11 @@ set(TABLES_TO_COMPARE
 )

 function(test_standard standard test_name base_config resource_dir output_filename)
+    if(NOT IS_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/${standard})
+        message(WARNING "Cannot find regression test ${standard}")
+        return()
+    endif()
+
    # Put all the generated files into a subdirectory
    file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${test_name})

@@ -95,6 +100,7 @@ test_standard(DDR4 DDR4 ${CMAKE_CURRENT_SOURCE_DIR}/DDR4/ddr4-example.json ${CMA
 test_standard(DDR5 DDR5.Ch0 ${CMAKE_CURRENT_SOURCE_DIR}/DDR5/ddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR5 DRAMSys_ddr5-example_ddr5_ch0.tdb)
 test_standard(DDR5 DDR5.Ch1 ${CMAKE_CURRENT_SOURCE_DIR}/DDR5/ddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR5 DRAMSys_ddr5-example_ddr5_ch1.tdb)
 test_standard(LPDDR4 LPDDR4 ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR4/lpddr4-example.json ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR4 DRAMSys_lpddr4-example_lpddr4_ch0.tdb)
+test_standard(LPDDR5 LPDDR5 ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR5/lpddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR5 DRAMSys_lpddr5-example_lpddr5_ch0.tdb)
 test_standard(HBM2 HBM2.Ch0 ${CMAKE_CURRENT_SOURCE_DIR}/HBM2/hbm2-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM2 DRAMSys_hbm2-example_hbm2_ch0.tdb)
 test_standard(HBM2 HBM2.Ch1 ${CMAKE_CURRENT_SOURCE_DIR}/HBM2/hbm2-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM2 DRAMSys_hbm2-example_hbm2_ch1.tdb)
 test_standard(HBM3 HBM3 ${CMAKE_CURRENT_SOURCE_DIR}/HBM3/hbm3-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM3 DRAMSys_hbm3-example_hbm3_ch0.tdb)
--- a/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb
+++ b/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb
--- a/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr5-example_lpddr5_ch0.tdb
+++ b/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr5-example_lpddr5_ch0.tdb
--- a/tests/tests_regression/LPDDR5/lpddr5-example.json
+++ b/tests/tests_regression/LPDDR5/lpddr5-example.json
@@ -0,0 +1,141 @@
+{
+    "simulation": {
+        "addressmapping": {
+            "BANKGROUP_BIT": [
+                5,
+                6
+            ],
+            "BANK_BIT": [
+                7,
+                8
+            ],
+            "BYTE_BIT": [
+                0
+            ],
+            "COLUMN_BIT": [
+                1,
+                2,
+                3,
+                4,
+                9,
+                10,
+                11,
+                12,
+                13,
+                14
+            ],
+            "ROW_BIT": [
+                15,
+                16,
+                17,
+                18,
+                19,
+                20,
+                21,
+                22,
+                23,
+                24,
+                25,
+                26,
+                27,
+                28,
+                29,
+                30
+            ]
+        },
+        "mcconfig": {
+            "Arbiter": "Simple",
+            "CmdMux": "Oldest",
+            "MaxActiveTransactions": 128,
+            "PagePolicy": "Open",
+            "PowerDownPolicy": "NoPowerDown",
+            "RefreshManagement": false,
+            "RefreshMaxPostponed": 0,
+            "RefreshMaxPulledin": 0,
+            "RefreshPolicy": "Per2Bank",
+            "RequestBufferSize": 8,
+            "RespQueue": "Fifo",
+            "Scheduler": "FrFcfs",
+            "SchedulerBuffer": "Bankwise"
+        },
+        "memspec": {
+            "memarchitecturespec": {
+                "burstLength": 16,
+                "dataRate": 8,
+                "nbrOfBankGroups": 4,
+                "nbrOfBanks": 16,
+                "nbrOfChannels": 1,
+                "nbrOfColumns": 1024,
+                "nbrOfDevices": 1,
+                "nbrOfRanks": 1,
+                "nbrOfRows": 65536,
+                "per2BankOffset": 8,
+                "width": 16
+            },
+            "memoryId": "JEDEC_1Gbx16_BG_LPDDR5-6400",
+            "memoryType": "LPDDR5",
+            "memtimingspec": {
+                "BL_n_L_16": 4,
+                "BL_n_L_32": 8,
+                "BL_n_S_16": 2,
+                "BL_n_S_32": 2,
+                "BL_n_max_16": 4,
+                "BL_n_max_32": 8,
+                "BL_n_min_16": 2,
+                "BL_n_min_32": 6,
+                "CCDMW": 16,
+                "FAW": 16,
+                "PPD": 2,
+                "RAS": 34,
+                "RBTP": 4,
+                "RCD_L": 15,
+                "RCD_S": 15,
+                "RCab": 51,
+                "RCpb": 48,
+                "REFI": 3124,
+                "REFIpb": 390,
+                "RFCab": 224,
+                "RFCpb": 112,
+                "RL": 17,
+                "RPRE": 0,
+                "RPST": 0,
+                "RPab": 17,
+                "RPpb": 15,
+                "RRD": 4,
+                "RTRS": 1,
+                "WCK2CK": 0,
+                "WCK2DQI": 0,
+                "WCK2DQO": 1,
+                "WL": 9,
+                "WPRE": 0,
+                "WPST": 0,
+                "WR": 28,
+                "WTR_L": 10,
+                "WTR_S": 5,
+                "clkMhz": 800,
+                "pbR2act": 6,
+                "pbR2pbR": 72
+            }
+        },
+        "simconfig": {
+            "AddressOffset": 0,
+            "CheckTLM2Protocol": false,
+            "DatabaseRecording": true,
+            "Debug": false,
+            "EnableWindowing": false,
+            "PowerAnalysis": false,
+            "SimulationName": "example",
+            "SimulationProgressBar": true,
+            "StoreMode": "NoStorage",
+            "UseMalloc": false,
+            "WindowSize": 1000
+        },
+        "simulationid": "lpddr5-example",
+        "tracesetup": [
+            {
+                "clkMhz": 1600,
+                "name": "trace_lpddr5.stl"
+            }
+        ]
+    }
+}
--- a/tests/tests_regression/LPDDR5/traces/trace_lpddr5.stl
+++ b/tests/tests_regression/LPDDR5/traces/trace_lpddr5.stl