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Removed old resource files.

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This commit is contained in:
Lukas Steiner
2020-06-04 15:58:09 +02:00
parent 0f68b148e1
commit 0f302b8e80
40 changed files with 152 additions and 4758 deletions
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4
DRAMSys/gem5/configs/configs.pri
View File

@@ -1,4 +0,0 @@
DISTFILES += dualElasticTraceReplay.ini
DISTFILES += nvdimmp.ini
DISTFILES += singleElasticTraceReplay.ini

155
DRAMSys/library/CMakeLists.txt
View File

@@ -64,23 +64,23 @@ else()
message("-- Building with SystemC submodule")
endif()
include_directories(
src/common
src/common/third_party/DRAMPower/src
src/configuration
src/configuration/memspec
src/controller
src/controller/checker
src/controller/cmdmux
src/controller/powerdown
src/controller/refresh
src/controller/respqueue
src/controller/scheduler
src/error
src/error/ECC
src/simulation
src/simulation/dram
)
#include_directories(
# src/common
# src/common/third_party/DRAMPower/src
# src/configuration
# src/configuration/memspec
# src/controller
# src/controller/checker
# src/controller/cmdmux
# src/controller/powerdown
# src/controller/refresh
# src/controller/respqueue
# src/controller/scheduler
# src/error
# src/error/ECC
# src/simulation
# src/simulation/dram
#)
if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/src/simulation/DRAMSysRecordable.cpp)
set(RECORDING_SOURCES
@@ -174,6 +174,127 @@ add_library(DRAMSysLibrary
src/simulation/dram/DramHBM2.cpp
${RECORDING_SOURCES}
# Simulation Config Files
resources/simulations/ddr3-boot-linux.json
resources/simulations/ddr3-ecc.json
resources/simulations/ddr3-example2.json
resources/simulations/ddr3-example.json
resources/simulations/ddr3-gem5-se.json
resources/simulations/ddr3_postpone_ref_test.json
resources/simulations/ddr3-single-device.json
resources/simulations/ddr4-example.json
resources/simulations/hbm2-example.json
resources/simulations/lpddr4-example.json
resources/simulations/ranktest.json
resources/simulations/wideio-example.json
# Address Mapping Config Files
resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.json
resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.json
resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.json
resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.json
resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.json
resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.json
resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.json
resources/configs/amconfigs/am_ddr3_x16_brc.json
resources/configs/amconfigs/am_ddr3_x16_rbc.json
resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json
resources/configs/amconfigs/am_hbm2_8Gb_pc_brc.json
resources/configs/amconfigs/am_lpddr4_8Gbx16_brc.json
resources/configs/amconfigs/am_ranktest.json
resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_brc.json
resources/configs/amconfigs/am_wideio2_4x64_4x2Gb_rbc.json
resources/configs/amconfigs/am_wideio_4x1Gb_brc.json
resources/configs/amconfigs/am_wideio_4x1Gb_rbc.json
resources/configs/amconfigs/am_wideio_4x256Mb_brc.json
resources/configs/amconfigs/am_wideio_4x256Mb_rbc.json
resources/configs/amconfigs/am_wideio_4x2Gb_brc.json
resources/configs/amconfigs/am_wideio_4x2Gb_rbc.json
resources/configs/amconfigs/am_wideio_4x4Gb_brc.json
resources/configs/amconfigs/am_wideio_4x4Gb_rbc.json
resources/configs/amconfigs/am_wideio_4x512Mb_brc.json
resources/configs/amconfigs/am_wideio_4x512Mb_rbc.json
# Memory Controller Config Files
resources/configs/mcconfigs/fifo.json
resources/configs/mcconfigs/fifoStrict.json
resources/configs/mcconfigs/fr_fcfs_grp.json
resources/configs/mcconfigs/fr_fcfs.json
# Memspec Config Files
resources/configs/memspecs/HBM2.json
resources/configs/memspecs/JEDEC_256Mb_WIDEIO-200_128bit.json
resources/configs/memspecs/JEDEC_256Mb_WIDEIO-266_128bit.json
resources/configs/memspecs/JEDEC_4Gb_DDR4-1866_8bit_A.json
resources/configs/memspecs/JEDEC_4Gb_DDR4-2400_8bit_A.json
resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-400_64bit.json
resources/configs/memspecs/JEDEC_4x64_2Gb_WIDEIO2-533_64bit.json
resources/configs/memspecs/JEDEC_8Gb_LPDDR4-3200_16bit.json
resources/configs/memspecs/memspec_ranktest.json
resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.json
resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.json
resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.json
resources/configs/memspecs/MICRON_1Gb_DDR3-800_8bit_G.json
resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_D_SODIMM.json
resources/configs/memspecs/MICRON_2GB_DDR3-1066_64bit_G_UDIMM.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.json
resources/configs/memspecs/MICRON_2GB_DDR3-1333_64bit_D_SODIMM.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.json
resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.json
resources/configs/memspecs/MICRON_2GB_DDR3-1600_64bit_G_UDIMM.json
resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.json
resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.json
resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.json
resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.json
resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.json
resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.json
resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.json
resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.json
resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_32bit_A.json
resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.json
resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.json
# Simulator Config Files
resources/configs/simulator/ddr3_boot_linux.json
resources/configs/simulator/ddr3_ecc.json
resources/configs/simulator/ddr3.json
resources/configs/simulator/ddr3_gem5_se.json
resources/configs/simulator/ddr3-single-device.json
resources/configs/simulator/ddr4.json
resources/configs/simulator/hbm2.json
resources/configs/simulator/lpddr4.json
resources/configs/simulator/wideio.json
# Thermal Simulation Config Files
resources/configs/thermalsim/config.json
# Trace Files
resources/traces/test_ecc.stl
resources/traces/ddr3_example.stl
resources/traces/ddr3_single_dev_example.stl
resources/traces/ddr3_postpone_ref_test_1.stl
resources/traces/ranktest.stl
resources/traces/chstone-adpcm_32.stl
)
# Build:

42
DRAMSys/library/resources/configs/amconfigs/am_ddr3.json
View File

@@ -1,42 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

37
DRAMSys/library/resources/configs/amconfigs/am_ddr4.json
View File

@@ -1,37 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
5,
6,
7,
8
],
"COLUMN_BIT": [
9,
10,
11,
12,
13,
14,
15,
16,
17,
18
],
"ROW_BIT": [
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31
]
}
}

8
DRAMSys/library/resources/configs/amconfigs/am_ddr4_8x4Gbx8_dimm_p1KB_brc.json
View File

@@ -1,13 +1,13 @@
{
"CONGEN": {
"BANKGROUP_BIT":[
30,
31
],
"BANK_BIT": [
28,
29
],
"BANK_BIT": [
30,
31
],
"BYTE_BIT": [
0,
1,

37
DRAMSys/library/resources/configs/amconfigs/am_highHits.json
View File

@@ -1,37 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
15,
16,
17,
18
],
"COLUMN_BIT": [
5,
6,
7,
8,
9,
10,
11,
12,
13,
14
],
"ROW_BIT": [
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31
]
}
}

37
DRAMSys/library/resources/configs/amconfigs/am_highPara.json
View File

@@ -1,37 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
5,
6,
7,
8
],
"COLUMN_BIT": [
9,
10,
11,
12,
13,
14,
15,
16,
17,
18
],
"ROW_BIT": [
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31
]
}
}

37
DRAMSys/library/resources/configs/amconfigs/am_lowHits.json
View File

@@ -1,37 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
5,
6,
7,
8
],
"COLUMN_BIT": [
24,
25,
26,
27,
28,
29,
30,
31
],
"ROW_BIT": [
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23
]
}
}

37
DRAMSys/library/resources/configs/amconfigs/am_lowPara.json
View File

@@ -1,37 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
30,
31
],
"COLUMN_BIT": [
5,
6,
7,
8,
9,
10,
11,
12,
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

43
DRAMSys/library/resources/configs/amconfigs/am_wideio.json
View File

@@ -1,43 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12,
13
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
27,
28
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

43
DRAMSys/library/resources/configs/amconfigs/am_wideioFourBanks.json
View File

@@ -1,43 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12
],
"BYTE_BIT": [
0,
1,
2,
3
],
"CHANNEL_BIT": [
27,
28
],
"COLUMN_BIT": [
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

45
DRAMSys/library/resources/configs/amconfigs/orgr_ddr4_4x16Gbx16_dimm_p2KB_brc.json
View File

@@ -1,45 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
30,
31,
32
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

45
DRAMSys/library/resources/configs/amconfigs/rgram-rbc.json
View File

@@ -1,45 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
13,
14,
15
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32
]
}
}

45
DRAMSys/library/resources/configs/amconfigs/rgram.json
View File

@@ -1,45 +0,0 @@
{
"CONGEN": {
"BANK_BIT": [
30,
31,
32
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
6,
7,
8,
9,
10,
11,
12
],
"ROW_BIT": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

66
DRAMSys/library/resources/configs/memspecs/DDR4.json
View File

@@ -1,66 +0,0 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 2,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 32768,
"width": 8
},
"memoryId": "MICRON_4Gb_DDR4-2400_8bit_A",
"memoryType": "DDR4",
"mempowerspec": {
"idd0": 60.75,
"idd02": 4.05,
"idd2n": 38.25,
"idd2p0": 17.0,
"idd2p1": 17.0,
"idd3n": 44.0,
"idd3p0": 22.5,
"idd3p1": 22.5,
"idd4r": 184.5,
"idd4w": 168.75,
"idd5": 118.0,
"idd6": 20.25,
"idd62": 2.6,
"vdd": 1.2,
"vdd2": 2.5
},
"memtimingspec": {
"AL": 0,
"CCD_L": 6,
"CCD_S": 4,
"CKE": 6,
"CKESR": 7,
"CL": 16,
"DQSCK": 2,
"FAW": 26,
"RAS": 39,
"RC": 55,
"RCD": 16,
"REFI": 4680,
"RFC": 313,
"RL": 16,
"RP": 16,
"RRD_L": 6,
"RRD_S": 4,
"RTP": 12,
"WL": 16,
"WR": 18,
"WTR_L": 9,
"WTR_S": 3,
"XP": 8,
"XPDLL": 325,
"XS": 324,
"XSDLL": 512,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"RTRS": 1,
"clkMhz": 1200
}
}
}

59
DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4.json
View File

@@ -1,59 +0,0 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16
},
"memoryId": "orgr_16Gb_DDR4_16bit",
"memoryType": "DDR3",
"mempowerspec": {
"idd0": 210.5,
"idd2n": 99.0,
"idd2p0": 16.0,
"idd2p1": 55.0,
"idd3n": 115.0,
"idd3p0": 70.0,
"idd3p1": 70.0,
"idd4r": 1470.8,
"idd4w": 1511.4,
"idd5": 2000.0,
"idd6": 22.0,
"vdd": 1.2
},
"memtimingspec": {
"AL": 0,
"CCD": 4,
"CKE": 8,
"CKESR": 8,
"CL": 15,
"DQSCK": 0,
"FAW": 37,
"RAS": 34,
"RC": 52,
"RCD": 18,
"REFI": 9361,
"RFC": 673,
"RL": 18,
"RP": 18,
"RRD": 8,
"RTP": 6,
"WL": 12,
"WR": 15,
"WTR": 8,
"XP": 4,
"XPDLL": 13,
"XS": 64,
"XSDLL": 512,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"RTRS": 1,
"clkMhz": 1200
}
}
}

59
DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4_2x.json
View File

@@ -1,59 +0,0 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16
},
"memoryId": "orgr_16Gb_DDR4_16bit",
"memoryType": "DDR3",
"mempowerspec": {
"idd0": 210.5,
"idd2n": 99.0,
"idd2p0": 16.0,
"idd2p1": 55.0,
"idd3n": 115.0,
"idd3p0": 70.0,
"idd3p1": 70.0,
"idd4r": 1470.8,
"idd4w": 1511.4,
"idd5": 1446.0,
"idd6": 22.0,
"vdd": 1.2
},
"memtimingspec": {
"AL": 0,
"CCD": 4,
"CKE": 8,
"CKESR": 8,
"CL": 15,
"DQSCK": 0,
"FAW": 37,
"RAS": 34,
"RC": 52,
"RCD": 18,
"REFI": 4681,
"RFC": 421,
"RL": 18,
"RP": 18,
"RRD": 8,
"RTP": 6,
"WL": 12,
"WR": 15,
"WTR": 8,
"XP": 4,
"XPDLL": 13,
"XS": 64,
"XSDLL": 512,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"RTRS": 1,
"clkMhz": 1200
}
}
}

59
DRAMSys/library/resources/configs/memspecs/orgr_16Gb_ddr4_4x.json
View File

@@ -1,59 +0,0 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16
},
"memoryId": "orgr_16Gb_DDR4_16bit",
"memoryType": "DDR3",
"mempowerspec": {
"idd0": 210.5,
"idd2n": 99.0,
"idd2p0": 16.0,
"idd2p1": 55.0,
"idd3n": 115.0,
"idd3p0": 70.0,
"idd3p1": 70.0,
"idd4r": 1470.8,
"idd4w": 1511.4,
"idd5": 1226.0,
"idd6": 22.0,
"vdd": 1.2
},
"memtimingspec": {
"AL": 0,
"CCD": 4,
"CKE": 8,
"CKESR": 8,
"CL": 15,
"DQSCK": 0,
"FAW": 37,
"RAS": 34,
"RC": 52,
"RCD": 18,
"REFI": 2341,
"RFC": 313,
"RL": 18,
"RP": 18,
"RRD": 8,
"RTP": 6,
"WL": 12,
"WR": 15,
"WTR": 8,
"XP": 4,
"XPDLL": 13,
"XS": 64,
"XSDLL": 512,
"ACTPDEN": 2,
"PRPDEN": 2,
"REFPDEN": 2,
"RTRS": 1,
"clkMhz": 1200
}
}
}

67
DRAMSys/library/resources/configs/memspecs/rgrspec.json
View File

@@ -1,67 +0,0 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 2,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16
},
"memoryId": "rgrspec",
"memoryType": "DDR4",
"mempowerspec": {
"idd0": 210.5,
"idd02": 4.05,
"idd2n": 99.0,
"idd2p0": 16.0,
"idd2p1": 55.0,
"idd3n": 115.0,
"idd3p0": 70.0,
"idd3p1": 70.0,
"idd4r": 1470.8,
"idd4w": 1511.4,
"idd5": 2000.0,
"idd6": 22.0,
"idd62": 2.6,
"vdd": 1.2,
"vdd2": 2.5
},
"memtimingspec": {
"AL": 0,
"CCD": 4,
"CCD_L": 6,
"CCD_S": 4,
"CKE": 8,
"CKESR": 8,
"CL": 15,
"DQSCK": 0,
"FAW": 37,
"RAS": 34,
"RC": 52,
"RCD": 18,
"REFI": 9364,
"RFC": 673,
"RFC2": 420,
"RFC4": 312,
"RL": 18,
"RP": 18,
"RRD": 8,
"RRD_L": 6,
"RRD_S": 4,
"RTP": 6,
"WL": 12,
"WR": 15,
"WTR": 8,
"WTR_L": 9,
"WTR_S": 3,
"XP": 4,
"XPDLL": 13,
"XS": 64,
"XSDLL": 512,
"clkMhz": 1200
}
}
}

40
DRAMSys/library/resources/configs/simulator/orgr.json
View File

@@ -1,40 +0,0 @@
{
"simconfig": {
"ControllerCoreRGR": true,
"ControllerCoreRGRB0": true,
"ControllerCoreRGRB1": true,
"ControllerCoreRGRB10": false,
"ControllerCoreRGRB11": false,
"ControllerCoreRGRB12": false,
"ControllerCoreRGRB13": false,
"ControllerCoreRGRB14": false,
"ControllerCoreRGRB15": false,
"ControllerCoreRGRB2": true,
"ControllerCoreRGRB3": true,
"ControllerCoreRGRB4": true,
"ControllerCoreRGRB5": true,
"ControllerCoreRGRB6": true,
"ControllerCoreRGRB7": true,
"ControllerCoreRGRB8": false,
"ControllerCoreRGRB9": false,
"ControllerCoreRGRtFAWBInClkCycles": 27,
"ControllerCoreRGRtRASBInClkCycles": 20,
"ControllerCoreRGRtRCBInClkCycles": 27,
"ControllerCoreRGRtRPBInClkCycles": 8,
"ControllerCoreRGRtRRDB_LInClkCycles": 6,
"ControllerCoreRGRtRRDB_SInClkCycles": 6,
"ControllerCoreRefDisable": 0,
"ControllerCoreRefNumARCmdsIntREFI": 8192,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": true,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "orgr",
"SimulationProgressBar": true,
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

40
DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.json
View File

@@ -1,40 +0,0 @@
{
"simconfig": {
"ControllerCoreRGR": true,
"ControllerCoreRGRB0": true,
"ControllerCoreRGRB1": true,
"ControllerCoreRGRB10": false,
"ControllerCoreRGRB11": false,
"ControllerCoreRGRB12": false,
"ControllerCoreRGRB13": false,
"ControllerCoreRGRB14": false,
"ControllerCoreRGRB15": false,
"ControllerCoreRGRB2": true,
"ControllerCoreRGRB3": true,
"ControllerCoreRGRB4": false,
"ControllerCoreRGRB5": false,
"ControllerCoreRGRB6": false,
"ControllerCoreRGRB7": false,
"ControllerCoreRGRB8": false,
"ControllerCoreRGRB9": false,
"ControllerCoreRGRtFAWBInClkCycles": 0,
"ControllerCoreRGRtRASBInClkCycles": 11,
"ControllerCoreRGRtRCBInClkCycles": 16,
"ControllerCoreRGRtRPBInClkCycles": 5,
"ControllerCoreRGRtRRDB_LInClkCycles": 2,
"ControllerCoreRGRtRRDB_SInClkCycles": 2,
"ControllerCoreRefDisable": 0,
"ControllerCoreRefNumARCmdsIntREFI": 8192,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": true,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "orgr_4b_opt_timings",
"SimulationProgressBar": true,
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

40
DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.json
View File

@@ -1,40 +0,0 @@
{
"simconfig": {
"ControllerCoreRGR": true,
"ControllerCoreRGRB0": true,
"ControllerCoreRGRB1": true,
"ControllerCoreRGRB10": false,
"ControllerCoreRGRB11": false,
"ControllerCoreRGRB12": false,
"ControllerCoreRGRB13": false,
"ControllerCoreRGRB14": false,
"ControllerCoreRGRB15": false,
"ControllerCoreRGRB2": true,
"ControllerCoreRGRB3": true,
"ControllerCoreRGRB4": false,
"ControllerCoreRGRB5": false,
"ControllerCoreRGRB6": false,
"ControllerCoreRGRB7": false,
"ControllerCoreRGRB8": false,
"ControllerCoreRGRB9": false,
"ControllerCoreRGRtFAWBInClkCycles": 27,
"ControllerCoreRGRtRASBInClkCycles": 20,
"ControllerCoreRGRtRCBInClkCycles": 27,
"ControllerCoreRGRtRPBInClkCycles": 8,
"ControllerCoreRGRtRRDB_LInClkCycles": 6,
"ControllerCoreRGRtRRDB_SInClkCycles": 6,
"ControllerCoreRefDisable": 0,
"ControllerCoreRefNumARCmdsIntREFI": 8192,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": true,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "orgr_4b_std_timings",
"SimulationProgressBar": true,
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

40
DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.json
View File

@@ -1,40 +0,0 @@
{
"simconfig": {
"ControllerCoreRGR": true,
"ControllerCoreRGRB0": true,
"ControllerCoreRGRB1": true,
"ControllerCoreRGRB10": false,
"ControllerCoreRGRB11": false,
"ControllerCoreRGRB12": false,
"ControllerCoreRGRB13": false,
"ControllerCoreRGRB14": false,
"ControllerCoreRGRB15": false,
"ControllerCoreRGRB2": true,
"ControllerCoreRGRB3": true,
"ControllerCoreRGRB4": true,
"ControllerCoreRGRB5": true,
"ControllerCoreRGRB6": true,
"ControllerCoreRGRB7": true,
"ControllerCoreRGRB8": false,
"ControllerCoreRGRB9": false,
"ControllerCoreRGRtFAWBInClkCycles": 0,
"ControllerCoreRGRtRASBInClkCycles": 11,
"ControllerCoreRGRtRCBInClkCycles": 16,
"ControllerCoreRGRtRPBInClkCycles": 5,
"ControllerCoreRGRtRRDB_LInClkCycles": 2,
"ControllerCoreRGRtRRDB_SInClkCycles": 2,
"ControllerCoreRefDisable": 0,
"ControllerCoreRefNumARCmdsIntREFI": 8192,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": true,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "orgr_8b_opt_timings",
"SimulationProgressBar": true,
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

40
DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.json
View File

@@ -1,40 +0,0 @@
{
"simconfig": {
"ControllerCoreRGR": true,
"ControllerCoreRGRB0": true,
"ControllerCoreRGRB1": true,
"ControllerCoreRGRB10": false,
"ControllerCoreRGRB11": false,
"ControllerCoreRGRB12": false,
"ControllerCoreRGRB13": false,
"ControllerCoreRGRB14": false,
"ControllerCoreRGRB15": false,
"ControllerCoreRGRB2": true,
"ControllerCoreRGRB3": true,
"ControllerCoreRGRB4": true,
"ControllerCoreRGRB5": true,
"ControllerCoreRGRB6": true,
"ControllerCoreRGRB7": true,
"ControllerCoreRGRB8": false,
"ControllerCoreRGRB9": false,
"ControllerCoreRGRtFAWBInClkCycles": 27,
"ControllerCoreRGRtRASBInClkCycles": 20,
"ControllerCoreRGRtRCBInClkCycles": 27,
"ControllerCoreRGRtRPBInClkCycles": 8,
"ControllerCoreRGRtRRDB_LInClkCycles": 6,
"ControllerCoreRGRtRRDB_SInClkCycles": 6,
"ControllerCoreRefDisable": 0,
"ControllerCoreRefNumARCmdsIntREFI": 8192,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": true,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "orgr_8b_std_timings_ddr3",
"SimulationProgressBar": true,
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

21
DRAMSys/library/resources/configs/simulator/orgr_ddr4.json
View File

@@ -1,21 +0,0 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": true,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "orgr_ddr4",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

21
DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.json
View File

@@ -1,21 +0,0 @@
{
"simconfig": {
"AddressOffset": 2147483648,
"CheckTLM2Protocol": false,
"DatabaseRecording": false,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": true,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "rgr",
"SimulationProgressBar": true,
"StoreMode": "Store",
"ThermalSimulation": false,
"UseMalloc": true,
"WindowSize": 1000
}
}

21
DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.json
View File

@@ -1,21 +0,0 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": true,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "rgr",
"SimulationProgressBar": true,
"StoreMode": "Store",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

21
DRAMSys/library/resources/configs/simulator/rgrsimcfg.json
View File

@@ -1,21 +0,0 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": true,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"NumberOfDevicesOnDIMM": 4,
"NumberOfMemChannels": 1,
"PowerAnalysis": true,
"SimulationName": "rgr",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

16
DRAMSys/library/resources/configs/simulator/sms.json
View File

@@ -1,16 +0,0 @@
{
"simconfig": {
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": true,
"NumberOfDevicesOnDIMM": 1,
"NumberOfMemChannels": 4,
"PowerAnalysis": true,
"SimulationName": "sms",
"SimulationProgressBar": true,
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

259
DRAMSys/library/resources/resources.pri
View File

@@ -1,259 +0,0 @@
# Relative paths to "DRAMSys/library" because this file is included in
# "DRAMSys/library/library.pro"
# Simulation Files
DISTFILES += resources/simulations/ddr3-example.xml
DISTFILES += resources/simulations/ddr3-single-device.xml
DISTFILES += resources/simulations/ddr3-rgr.xml
DISTFILES += resources/simulations/ddr3-rgr00.xml
DISTFILES += resources/simulations/ddr3-rgr01.xml
DISTFILES += resources/simulations/ddr3-rgr02.xml
DISTFILES += resources/simulations/ddr3-rgr03.xml
DISTFILES += resources/simulations/ddr3-rgr04.xml
DISTFILES += resources/simulations/ddr3-rgr05.xml
DISTFILES += resources/simulations/ddr3-rgr06.xml
DISTFILES += resources/simulations/ddr3-rgr07.xml
DISTFILES += resources/simulations/ddr3-rgr08.xml
DISTFILES += resources/simulations/ddr3-rgr09.xml
DISTFILES += resources/simulations/ddr3-rgr10.xml
DISTFILES += resources/simulations/ddr3-rgr11.xml
DISTFILES += resources/simulations/ddr3-rgr12.xml
DISTFILES += resources/simulations/ddr3-rgr13.xml
DISTFILES += resources/simulations/ddr3-rgr14.xml
DISTFILES += resources/simulations/ddr3-rgr15.xml
DISTFILES += resources/simulations/ddr3-rgr16.xml
DISTFILES += resources/simulations/ddr3-rgr17.xml
DISTFILES += resources/simulations/ddr3-rgr18.xml
DISTFILES += resources/simulations/ddr3-rgr19.xml
DISTFILES += resources/simulations/ddr3-rgr20.xml
DISTFILES += resources/simulations/ddr3-rgr21.xml
DISTFILES += resources/simulations/ddr3-rgr22.xml
DISTFILES += resources/simulations/ddr3-rgr23.xml
DISTFILES += resources/simulations/ddr3-rgr24.xml
DISTFILES += resources/simulations/ddr3-rgr25.xml
DISTFILES += resources/simulations/ddr3-rgr26.xml
DISTFILES += resources/simulations/ddr3-rgr27.xml
DISTFILES += resources/simulations/ddr3-rgr28.xml
DISTFILES += resources/simulations/ddr3-rgr29.xml
DISTFILES += resources/simulations/ddr3-rgr30.xml
DISTFILES += resources/simulations/ddr3-rgr31.xml
DISTFILES += resources/simulations/ddr3-rgr32.xml
DISTFILES += resources/simulations/ddr3-rgr33.xml
DISTFILES += resources/simulations/ddr3-rgr34.xml
DISTFILES += resources/simulations/ddr3-rgr35.xml
DISTFILES += resources/simulations/ddr3-rgr36.xml
DISTFILES += resources/simulations/ddr3-rgr37.xml
DISTFILES += resources/simulations/ddr3-rgr38.xml
DISTFILES += resources/simulations/ddr3-rgr39.xml
DISTFILES += resources/simulations/ddr3-rgr40.xml
DISTFILES += resources/simulations/ddr3-rgr41.xml
DISTFILES += resources/simulations/ddr3-rgr42.xml
DISTFILES += resources/simulations/ddr3-rgr43.xml
DISTFILES += resources/simulations/ddr3-rgr44.xml
DISTFILES += resources/simulations/wideio-example.xml
DISTFILES += resources/simulations/wideio-ecc.xml
DISTFILES += resources/simulations/ddr3-ecc.xml
DISTFILES += resources/simulations/sms-example.xml
DISTFILES += resources/simulations/ddr3_postpone_ref_test.xml
DISTFILES += resources/simulations/rgrsim.xml
DISTFILES += resources/simulations/lpddr4-single-device.xml
# Simulator Files
DISTFILES += resources/configs/simulator/wideio.xml
DISTFILES += resources/configs/simulator/ddr3.xml
DISTFILES += resources/configs/simulator/ddr3-single-device.xml
DISTFILES += resources/configs/simulator/wideio_thermal.xml
DISTFILES += resources/configs/simulator/wideio_ecc.xml
DISTFILES += resources/configs/simulator/ddr3_ecc.xml
DISTFILES += resources/configs/simulator/sms.xml
DISTFILES += resources/configs/simulator/rgrsimcfg.xml
DISTFILES += resources/configs/simulator/lpddr4.xml
# Scripts
DISTFILES += resources/scripts/address_scrambler.pl
DISTFILES += resources/scripts/createTraceDB.sql
DISTFILES += resources/scripts/stride_detection.pl
DISTFILES += resources/scripts/analyse_trace.pl
DISTFILES += resources/scripts/video_rendering/temperatur.job.pl
DISTFILES += resources/scripts/video_rendering/temperatur.pl
DISTFILES += resources/scripts/video_rendering/Makefile
DISTFILES += resources/scripts/DRAMSylva/collect.sh
DISTFILES += resources/scripts/DRAMSylva/common.in
DISTFILES += resources/scripts/DRAMSylva/DRAMSylva.jobscript
DISTFILES += resources/scripts/DRAMSylva/DRAMSylva.sh
DISTFILES += resources/scripts/DRAMSylva/DRAMSylvaCSVPlot.py
DISTFILES += resources/scripts/DRAMSylva/DRAMSyrup.py
DISTFILES += resources/scripts/DRAMSylva/gem5ilva.jobscript
DISTFILES += resources/scripts/DRAMSylva/gem5ilva.sh
DISTFILES += resources/scripts/DRAMSylva/gem5ilva_fs.jobscript
DISTFILES += resources/scripts/DRAMSylva/gem5ilva_fs.sh
DISTFILES += resources/scripts/DRAMSylva/LICENSE
DISTFILES += resources/scripts/DRAMSylva/README
DISTFILES += resources/scripts/DRAMSylva/configs_json/configs.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc1x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc1x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc2x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc2x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc4x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsbrc4x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x_gem5_fs.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc1x_gem5_fs_nodb.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc2x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc2x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc4x.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/configsrbc4x_gem5.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/ref.json
DISTFILES += resources/scripts/DRAMSylva/configs_json/ref_bw.json
DISTFILES += resources/scripts/trace_gen.py
DISTFILES += resources/scripts/traceGenerationForNNTraining.pl
# Trace Files
DISTFILES += resources/traces/chstone-aes_32.stl
DISTFILES += resources/traces/test2.stl
DISTFILES += resources/traces/voco2.stl
DISTFILES += resources/traces/chstone-bf_32.stl
DISTFILES += resources/traces/trace2.stl
DISTFILES += resources/traces/chstone-sha_32.stl
DISTFILES += resources/traces/prettyTest
DISTFILES += resources/traces/test.stl
DISTFILES += resources/traces/mediabench-mpeg2encode_32.stl
DISTFILES += resources/traces/mediabench-unepic_32.stl
DISTFILES += resources/traces/chstone-mips_32.stl
DISTFILES += resources/traces/mediabench-gsmdecode_32.stl
DISTFILES += resources/traces/mediabench-c-ray-1.1_32.stl
DISTFILES += resources/traces/eiersalat.stl
DISTFILES += resources/traces/mediabench-fractal_32.stl
DISTFILES += resources/traces/wideio_multi_channel.stl
DISTFILES += resources/traces/mediabench-g721decode_32.stl
DISTFILES += resources/traces/mediabench-jpegencode_32.stl
DISTFILES += resources/traces/chstone-jpeg_32.stl
DISTFILES += resources/traces/trace.stl
DISTFILES += resources/traces/mediabench-h263decode_32.stl
DISTFILES += resources/traces/mediabench-h263encode_32.stl
DISTFILES += resources/traces/mediabench-mpeg2decode_32.stl
DISTFILES += resources/traces/chstone-gsm_32.stl
DISTFILES += resources/traces/mediabench-epic_32.stl
DISTFILES += resources/traces/empty.stl
DISTFILES += resources/traces/mediabench-adpcmencode_32.stl
DISTFILES += resources/traces/chstone-adpcm_32.stl
DISTFILES += resources/traces/mediabench-jpegdecode_32.stl
DISTFILES += resources/traces/mediabench-g721encode_32.stl
DISTFILES += resources/traces/small.stl
DISTFILES += resources/traces/chstone-motion_32.stl
DISTFILES += resources/traces/mediabench-adpcmdecode_32.stl
DISTFILES += resources/traces/ddr3_example.stl
DISTFILES += resources/traces/ddr3_exampleb.stl
DISTFILES += resources/traces/ddr3_rgr.stl
DISTFILES += resources/traces/ddr3_single_dev_example.stl
DISTFILES += resources/traces/ddr3_SAMSUNG_M471B5674QH0_DIMM_example.stl
DISTFILES += resources/traces/test_ecc.stl
DISTFILES += resources/traces/sms_t1.stl
DISTFILES += resources/traces/sms_t2.stl
DISTFILES += resources/traces/sms_t3.stl
DISTFILES += resources/traces/sms_t4.stl
DISTFILES += resources/traces/ddr3_postpone_ref_test_1.stl
DISTFILES += resources/traces/ddr3_postpone_ref_test_2.stl
DISTFILES += resources/traces/ddr3_postpone_ref_test_3.stl
DISTFILES += resources/traces/ip*.stl
DISTFILES += resources/traces/rgr*.stl
DISTFILES += resources/traces/read_write_switch.stl
# Memory Controller Configs
DISTFILES += resources/configs/mcconfigs/fifoStrict.xml
DISTFILES += resources/configs/mcconfigs/fifo.xml
DISTFILES += resources/configs/mcconfigs/fr_fcfs.xml
DISTFILES += resources/configs/mcconfigs/par_bs.xml
DISTFILES += resources/configs/mcconfigs/fifo_ecc.xml
DISTFILES += resources/configs/mcconfigs/sms.xml
DISTFILES += resources/configs/mcconfigs/rgrmccfg.xml
DISTFILES += resources/configs/mcconfigs/grp.xml
DISTFILES += resources/configs/mcconfigs/fr_fcfs_rp.xml
DISTFILES += resources/configs/mcconfigs/fr_fcfs_grp.xml
# Memspecs
DISTFILES += resources/configs/memspecs/memspec.dtd
DISTFILES += resources/configs/memspecs/MatzesWideIO.xml
DISTFILES += resources/configs/memspecs/DDR4.xml
DISTFILES += resources/configs/memspecs/MatzesWideIO-short.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml
DISTFILES += resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-200_128bit.xml
DISTFILES += resources/configs/memspecs/JEDEC_256Mb_WIDEIO_SDR-266_128bit.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR2-1066_16bit_H.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR2-800_16bit_H.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_2s.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_3s.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_16bit_G_mu.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_2s.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_3s.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1066_8bit_G_mu.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_2s.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_3s.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_mu.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_2s.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_3s.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1066_8bit_D_mu.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_2s.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_3s.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_DDR3-1600_16bit_D_mu.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_LPDDR-266_16bit_A.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_LPDDR-333_16bit_A.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_LPDDR2-1066-S4_16bit_A.xml
DISTFILES += resources/configs/memspecs/MICRON_2Gb_LPDDR2-800-S4_16bit_A.xml
DISTFILES += resources/configs/memspecs/MICRON_4Gb_DDR4-1866_8bit_A.xml
DISTFILES += resources/configs/memspecs/MICRON_4Gb_DDR4-2400_8bit_A.xml
DISTFILES += resources/configs/memspecs/MICRON_4Gb_LPDDR3-1333_32bit_A.xml
DISTFILES += resources/configs/memspecs/MICRON_4Gb_LPDDR3-1600_32bit_A.xml
DISTFILES += resources/configs/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml
DISTFILES += resources/configs/memspecs/SAMSUNG_K4B4G1646Q_4Gb_DDR3-1066_16bit.xml
DISTFILES += resources/configs/memspecs/orgr_16Gb_ddr4.xml
DISTFILES += resources/configs/memspecs/wideio.xml
DISTFILES += resources/configs/memspecs/wideio_less_refresh.xml
DISTFILES += resources/configs/memspecs/MICRON_1Gb_DDR3-1600_8bit_G_less_refresh.xml
DISTFILES += resources/configs/memspecs/rgrspec.xml
DISTFILES += resources/configs/memspecs/MICRON_6Gb_LPDDR4-3200_NDA_NDA_NDA.xml
# Address Mapping Configs
DISTFILES += resources/configs/amconfigs/am_ddr3.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_x16_brc.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_x16_rbc.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_brc.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_8x2Gbx8_dimm_p1KB_rbc.xml
DISTFILES += resources/configs/amconfigs/resources/configs/amconfigs/am_ddr4.xml
DISTFILES += resources/configs/amconfigs/am_highHits.xml
DISTFILES += resources/configs/amconfigs/am_highPara.xml
DISTFILES += resources/configs/amconfigs/am_wideio.xml
DISTFILES += resources/configs/amconfigs/am_lowHits.xml
DISTFILES += resources/configs/amconfigs/am_lowPara.xml
DISTFILES += resources/configs/amconfigs/am_wideioFourBanks.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_1Gbx8_p1KB_brc.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_brc.xml
DISTFILES += resources/configs/amconfigs/am_ddr3_4x4Gbx16_dimm_p2KB_rbc.xml
DISTFILES += resources/configs/amconfigs/rgram.xml
DISTFILES += resources/configs/amconfigs/am_test_congen_output.json
DISTFILES += resources/configs/amconfigs/am_lpddr4.xml
# Thermal Simulation configs
DISTFILES += resources/configs/thermalsim/core.flp
DISTFILES += resources/configs/thermalsim/mem.flp
DISTFILES += resources/configs/thermalsim/powerInfo.xml
DISTFILES += resources/configs/thermalsim/stack.stk
DISTFILES += resources/configs/thermalsim/config.xml
# Add DRAMPower
DISTFILES += src/common/third_party/DRAMPower/*
DISTFILES += src/common/third_party/DRAMPower/src/*
# Error Simulation data
DISTFILES += resources/error/wideio.csv

10
DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json
View File

@@ -1,10 +0,0 @@
{
"simulation": {
"addressmapping": "rgram.json",
"mcconfig": "rgrmccfg.json",
"memspec": "rgrspec.json",
"simconfig": "rgrsimcfg-gem5-fs.json",
"simulationid": "rgrsim-gem5-fs",
"thermalconfig": "config.json"
}
}

10
DRAMSys/library/resources/simulations/rgrsim-gem5-se.json
View File

@@ -1,10 +0,0 @@
{
"simulation": {
"addressmapping": "rgram.json",
"mcconfig": "rgrmccfg.json",
"memspec": "rgrspec.json",
"simconfig": "rgrsimcfg-gem5-se.json",
"simulationid": "rgrsim-gem5-se",
"thermalconfig": "config.json"
}
}

16
DRAMSys/library/resources/simulations/rgrsim.json
View File

@@ -1,16 +0,0 @@
{
"simulation": {
"addressmapping": "rgram.json",
"mcconfig": "rgrmccfg.json",
"memspec": "rgrspec.json",
"simconfig": "rgrsimcfg.json",
"simulationid": "rgrsimid",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 1000,
"name": "1_720x1280_64-Pixelgroesse_imb3_str1_scram_ddr4_8b_same_clock.stl"
}
]
}
}

16
DRAMSys/library/resources/simulations/wideio-ecc.json
View File

@@ -1,16 +0,0 @@
{
"simulation": {
"addressmapping": "am_wideio.json",
"mcconfig": "fifo.json",
"memspec": "wideio_less_refresh.json",
"simconfig": "wideio_ecc.json",
"simulationid": "wideio-ecc",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 1000,
"name": "test_ecc.stl"
}
]
}
}

4
DRAMSys/library/resources/simulations/wideio-example.json
View File

@@ -1,8 +1,8 @@
{
"simulation": {
"addressmapping": "am_wideio.json",
"addressmapping": "am_wideio_4x1Gb_rbc.json",
"mcconfig": "fifoStrict.json",
"memspec": "wideio.json",
"memspec": "JEDEC_256Mb_WIDEIO-200_128bit.json",
"simconfig": "wideio.json",
"simulationid": "wideio-example",
"thermalconfig": "config.json",

3248
DRAMSys/library/resources/traces/prettyTest
View File

File diff suppressed because it is too large Load Diff

8
DRAMSys/traceAnalyzer/CMakeLists.txt
View File

@@ -99,6 +99,7 @@ add_executable(TraceAnalyzer
businessObjects/tracetestresults.cpp
presentation/tracemetrictreewidget.cpp
businessObjects/phases/phase.cpp
selectmetrics.ui
preferences.ui
evaluationtool.ui
@@ -106,6 +107,13 @@ add_executable(TraceAnalyzer
tracefiletab.ui
queryeditor.ui
traceanalyzer.ui
scripts/memUtil.py
scripts/metrics.py
scripts/tests.py
scripts/plots.py
scripts/sonification.pl
scripts/dataExtractForNN.pl
)
# Build:

10
DRAMSys/traceAnalyzer/scripts/scripts.pri
View File

@@ -1,10 +0,0 @@
# Relative paths to "DRAMSys/traceAnalyzer" because this file is included in
# "DRAMSys/traceAnalyzer/traceAnalyzer.pro"
DISTFILES += scripts/memUtil.py
DISTFILES += scripts/metrics.py
DISTFILES += scripts/tests.py
DISTFILES += scripts/plots.py
DISTFILES += scripts/sonification.pl
DISTFILES += scripts/dataExtractForNN.pl

23
DRAMSys/unitTests/googleTest.pri
View File

@@ -1,23 +0,0 @@
GOOGLETEST_DIR = googletest
!isEmpty(GOOGLETEST_DIR): {
GTEST_SRCDIR = $$GOOGLETEST_DIR/googletest
GMOCK_SRCDIR = $$GOOGLETEST_DIR/googlemock
}
requires(exists($$GTEST_SRCDIR):exists($$GMOCK_SRCDIR))
!exists($$GOOGLETEST_DIR):message("No googletest src dir found - set GOOGLETEST_DIR to enable.")
DEFINES += \
GTEST_LANG_CXX11
INCLUDEPATH *= \
$$GTEST_SRCDIR \
$$GTEST_SRCDIR/include \
$$GMOCK_SRCDIR \
$$GMOCK_SRCDIR/include
SOURCES += \
$$GTEST_SRCDIR/src/gtest-all.cc \
$$GMOCK_SRCDIR/src/gmock-all.cc

81
DRAMSys/unitTests/unitTests.pro
View File

@@ -1,81 +0,0 @@
TARGET = unitTestsDRAMSys
TEMPLATE = app
CONFIG += console
CONFIG -= app_bundle
CONFIG -= qt
systemc_home = $$(SYSTEMC_HOME)
isEmpty(systemc_home) {
systemc_home = /opt/systemc
}
message(SystemC home is $${systemc_home})
systemc_target_arch = $$(SYSTEMC_TARGET_ARCH)
isEmpty(systemc_target_arch) {
systemc_target_arch = linux64
}
message(SystemC target architecture is $${systemc_target_arch})
dramsys_disable_coverage_check = $$(DRAMSYS_DISABLE_COVERAGE_CHECK)
isEmpty(dramsys_disable_coverage_check) {
coverage_check = true
message(Coverage check ENABLED)
} else {
coverage_check = false
message(Coverage check DISABLED)
}
unix:!macx {
message(Building on a GNU/Linux)
QMAKE_RPATHDIR += $${systemc_home}/lib-$${systemc_target_arch}
message(Linker options QMAKE_RPATHDIR is $${QMAKE_RPATHDIR})
}
DEFINES += TIXML_USE_STL
DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES
unix:!macx {
QMAKE_CXXFLAGS += -std=c++11 -O0 -g
$$eval(coverage_check) {
QMAKE_CXXFLAGS += -fprofile-arcs -ftest-coverage -fPIC -O0
QMAKE_LFLAGS += -lgcov --coverage
}
}
macx: {
CONFIG += c++11
QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ -O0 -g
$$eval(coverage_check) {
QMAKE_CXXFLAGS += --coverage
QMAKE_LFLAGS += --coverage
}
}
QMAKE_CXXFLAGS += -pthread
INCLUDEPATH += ../library/src/simulation/
INCLUDEPATH += $${systemc_home}/include
LIBS += -L$${systemc_home}/lib-$${systemc_target_arch} -lsystemc -lpthread
SOURCEHOME = ../library/src/
SOURCES += \
main.cpp \
CommandMuxTests.cpp \
$${SOURCEHOME}/controller/CommandMux.cpp \
$${SOURCEHOME}/controller/Command.cpp
HEADERS += \
Testfile.h \
$${SOURCEHOME}/controller/CommandMux.h \
$${SOURCEHOME}/controller/Command.h
DISTFILES += ../DRAMSys.astylerc
include(googleTest.pri)
DISTFILES += googleTest.pri