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tracerecorder, refresh and stuff

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This commit is contained in:
robert
2014-03-29 00:26:21 +01:00
parent 35ba108cf7
commit 04e38d6663
40 changed files with 417 additions and 362 deletions
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96
dram/src/simulation/controllerwrapper.h
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@@ -15,9 +15,11 @@
#include <tlm_utils/peq_with_cb_and_phase.h>
#include <iostream>
#include <map>
#include <string>
#include "../common/protocol.h"
#include "../common/tlmDBPhaseRecorder.h"
#include "../common/TlmRecorder.h"
#include "../common/DebugManager.h"
#include "../core/IWrapperConnector.h"
#include "../core/Controller.h"
#include "../scheduler/Scheduler.h"
@@ -36,12 +38,12 @@ public:
tlm_utils::simple_initiator_socket<ControllerWrapper, BUSWIDTH, tlm::tlm_base_protocol_types> iSocket;
tlm_utils::simple_target_socket<ControllerWrapper, BUSWIDTH, tlm::tlm_base_protocol_types> tSocket;
ControllerWrapper(sc_module_name name, tlmDBPhaseRecorder& tpr):
ControllerWrapper(sc_module_name name, TlmRecorder& recorder):
frontendPEQ(this, &ControllerWrapper::frontendPEQCallback), dramPEQ(
this, &ControllerWrapper::dramPEQCallback), controllerPEQ(this,
&ControllerWrapper::controllerPEQCallback), tpr(tpr)
&ControllerWrapper::controllerPEQCallback), recorder(recorder), debugManager(DebugManager::getInstance())
{
controller = new DramController(*this);
controller = new Controller(*this, recorder);
scheduler = new Fifo(controller->getBankStates());
inputBufferDelay = controller->config.Timings.clk;
iSocket.register_nb_transport_bw(this, &ControllerWrapper::nb_transport_bw);
@@ -60,43 +62,43 @@ public:
virtual void send(const ScheduledCommand& command) override
{
assert(command.getStart() >= sc_time_stamp());
sc_time delay = command.getStart() - sc_time_stamp();
tlm::tlm_phase phase;
switch (command.getCommand())
{
case Read:
phase = BEGIN_RD;
case Command::Read:
dramPEQ.notify(command.getTransaction(),BEGIN_RD, command.getStart() - sc_time_stamp());
dramPEQ.notify(command.getTransaction(),END_RD, command.getEnd() - sc_time_stamp());
break;
case Write:
phase = BEGIN_WR;
case Command::Write:
dramPEQ.notify(command.getTransaction(),BEGIN_WR, command.getStart() - sc_time_stamp());
dramPEQ.notify(command.getTransaction(),END_WR, command.getEnd() - sc_time_stamp());
break;
case Refresh:
phase = BEGIN_AUTO_REFRESH;
case Command::AutoRefresh:
dramPEQ.notify(command.getTransaction(),BEGIN_AUTO_REFRESH, command.getStart() - sc_time_stamp());
dramPEQ.notify(command.getTransaction(),END_AUTO_REFRESH, command.getEnd() - sc_time_stamp());
break;
case Activate:
phase = BEGIN_ACT;
case Command::Activate:
break;
case Precharge:
phase = BEGIN_PRE;
case Command::Precharge:
break;
case Command::PrechargeAll:
break;
default:
SC_REPORT_FATAL(0, "unsupported command in controller wrapper");
break;
}
dramPEQ.notify(command.getTransaction(), phase, delay);
}
virtual void send(Trigger trigger, sc_time time) override
virtual void send(Trigger trigger, sc_time time, tlm_generic_payload& payload) override
{
assert(time >= sc_time_stamp());
sc_time delay = time - sc_time_stamp();
controllerPEQ.notify(triggerDummy, REFRESH_TRIGGER, delay);
controllerPEQ.notify(payload, REFRESH_TRIGGER, delay);
}
private:
DramController* controller;
Controller* controller;
Scheduler* scheduler;
map<Bank, bool> bankIsFreeForRequest;
@@ -105,15 +107,12 @@ private:
tlm_utils::peq_with_cb_and_phase<ControllerWrapper> controllerPEQ;
sc_time inputBufferDelay;
tlm::tlm_generic_payload triggerDummy;
tlmDBPhaseRecorder& tpr;
TlmRecorder& recorder;
DebugManager& debugManager;
void payloadEntersSystem(tlm_generic_payload& payload)
{
//std::cout << "----------------------------------------------------------------------- " << std::endl;
//std::cout << "Transaction enters system at " << sc_time_stamp() << std::endl;
printDebugMessage("Transaction enters system");
Bank bank = DramExtension::getExtension(payload).getBank();
scheduler->schedule(&payload);
scheduleNextPayload(bank);
@@ -121,23 +120,18 @@ private:
void scheduleNextPayload(Bank bank)
{
//std::cout << "----------------------------------------------------------------------- " << std::endl;
//std::cout << "In trigger for bank " << bank.ID() << std::endl;
printDebugMessage("In trigger for bank " + to_string(bank.ID()));
if(controller->isBusy(sc_time_stamp(), bank))
return;
else if(scheduler->hasTransactionForBank(bank))
{
tlm_generic_payload* nextTransaction = scheduler->getTransactionForBank(bank);
if(controller->schedule(sc_time_stamp(), *nextTransaction))
{
//std::cout << "Next payload was scheduled by core " << std::endl;
printDebugMessage("Next payload was scheduled by core");
scheduler->popTransactionForBank(bank);
}
else
{
//std::cout << "Next payload was not scheduled because of refresh " << std::endl;
}
}
}
@@ -147,10 +141,8 @@ private:
}
// Initiated by dram
tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay)
{
dramPEQ.notify(payload, phase, bwDelay);
return TLM_ACCEPTED;
}
@@ -158,7 +150,7 @@ private:
tlm_sync_enum nb_transport_fw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& fwDelay)
{
DramExtension::getExtension(payload);
tpr.recordPhase(payload,phase,sc_time_stamp());
recorder.recordPhase(payload,phase,sc_time_stamp());
if (phase == BEGIN_REQ)
{
@@ -181,7 +173,7 @@ private:
{
payloadEntersSystem(payload);
payload.set_response_status(tlm::TLM_OK_RESPONSE);
tpr.recordPhase(payload, END_REQ, sc_time_stamp());
recorder.recordPhase(payload, END_REQ, sc_time_stamp());
sendToFrontend(payload, END_REQ, SC_ZERO_TIME);
}
else
@@ -193,24 +185,13 @@ private:
void dramPEQCallback(tlm_generic_payload& payload, const tlm_phase& phase)
{
tpr.recordPhase(payload,phase,sc_time_stamp());
DramExtension *result = NULL;
payload.get_extension(result);
if(result==NULL)
{
cout << "ERROR AT TIME " << sc_time_stamp() << std::endl;
cout << "Payload " << payload.get_address() << " " << phase;
assert(result != NULL);
}
if (phase == BEGIN_RD || phase == BEGIN_WR)
{
//std::cout << "BEGIN_RD at " <<sc_time_stamp() << " on Bank " << DramExtension::getExtension(payload).getBank().ID() << std::endl;
scheduleNextPayload(DramExtension::getExtension(payload).getBank());
sendToDram(payload, phase, SC_ZERO_TIME);
}
else if(phase == BEGIN_AUTO_REFRESH || phase == BEGIN_ACT
|| phase == BEGIN_PRE)
|| phase == BEGIN_PRE || phase == BEGIN_PRE_ALL)
{
sendToDram(payload, phase, SC_ZERO_TIME);
}
@@ -220,7 +201,7 @@ private:
}
else if (phase == END_RD || phase == END_WR)
{
tpr.recordPhase(payload, BEGIN_RESP, sc_time_stamp());
recorder.recordPhase(payload, BEGIN_RESP, sc_time_stamp());
sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
}
else if (phase == END_PRE || phase == END_ACT)
@@ -229,8 +210,10 @@ private:
}
else
{
SC_REPORT_FATAL(0,
"dramPEQCallback queue in controller wrapper was triggered with unknown phase");
ostringstream oss;
oss << phase;
string str = string("dramPEQCallback queue in controller wrapper was triggered with unknown phase ") + oss.str();
SC_REPORT_FATAL(0, str.c_str());
}
}
@@ -238,7 +221,7 @@ private:
{
if (phase == REFRESH_TRIGGER)
{
controller->scheduleRefresh(sc_time_stamp());
controller->scheduleRefresh(payload, sc_time_stamp());
}
else
{
@@ -262,6 +245,11 @@ private:
tSocket->nb_transport_bw(payload, TPhase, TDelay);
}
void printDebugMessage(string message, Importance importance = Importance::Info)
{
debugManager.printDebugMessage(message,Sender::DramWrapper,importance);
}
};
#endif /* CONTROLLERWRAPPER_H_ */