From 04e38d6663e191efe3a7d1a1e040076f4fc27eeb Mon Sep 17 00:00:00 2001 From: robert Date: Sat, 29 Mar 2014 00:26:21 +0100 Subject: [PATCH] tracerecorder, refresh and stuff --- dram/.cproject | 10 +- dram/.settings/language.settings.xml | 2 +- .../org.eclipse.core.resources.prefs | 2 + dram/src/common/DebugManager.cpp | 8 +- dram/src/common/DebugManager.h | 4 +- ...tlmDBPhaseRecorder.cpp => TlmRecorder.cpp} | 143 ++++++++++-------- .../{tlmDBPhaseRecorder.h => TlmRecorder.h} | 22 +-- dram/src/common/dramExtension.cpp | 14 -- dram/src/common/dramExtension.h | 14 +- dram/src/common/xmlAddressdecoder.cpp | 10 +- dram/src/common/xmlAddressdecoder.h | 2 +- dram/src/common/xmlConfig.h | 2 +- dram/src/core/Command.cpp | 42 +++++ dram/src/core/Command.h | 9 +- dram/src/core/Configuration.h | 2 +- dram/src/core/Controller.cpp | 66 ++++---- dram/src/core/Controller.h | 17 ++- dram/src/core/ControllerState.cpp | 20 +-- dram/src/core/IWrapperConnector.h | 2 +- dram/src/core/TimingConfiguration.h | 4 +- dram/src/core/refresh/IRefreshManager.h | 36 ----- dram/src/core/refresh/RefreshManager.cpp | 11 +- dram/src/core/refresh/RefreshManager.h | 16 +- .../core/refresh/RefreshManagerForBank.cpp | 85 ++++++++--- dram/src/core/refresh/RefreshManagerForBank.h | 25 +-- dram/src/core/scheduling/CommandSchedule.h | 10 +- .../scheduling/CommandSequenceGenerator.cpp | 10 +- .../scheduling/CommandSequenceScheduler.h | 6 +- dram/src/core/scheduling/ScheduledCommand.h | 24 +-- .../scheduling/checker/ActivateChecker.cpp | 8 +- .../scheduling/checker/PrechargeChecker.cpp | 4 +- .../core/scheduling/checker/ReadChecker.cpp | 2 +- .../core/scheduling/checker/WriteChecker.cpp | 2 +- dram/src/core/utils/Utils.cpp | 1 + dram/src/core/utils/Utils.h | 1 - dram/src/simulation/MemoryManager.cpp | 20 +-- dram/src/simulation/controllerwrapper.h | 96 +++++------- dram/src/simulation/dram.h | 2 +- dram/src/simulation/main.cpp | 18 ++- dram/src/simulation/traceplayer.h | 7 +- 40 files changed, 417 insertions(+), 362 deletions(-) create mode 100644 dram/.settings/org.eclipse.core.resources.prefs rename dram/src/common/{tlmDBPhaseRecorder.cpp => TlmRecorder.cpp} (67%) rename dram/src/common/{tlmDBPhaseRecorder.h => TlmRecorder.h} (79%) create mode 100644 dram/src/core/Command.cpp delete mode 100644 dram/src/core/refresh/IRefreshManager.h diff --git a/dram/.cproject b/dram/.cproject index c61531b3..d744cb34 100644 --- a/dram/.cproject +++ b/dram/.cproject @@ -90,24 +90,24 @@ - + - - - + + + - + diff --git a/dram/.settings/language.settings.xml b/dram/.settings/language.settings.xml index 127cd8ac..278289a3 100644 --- a/dram/.settings/language.settings.xml +++ b/dram/.settings/language.settings.xml @@ -4,7 +4,7 @@ - + diff --git a/dram/.settings/org.eclipse.core.resources.prefs b/dram/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..bd61a50f --- /dev/null +++ b/dram/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding//src/core/Command.cpp=UTF-8 diff --git a/dram/src/common/DebugManager.cpp b/dram/src/common/DebugManager.cpp index ad93b4f1..b0b1d8a8 100644 --- a/dram/src/common/DebugManager.cpp +++ b/dram/src/common/DebugManager.cpp @@ -17,7 +17,7 @@ DebugManager& DebugManager::getInstance() return manager; } -void DebugManager::printDebug(string message, Sender sender, Importance importance) +void DebugManager::printDebugMessage(string message, Sender sender, Importance importance) { bool show = count(whiteList.begin(), whiteList.end(), pair(sender, importance)); @@ -59,8 +59,10 @@ string DebugManager::senderToString(Sender sender) { switch (sender) { - case Sender::Core: - return "Core"; + case Sender::DramController: + return "DRAM core"; + case Sender::DramWrapper: + return "DRAM Wrapper"; case Sender::Scheduler: return "Scheduler"; case Sender::TracePlayer: diff --git a/dram/src/common/DebugManager.h b/dram/src/common/DebugManager.h index 2f2fad82..528a122e 100644 --- a/dram/src/common/DebugManager.h +++ b/dram/src/common/DebugManager.h @@ -11,7 +11,7 @@ #include enum class Importance {Warning, Info}; -enum class Sender {Core, Scheduler, TracePlayer, TraceRecorder}; +enum class Sender {DramController, DramWrapper, Scheduler, TracePlayer, TraceRecorder}; class DebugManager { @@ -21,7 +21,7 @@ public: bool printTime; bool printLocation; - void printDebug(std::string message, Sender sender, Importance importance=Importance::Info); + void printDebugMessage(std::string message, Sender sender, Importance importance=Importance::Info); void addToWhiteList(Sender sender, Importance importance); void addToWhiteList(Sender sender); diff --git a/dram/src/common/tlmDBPhaseRecorder.cpp b/dram/src/common/TlmRecorder.cpp similarity index 67% rename from dram/src/common/tlmDBPhaseRecorder.cpp rename to dram/src/common/TlmRecorder.cpp index d1ccfdc7..f0b5b403 100644 --- a/dram/src/common/tlmDBPhaseRecorder.cpp +++ b/dram/src/common/TlmRecorder.cpp @@ -1,4 +1,4 @@ -#include "tlmDBPhaseRecorder.h" +#include "TlmRecorder.h" #include "protocol.h" #include "dramExtension.h" #include "xmlAddressdecoder.h" @@ -6,8 +6,8 @@ using namespace std; -tlmDBPhaseRecorder::tlmDBPhaseRecorder(string dbName, string sqlScriptURI) : - dbName(dbName), transactionIDCounter(1), PicosecondsPerNanosecond(1e3) +TlmRecorder::TlmRecorder(string dbName, string sqlScriptURI) : + dbName(dbName), transactionIDCounter(1), recordingEndTime(SC_ZERO_TIME) { setUpTransactionTerminatingPhases(); openDB(dbName.c_str()); @@ -15,55 +15,73 @@ tlmDBPhaseRecorder::tlmDBPhaseRecorder(string dbName, string sqlScriptURI) : prepareSqlStatements(); sqlite3_exec(db, "BEGIN", 0, 0, 0); - debugMessage("Starting new database transaction"); + printDebugMessage("Starting new database transaction"); } -tlmDBPhaseRecorder::~tlmDBPhaseRecorder() +TlmRecorder::~TlmRecorder() { if (db) closeConnection(); } -void tlmDBPhaseRecorder::recordPhase(tlm::tlm_generic_payload& trans, tlm::tlm_phase phase, +void TlmRecorder::recordPhase(tlm::tlm_generic_payload& trans, tlm::tlm_phase phase, sc_time time) { - time /= PicosecondsPerNanosecond; - - if (currentTransactionsInSystem.count(&trans) == 0) + if(phase == tlm::BEGIN_REQ) + { introduceNewTransactionToSystem(time, trans); - - unsigned int id = currentTransactionsInSystem[&trans]; - - string phaseName = phaseToString(phase); - string phaseBeginPrefix = "BEGIN_"; - string phaseEndPrefix = "END_"; - - if (phaseName.find(phaseBeginPrefix) != string::npos) - insertPhaseInDB(phaseName, time, id); + recordPhase(trans, "REQ", time, time); + } + else if(phase == tlm::END_REQ) + { + updatePhaseEndInDB("REQ", time, trans); + } + else if(phase == tlm::BEGIN_RESP) + { + recordPhase(trans, "RESP", time, time); + } + else if(phase == tlm::END_RESP) + { + updatePhaseEndInDB("RESP", time, trans); + removeTransactionFromSystem(time, trans); + } else - updatePhaseEndInDB(phaseName, time, id); + { + SC_REPORT_FATAL("Trace Recorder", "Method recordPhase with unknown phase"); + } - bool phaseTerminatesTransaction = count(transactionTerminatingPhases.begin(), - transactionTerminatingPhases.end(), phase) == 1; - if (phaseTerminatesTransaction) - removeTransactionFromSystem(time, id, trans); - - recordingEndTime = time; } -void tlmDBPhaseRecorder::recordDebugMessage(std::string message, sc_time time) +void TlmRecorder::recordPhase(tlm::tlm_generic_payload& trans, std::string name, + sc_time begin, sc_time end) +{ + + unsigned int id = currentTransactionsInSystem.at(&trans); + insertPhaseInDB(name, begin, end, id); +} + + +void TlmRecorder::recordDebugMessage(std::string message, sc_time time) { - time /= PicosecondsPerNanosecond; insertDebugMessageInDB(message, time); } -void tlmDBPhaseRecorder::createTables(string pathToURI) +void TlmRecorder::createTables(string pathToURI) { string initial = getFileContents(pathToURI); executeSqlCommand(initial); } -void tlmDBPhaseRecorder::prepareSqlStatements() +void TlmRecorder::setUpTransactionTerminatingPhases() +{ + transactionTerminatingPhases.push_back(tlm::END_RESP); + transactionTerminatingPhases.push_back(static_cast(END_AUTO_REFRESH)); + transactionTerminatingPhases.push_back(static_cast(END_PDNP)); + transactionTerminatingPhases.push_back(static_cast(END_PDNA)); + transactionTerminatingPhases.push_back(static_cast(END_SREF)); +} + +void TlmRecorder::prepareSqlStatements() { insertTransactionString = "INSERT INTO Transactions VALUES (:id,:rangeID,:address,:thread,:channel,:bank,:row,:column,:command)"; @@ -76,7 +94,6 @@ void tlmDBPhaseRecorder::prepareSqlStatements() insertGeneralInfoString = "INSERT INTO GeneralInfo (NumberOfTransactions,TraceEnd,NumberOfBanks,description,clk,UnitOfTime) Values (:numberOfTransactions,:end,:numberOfBanks,:description,:clk,:unitOfTime)"; insertDebugMessageString = "INSERT INTO DebugMessages (Time,Message) Values (:time,:message)"; - sqlite3_prepare(db, insertTransactionString.c_str(), -1, &insertTransactionStatement, 0); sqlite3_prepare(db, insertRangeString.c_str(), -1, &insertRangeStatement, 0); sqlite3_prepare(db, updateRangeString.c_str(), -1, &updateRangeStatement, 0); @@ -86,16 +103,7 @@ void tlmDBPhaseRecorder::prepareSqlStatements() sqlite3_prepare(db, insertDebugMessageString.c_str(), -1, &insertDebugMessageStatement, 0); } -void tlmDBPhaseRecorder::setUpTransactionTerminatingPhases() -{ - transactionTerminatingPhases.push_back(tlm::END_RESP); - transactionTerminatingPhases.push_back(static_cast(END_AUTO_REFRESH)); - transactionTerminatingPhases.push_back(static_cast(END_PDNP)); - transactionTerminatingPhases.push_back(static_cast(END_PDNA)); - transactionTerminatingPhases.push_back(static_cast(END_SREF)); -} - -void tlmDBPhaseRecorder::openDB(std::string name) +void TlmRecorder::openDB(std::string name) { if (sqlite3_open(name.c_str(), &db)) { @@ -104,14 +112,14 @@ void tlmDBPhaseRecorder::openDB(std::string name) } } -void tlmDBPhaseRecorder::insertDebugMessageInDB(string message, const sc_time& time) +void TlmRecorder::insertDebugMessageInDB(string message, const sc_time& time) { sqlite3_bind_int64(insertDebugMessageStatement, 1, time.value()); sqlite3_bind_text(insertDebugMessageStatement, 2, message.c_str(), message.length(), 0); executeSqlStatement(insertDebugMessageStatement); } -void tlmDBPhaseRecorder::insertGeneralInfo() +void TlmRecorder::insertGeneralInfo() { sqlite3_bind_int64(insertGeneralInfoStatement, 1, transactionIDCounter - 1); sqlite3_bind_int64(insertGeneralInfoStatement, 2, recordingEndTime.value()); @@ -122,7 +130,7 @@ void tlmDBPhaseRecorder::insertGeneralInfo() sqlite3_bind_text(insertGeneralInfoStatement, 6, "NS", 2, NULL); executeSqlStatement(insertGeneralInfoStatement); } -void tlmDBPhaseRecorder::insertTransactionInDB(unsigned int id, tlm::tlm_generic_payload& trans) +void TlmRecorder::insertTransactionInDB(unsigned int id, tlm::tlm_generic_payload& trans) { sqlite3_bind_int(insertTransactionStatement, 1, id); sqlite3_bind_int(insertTransactionStatement, 2, id); @@ -139,35 +147,32 @@ void tlmDBPhaseRecorder::insertTransactionInDB(unsigned int id, tlm::tlm_generic executeSqlStatement(insertTransactionStatement); } -void tlmDBPhaseRecorder::insertRangeInDB(unsigned int id, const sc_time& time) +void TlmRecorder::insertRangeInDB(unsigned int id, const sc_time& time) { sqlite3_bind_int(insertRangeStatement, 1, id); sqlite3_bind_int64(insertRangeStatement, 2, time.value()); sqlite3_bind_int64(insertRangeStatement, 3, time.value()); executeSqlStatement(insertRangeStatement); } -void tlmDBPhaseRecorder::insertPhaseInDB(string phaseName, const sc_time& time, unsigned int id) +void TlmRecorder::insertPhaseInDB(string phaseName, const sc_time& begin, const sc_time& end, unsigned int id) { - string phaseBeginPrefix = "BEGIN_"; - phaseName.erase(0, phaseBeginPrefix.length()); sqlite3_bind_text(insertPhaseStatement, 1, phaseName.c_str(), phaseName.length(), 0); - sqlite3_bind_int64(insertPhaseStatement, 2, time.value()); - sqlite3_bind_int64(insertPhaseStatement, 3, time.value()); + sqlite3_bind_int64(insertPhaseStatement, 2, begin.value()); + sqlite3_bind_int64(insertPhaseStatement, 3, end.value()); sqlite3_bind_int(insertPhaseStatement, 4, id); executeSqlStatement(insertPhaseStatement); } -void tlmDBPhaseRecorder::updatePhaseEndInDB(string phaseName, const sc_time& time, unsigned int id) +void TlmRecorder::updatePhaseEndInDB(string phaseName, const sc_time& time, tlm::tlm_generic_payload& trans) { - string phaseEndPrefix = "END_"; - phaseName.erase(0, phaseEndPrefix.length()); + unsigned int id = currentTransactionsInSystem.at(&trans); sqlite3_bind_int64(updatePhaseStatement, 1, time.value()); sqlite3_bind_int(updatePhaseStatement, 2, id); sqlite3_bind_text(updatePhaseStatement, 3, phaseName.c_str(), phaseName.length(), 0); executeSqlStatement(updatePhaseStatement); } -void tlmDBPhaseRecorder::introduceNewTransactionToSystem(const sc_time& time, +void TlmRecorder::introduceNewTransactionToSystem(const sc_time& time, tlm::tlm_generic_payload& trans) { unsigned int id = transactionIDCounter++; @@ -177,22 +182,25 @@ void tlmDBPhaseRecorder::introduceNewTransactionToSystem(const sc_time& time, if (id % transactionCommitRate == 0) { sqlite3_exec(db, "COMMIT", 0, 0, 0); - debugMessage( + printDebugMessage( "Committing transactions " + to_string(id - transactionCommitRate + 1) + " - " + to_string(id)); sqlite3_exec(db, "BEGIN", 0, 0, 0); } } -void tlmDBPhaseRecorder::removeTransactionFromSystem(const sc_time& time, unsigned int id, - tlm::tlm_generic_payload& trans) + +void TlmRecorder::removeTransactionFromSystem(const sc_time& time, tlm::tlm_generic_payload& trans) { + unsigned int id = currentTransactionsInSystem.at(&trans); currentTransactionsInSystem.erase(&trans); sqlite3_bind_int64(updateRangeStatement, 1, time.value()); sqlite3_bind_int(updateRangeStatement, 2, id); executeSqlStatement(updateRangeStatement); + if(time > recordingEndTime) + recordingEndTime = time; } -void tlmDBPhaseRecorder::executeSqlStatement(sqlite3_stmt* statement) +void TlmRecorder::executeSqlStatement(sqlite3_stmt* statement) { if (sqlite3_step(statement) != SQLITE_DONE) { @@ -200,9 +208,9 @@ void tlmDBPhaseRecorder::executeSqlStatement(sqlite3_stmt* statement) } sqlite3_reset(statement); } -void tlmDBPhaseRecorder::executeSqlCommand(string command) +void TlmRecorder::executeSqlCommand(string command) { - debugMessage("Creating database by running provided sql script"); + printDebugMessage("Creating database by running provided sql script"); char * errMsg = 0; int rc = sqlite3_exec(db, command.c_str(), NULL, 0, &errMsg); @@ -212,9 +220,9 @@ void tlmDBPhaseRecorder::executeSqlCommand(string command) sqlite3_free(errMsg); } - debugMessage("Database created successfully"); + printDebugMessage("Database created successfully"); } -string tlmDBPhaseRecorder::getFileContents(string filename) +string TlmRecorder::getFileContents(string filename) { ifstream in(filename.c_str(), ios::in | ios::binary); if (in) @@ -229,7 +237,7 @@ string tlmDBPhaseRecorder::getFileContents(string filename) } throw(errno); } -string tlmDBPhaseRecorder::phaseToString(tlm::tlm_phase phase) +string TlmRecorder::phaseToString(tlm::tlm_phase phase) { ostringstream oss; oss << phase; @@ -237,19 +245,20 @@ string tlmDBPhaseRecorder::phaseToString(tlm::tlm_phase phase) return str; } -void tlmDBPhaseRecorder::debugMessage(std::string message, Importance importance) + +void TlmRecorder::printDebugMessage(std::string message, Importance importance) { - DebugManager::getInstance().printDebug(dbName + " - " + message, Sender::TraceRecorder, + DebugManager::getInstance().printDebugMessage(dbName + " - " + message, Sender::TraceRecorder, Importance::Info); } -void tlmDBPhaseRecorder::closeConnection() +void TlmRecorder::closeConnection() { insertGeneralInfo(); sqlite3_exec(db, "COMMIT", 0, 0, 0); - debugMessage( + printDebugMessage( "Number of transactions written to DB: " + std::to_string(transactionIDCounter - 1)); - debugMessage("tlmPhaseRecorder:\tEnd Recording"); + printDebugMessage("tlmPhaseRecorder:\tEnd Recording"); sqlite3_close(db); db = NULL; } diff --git a/dram/src/common/tlmDBPhaseRecorder.h b/dram/src/common/TlmRecorder.h similarity index 79% rename from dram/src/common/tlmDBPhaseRecorder.h rename to dram/src/common/TlmRecorder.h index 79140245..391589fc 100755 --- a/dram/src/common/tlmDBPhaseRecorder.h +++ b/dram/src/common/TlmRecorder.h @@ -14,18 +14,23 @@ #include "xmlAddressdecoder.h" #include "DebugManager.h" + using namespace std; -class tlmDBPhaseRecorder +class TlmRecorder { public: - tlmDBPhaseRecorder(std::string dbName, std::string sqlScriptURI); - ~tlmDBPhaseRecorder(); + TlmRecorder(std::string dbName, std::string sqlScriptURI); + ~TlmRecorder(); void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time time); + void recordPhase(tlm::tlm_generic_payload &trans, std::string name, sc_time begin, sc_time end); void recordDebugMessage(std::string message, sc_time time); + void introduceNewTransactionToSystem(const sc_time& time, tlm::tlm_generic_payload& trans); + void removeTransactionFromSystem(const sc_time& time, tlm::tlm_generic_payload& trans); + void closeConnection(); private: @@ -39,18 +44,16 @@ private: void openDB(std::string name); void setUpTransactionTerminatingPhases(); - void introduceNewTransactionToSystem(const sc_time& time, tlm::tlm_generic_payload& trans); - void removeTransactionFromSystem(const sc_time& time, unsigned int transactionID, tlm::tlm_generic_payload& trans); void createTables(std::string pathToURI); void insertGeneralInfo(); void insertTransactionInDB(unsigned int transactionID, tlm::tlm_generic_payload& trans); void insertRangeInDB(unsigned int transactionID, const sc_time& time); - void insertPhaseInDB(string phaseName, const sc_time& time, unsigned int transactionID); - void updatePhaseEndInDB(string phaseName, const sc_time& time, unsigned int transactionID); + void insertPhaseInDB(string phaseName, const sc_time& begin, const sc_time& end, unsigned int id); + void updatePhaseEndInDB(string phaseName, const sc_time& time, tlm::tlm_generic_payload& trans); void insertDebugMessageInDB(string message, const sc_time& time); - void debugMessage(std::string message, Importance importance = Importance::Info); + void printDebugMessage(std::string message, Importance importance = Importance::Info); static const int transactionCommitRate = 10000; map currentTransactionsInSystem; @@ -62,8 +65,5 @@ private: *insertPhaseStatement, *updatePhaseStatement, *insertGeneralInfoStatement, *insertDebugMessageStatement; std::string insertTransactionString, insertRangeString, updateRangeString, insertPhaseString, updatePhaseString, insertGeneralInfoString, insertDebugMessageString; - - double PicosecondsPerNanosecond; }; - #endif diff --git a/dram/src/common/dramExtension.cpp b/dram/src/common/dramExtension.cpp index ccc331a9..44312c46 100644 --- a/dram/src/common/dramExtension.cpp +++ b/dram/src/common/dramExtension.cpp @@ -3,20 +3,6 @@ using namespace tlm; -tlm_extension_base* DramExtension::clone() const -{ - return new DramExtension(thread, bank, row, column); -} - -void DramExtension::copy_from(const tlm_extension_base &ext) -{ - const DramExtension &cpyFrom = static_cast(ext); - thread = cpyFrom.thread; - bank = cpyFrom.bank; - row = cpyFrom.row; - column = cpyFrom.column; -} - /* Static methods * */ diff --git a/dram/src/common/dramExtension.h b/dram/src/common/dramExtension.h index 435212b1..7f004605 100644 --- a/dram/src/common/dramExtension.h +++ b/dram/src/common/dramExtension.h @@ -99,8 +99,18 @@ public: ~DramExtension(){} - virtual tlm::tlm_extension_base* clone() const; - virtual void copy_from(const tlm_extension_base &ext); + virtual tlm_extension_base* clone() const + { + return new DramExtension(thread, bank, row, column); + } + virtual void copy_from(const tlm_extension_base& ext) + { + const DramExtension& cpyFrom = static_cast(ext); + thread = cpyFrom.thread; + bank = cpyFrom.bank; + row = cpyFrom.row; + column = cpyFrom.column; + } const Thread& getThread() const{return thread;} const Channel& getChannel() const{return channel;} diff --git a/dram/src/common/xmlAddressdecoder.cpp b/dram/src/common/xmlAddressdecoder.cpp index be6fd638..8e438365 100644 --- a/dram/src/common/xmlAddressdecoder.cpp +++ b/dram/src/common/xmlAddressdecoder.cpp @@ -3,11 +3,11 @@ using namespace std; -string xmlAddressDecoder::URI = ""; +string xmlAddressDecoder::addressConfigURI = ""; -xmlAddressDecoder::xmlAddressDecoder(string URI) +xmlAddressDecoder::xmlAddressDecoder(string addressConfigURI) { - doc = new TiXmlDocument(URI.c_str()); + doc = new TiXmlDocument(addressConfigURI.c_str()); if (doc->LoadFile()) { dramconfig = doc->FirstChildElement("dramconfig"); @@ -68,13 +68,13 @@ xmlAddressDecoder::xmlAddressDecoder(string URI) } else { - SC_REPORT_ERROR("xmlAddressDecoder can not find ", URI.c_str()); + SC_REPORT_ERROR("xmlAddressDecoder can not find ", addressConfigURI.c_str()); } } xmlAddressDecoder& xmlAddressDecoder::getInstance() { - static xmlAddressDecoder decoder(xmlAddressDecoder::URI); + static xmlAddressDecoder decoder(xmlAddressDecoder::addressConfigURI); return decoder; } diff --git a/dram/src/common/xmlAddressdecoder.h b/dram/src/common/xmlAddressdecoder.h index cb4b0291..0ff5ffeb 100755 --- a/dram/src/common/xmlAddressdecoder.h +++ b/dram/src/common/xmlAddressdecoder.h @@ -36,7 +36,7 @@ class xmlAddressDecoder { public: - static std::string URI; + static std::string addressConfigURI; static xmlAddressDecoder& getInstance(); void getNode(unsigned int addr, node * n); diff --git a/dram/src/common/xmlConfig.h b/dram/src/common/xmlConfig.h index b1533af7..78b4645d 100755 --- a/dram/src/common/xmlConfig.h +++ b/dram/src/common/xmlConfig.h @@ -51,7 +51,7 @@ class xmlConfig xmlConfig() { //clk = sc_time(6.0, SC_NS); // 166MHz - clk = sc_time(6.0, SC_NS); // 166MHz + clk = sc_time(6, SC_NS); // 166MHz // Timings: // WC timings for 200MHz diff --git a/dram/src/core/Command.cpp b/dram/src/core/Command.cpp new file mode 100644 index 00000000..5815d1ac --- /dev/null +++ b/dram/src/core/Command.cpp @@ -0,0 +1,42 @@ +#include "Command.h" +#include + +namespace core { + +std::string commandToString(Command command) +{ + switch (command) { + case Command::Read: + return "RD"; + break; + case Command::ReadA: + return "RDA"; + break; + case Command::Write: + return "WR"; + break; + case Command::WriteA: + return "WRA"; + break; + case Command::Precharge: + return "PRE"; + break; + case Command::Activate: + return "ACT"; + break; + case Command::PrechargeAll: + return "PRE_ALL"; + break; + case Command::AutoRefresh: + return "AUTO_REFRESH"; + break; + + default: + SC_REPORT_FATAL("command","commandToString was called with unknown command"); + break; + } + + return ""; +} + +} diff --git a/dram/src/core/Command.h b/dram/src/core/Command.h index f9b2407d..2fd3f83d 100644 --- a/dram/src/core/Command.h +++ b/dram/src/core/Command.h @@ -4,13 +4,18 @@ * Created on: Mar 5, 2014 * Author: jonny */ - #ifndef COMMAND_H_ #define COMMAND_H_ +#include +#include + namespace core { -enum Command {NOP, Precharge, PrechargeAll, Activate, Read, Write, ReadA, WriteA, Refresh}; +enum class Command {NOP, Precharge, PrechargeAll, Activate, Read, Write, ReadA, WriteA, AutoRefresh}; +std::string commandToString(Command command); + + typedef std::vector CommandSequence; diff --git a/dram/src/core/Configuration.h b/dram/src/core/Configuration.h index 90a88619..a0d47ad8 100644 --- a/dram/src/core/Configuration.h +++ b/dram/src/core/Configuration.h @@ -15,7 +15,7 @@ namespace core{ struct Configuration { - Configuration(): numberOfBanks(8), burstlength(2), Timings(numberOfBanks), RefreshBankwise(false), + Configuration(): numberOfBanks(8), burstlength(2), Timings(numberOfBanks), RefreshBankwise(true), nActivate(2) {} unsigned int numberOfBanks; diff --git a/dram/src/core/Controller.cpp b/dram/src/core/Controller.cpp index b246119b..55879be0 100644 --- a/dram/src/core/Controller.cpp +++ b/dram/src/core/Controller.cpp @@ -14,43 +14,45 @@ namespace core { -DramController::DramController(IWrapperConnector& wrapperConnector): - config(),state(config.numberOfBanks, config.nActivate), savedState(config.numberOfBanks, config.nActivate), commandSequenceGenerator(state), commandChecker(), busChecker(config, state), commandSequenceScheduler( - *this), refreshManager(*this), wrapper(wrapperConnector) -{ - commandChecker[Activate] = new ActivateChecker(config, state); +Controller::Controller(IWrapperConnector& wrapperConnector, TlmRecorder& recorder) : + config(), state(config.numberOfBanks, config.nActivate), busChecker(config, state), wrapper( + wrapperConnector), commandChecker(), recorder(recorder), savedState( + config.numberOfBanks, config.nActivate), commandSequenceGenerator(state), commandSequenceScheduler( + *this), refreshManager(*this) - commandChecker[Precharge] = new PrechargeChecker(config, state); - commandChecker[Read] = new ReadChecker(config, state); - commandChecker[Write] = new WriteChecker(config, state); +{ + commandChecker[Command::Activate] = new ActivateChecker(config, state); + + commandChecker[Command::Precharge] = new PrechargeChecker(config, state); + commandChecker[Command::Read] = new ReadChecker(config, state); + commandChecker[Command::Write] = new WriteChecker(config, state); } - -DramController::~DramController() +Controller::~Controller() { - delete commandChecker[Activate]; - delete commandChecker[Precharge]; - delete commandChecker[Read]; - delete commandChecker[Write]; + delete commandChecker[Command::Activate]; + delete commandChecker[Command::Precharge]; + delete commandChecker[Command::Read]; + delete commandChecker[Command::Write]; } -void DramController::saveState() +void Controller::saveState() { savedState = state; } -void DramController::resetState() +void Controller::resetState() { state = savedState; } -void DramController::scheduleRefresh(sc_time time) +void Controller::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time time) { cleanUpBus(time); - refreshManager.scheduleRefresh(time); + refreshManager.scheduleRefresh(payload, time); } -bool DramController::schedule(sc_time start, tlm::tlm_generic_payload& payload) +bool Controller::schedule(sc_time start, tlm::tlm_generic_payload& payload) { cleanUpBus(start); @@ -59,8 +61,7 @@ bool DramController::schedule(sc_time start, tlm::tlm_generic_payload& payload) saveState(); - CommandSequence sequence = commandSequenceGenerator.generateCommandSequence( - payload); + CommandSequence sequence = commandSequenceGenerator.generateCommandSequence(payload); CommandSchedule schedule = commandSequenceScheduler.schedule(sequence, start, payload); if (refreshManager.hasCollision(schedule)) @@ -70,21 +71,23 @@ bool DramController::schedule(sc_time start, tlm::tlm_generic_payload& payload) } else { + schedule.record(recorder); send(schedule); return true; } } -bool DramController::isBusy(sc_time currentTime, Bank bank) +bool Controller::isBusy(sc_time currentTime, Bank bank) { ScheduledCommand lastScheduledCommand = state.getLastCommand(bank); - if(lastScheduledCommand.isNoCommand()) + if (lastScheduledCommand.isNoCommand()) return false; - else if(lastScheduledCommand.getCommand() == Write || lastScheduledCommand.getCommand() == Read) + else if (lastScheduledCommand.getCommand() == Command::Write + || lastScheduledCommand.getCommand() == Command::Read) { return (currentTime < lastScheduledCommand.getStart()); } - else if(lastScheduledCommand.getCommand() == Refresh) + else if (lastScheduledCommand.getCommand() == Command::AutoRefresh) { return (currentTime < lastScheduledCommand.getEnd()); } @@ -96,16 +99,16 @@ bool DramController::isBusy(sc_time currentTime, Bank bank) } -void DramController::send(const CommandSchedule& schedule) const +void Controller::send(const CommandSchedule& schedule) const { - for(const ScheduledCommand& cmd : schedule.getScheduledCommands()) - { - wrapper.send(cmd); - } + for (const ScheduledCommand& cmd : schedule.getScheduledCommands()) + { + wrapper.send(cmd); + } } -void DramController::cleanUpBus(sc_time currentTime) +void Controller::cleanUpBus(sc_time currentTime) { state.pendingBusCommands.erase(state.pendingBusCommands.begin(), state.pendingBusCommands.lower_bound(currentTime)); @@ -113,4 +116,3 @@ void DramController::cleanUpBus(sc_time currentTime) } /* namespace controller */ - diff --git a/dram/src/core/Controller.h b/dram/src/core/Controller.h index a28b43f7..a2ba6d2e 100644 --- a/dram/src/core/Controller.h +++ b/dram/src/core/Controller.h @@ -18,22 +18,22 @@ #include "scheduling/checker/ICommandChecker.h" #include "scheduling/checker/BusChecker.h" #include "scheduling/CommandSequenceScheduler.h" +#include "../common/TlmRecorder.h" namespace core { -class DramController +class Controller { public: - DramController(IWrapperConnector& wrapper); - virtual ~DramController() ; + Controller(IWrapperConnector& wrapper, TlmRecorder& recorder); + virtual ~Controller() ; bool schedule(sc_time currentTime, tlm::tlm_generic_payload& payload); bool isBusy(sc_time currentTime, Bank bank); - void scheduleRefresh(sc_time time); + void scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time time); const ICommandChecker& getChecker(Command command) const; - Configuration config; const BankStates& getBankStates(){return state.bankStates;} void saveState(); @@ -42,17 +42,18 @@ public: void cleanUpBus(sc_time time); void send(const CommandSchedule& schedule) const; + Configuration config; + ControllerState state; BusChecker busChecker; IWrapperConnector& wrapper; - ControllerState state; std::map commandChecker; + TlmRecorder& recorder; + private: ControllerState savedState; - CommandSequenceGenerator commandSequenceGenerator; CommandSequenceScheduler commandSequenceScheduler; RefreshManager refreshManager; - //PowerDownManager powerDownManager; void addCommandChecker(Command command, ICommandChecker* checker); diff --git a/dram/src/core/ControllerState.cpp b/dram/src/core/ControllerState.cpp index e019677d..6a3388b7 100644 --- a/dram/src/core/ControllerState.cpp +++ b/dram/src/core/ControllerState.cpp @@ -46,29 +46,21 @@ void ControllerState::change(const ScheduledCommand& scheduledCommand) lastCommandsOnBus[scheduledCommand.getCommand()][scheduledCommand.getBank()] = scheduledCommand; lastCommandsOnBus[scheduledCommand.getCommand()][scheduledCommand.getBank()].invalidateTransaction(); - //TODO do in refresh manager - /*if(scheduledCommand.getCommand() == Refresh) - { - for(unsigned int i = 0; i < bankStates.getNumberOfBanks(); ++i) - { - lastCommandsOnBus[scheduledCommand.getCommand()][Bank(i)] = scheduledCommand; - } - }*/ - - - switch (scheduledCommand.getCommand()) { - case Refresh: + case Command::AutoRefresh: bankStates.closeRowBuffer(scheduledCommand.getBank()); break; - case Activate: + case Command::Activate: bankStates.openRowInRowBuffer(scheduledCommand.getBank(), scheduledCommand.getRow()); nActivateWindow.put(scheduledCommand.getStart()); break; - case Precharge: + case Command::Precharge: bankStates.closeRowBuffer(scheduledCommand.getBank()); break; + case Command::PrechargeAll: + bankStates.closeAllRowBuffers(); + break; default: break; } diff --git a/dram/src/core/IWrapperConnector.h b/dram/src/core/IWrapperConnector.h index 790b411c..413d598e 100644 --- a/dram/src/core/IWrapperConnector.h +++ b/dram/src/core/IWrapperConnector.h @@ -20,7 +20,7 @@ class IWrapperConnector public: virtual ~IWrapperConnector() {} virtual void send(const core::ScheduledCommand& command) = 0; - virtual void send(core::Trigger trigger, sc_time time) = 0; + virtual void send(Trigger trigger, sc_time time, tlm::tlm_generic_payload& payload) = 0; }; } diff --git a/dram/src/core/TimingConfiguration.h b/dram/src/core/TimingConfiguration.h index 9bd1ffc6..71319a24 100644 --- a/dram/src/core/TimingConfiguration.h +++ b/dram/src/core/TimingConfiguration.h @@ -25,7 +25,7 @@ struct TimingConfiguration TimingConfiguration(unsigned int numberOfBanks) { - clk = sc_time(6.0, SC_NS); // 166MHz + clk = sc_time(6, SC_NS); // 166MHz for (unsigned int i = 0; i < numberOfBanks; ++i) { @@ -46,7 +46,7 @@ struct TimingConfiguration tRL = 3*clk; //read latency (read command start to data strobe) - tTAW = clkAlign(sc_time(50, SC_NS), clk, DOWN); //two activate window + tTAW = 48*clk; //two activate window } sc_time clk; diff --git a/dram/src/core/refresh/IRefreshManager.h b/dram/src/core/refresh/IRefreshManager.h deleted file mode 100644 index 1705105b..00000000 --- a/dram/src/core/refresh/IRefreshManager.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * IRefreshManager.h - * - * Created on: Mar 9, 2014 - * Author: jonny - */ - -#ifndef IREFRESHMANAGER_H_ -#define IREFRESHMANAGER_H_ - -#include -#include -#include "../Configuration.h" -#include "../scheduling/CommandSchedule.h" - -namespace core { - -class IRefreshManager -{ -public: - virtual ~IRefreshManager() {} - - /* - *Checks whether a schedule collides with the next planned refresh - */ - virtual bool hasCollision(const CommandSchedule& schedule) = 0; - - /* - *Schedules the next planned refresh if it's start time is not in the past - */ - virtual void scheduleRefresh(sc_time time) = 0; -}; - -} /* namespace controller */ - -#endif /* IREFRESHMANAGER_H_ */ diff --git a/dram/src/core/refresh/RefreshManager.cpp b/dram/src/core/refresh/RefreshManager.cpp index 35f83390..f71f5a68 100644 --- a/dram/src/core/refresh/RefreshManager.cpp +++ b/dram/src/core/refresh/RefreshManager.cpp @@ -12,7 +12,7 @@ using namespace std; namespace core { -RefreshManager::RefreshManager(DramController& controller) : controller(controller) +RefreshManager::RefreshManager(Controller& controller) : controller(controller) { assert(!controller.config.Timings.refreshTimings.empty()); @@ -37,13 +37,10 @@ bool RefreshManager::hasCollision(const CommandSchedule& schedule) return manager.hasCollision(schedule); } -void RefreshManager::scheduleRefresh(sc_time time) +void RefreshManager::scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time time) { - for (unsigned int i = 0; i < refreshManagerForBanks.size(); ++i) - { - RefreshManagerForBank& manager = *refreshManagerForBanks.at(i); - manager.scheduleRefresh(time); - } + RefreshManagerForBank& manager = *refreshManagerForBanks.at(DramExtension::getExtension(payload).getBank().ID()); + manager.scheduleRefresh(time); } } /* namespace controller */ diff --git a/dram/src/core/refresh/RefreshManager.h b/dram/src/core/refresh/RefreshManager.h index 9da5cc77..a23b4f19 100644 --- a/dram/src/core/refresh/RefreshManager.h +++ b/dram/src/core/refresh/RefreshManager.h @@ -8,25 +8,25 @@ #ifndef BANKWISEREFRESHMANAGER_H_ #define BANKWISEREFRESHMANAGER_H_ -#include "IRefreshManager.h" +#include "../scheduling/CommandSchedule.h" #include "../../common/dramExtension.h" #include "RefreshManagerForBank.h" namespace core { -class DramController; +class Controller; -class RefreshManager : public IRefreshManager +class RefreshManager { public: - RefreshManager(DramController& controller); - virtual ~RefreshManager(); + RefreshManager(Controller& controller); + ~RefreshManager(); - virtual bool hasCollision(const CommandSchedule& schedule); - virtual void scheduleRefresh(sc_time time); + bool hasCollision(const CommandSchedule& schedule); + void scheduleRefresh(tlm::tlm_generic_payload& payload, sc_time time); private: - DramController& controller; + Controller& controller; std::vector refreshManagerForBanks; }; diff --git a/dram/src/core/refresh/RefreshManagerForBank.cpp b/dram/src/core/refresh/RefreshManagerForBank.cpp index 4c61304f..af731d13 100644 --- a/dram/src/core/refresh/RefreshManagerForBank.cpp +++ b/dram/src/core/refresh/RefreshManagerForBank.cpp @@ -9,20 +9,18 @@ #include "../utils/Utils.h" #include "../Controller.h" - namespace core { -RefreshManagerForBank::RefreshManagerForBank(DramController& controller, Bank bank) : controller(controller), timing(controller.config.Timings.refreshTimings.at(bank.ID())) +RefreshManagerForBank::RefreshManagerForBank(Controller& controller, Bank bank) : + controller(controller), timing(controller.config.Timings.refreshTimings.at(bank.ID())), bank( + bank), nextPlannedRefresh(SC_ZERO_TIME) { - setupTransaction(refreshTransaction, bank); - nextPlannedRefresh = new ScheduledCommand(refreshTransaction, Refresh, SC_ZERO_TIME, - timing.tRFC); - planNextRefresh(*nextPlannedRefresh); + setupTransaction(refreshTransaction); + planNextRefresh(); } RefreshManagerForBank::~RefreshManagerForBank() { - delete nextPlannedRefresh; } /* @@ -33,7 +31,7 @@ RefreshManagerForBank::~RefreshManagerForBank() */ bool RefreshManagerForBank::hasCollision(const CommandSchedule& schedule) { - if (schedule.getEnd() < nextPlannedRefresh->getStart()) + if (schedule.getEnd() < nextPlannedRefresh) { return false; } @@ -45,27 +43,65 @@ bool RefreshManagerForBank::hasCollision(const CommandSchedule& schedule) void RefreshManagerForBank::scheduleRefresh(sc_time time) { - if (time == nextPlannedRefresh->getStart()) - scheduleRefresh(*nextPlannedRefresh); + if (time == nextPlannedRefresh) + { + controller.recorder.introduceNewTransactionToSystem(time, refreshTransaction); + + if (controller.config.RefreshBankwise) + { + if (controller.state.bankStates.rowBufferIsOpen(bank)) + { + ScheduledCommand precharge(refreshTransaction, Command::Precharge, time, + controller.config.Timings.tRP); + controller.busChecker.findSlotOnBus(precharge); + ScheduledCommand nextRefresh(refreshTransaction, Command::AutoRefresh, + precharge.getEnd(), timing.tRFC); + controller.busChecker.findSlotOnBus(nextRefresh); + controller.state.change(precharge); + controller.state.change(nextRefresh); + precharge.record(controller.recorder); + nextRefresh.record(controller.recorder); + controller.wrapper.send(precharge); + controller.wrapper.send(nextRefresh); + controller.recorder.removeTransactionFromSystem(nextRefresh.getEnd(),refreshTransaction); + } + else + { + ScheduledCommand nextRefresh(refreshTransaction, Command::AutoRefresh, time, + timing.tRFC); + controller.busChecker.findSlotOnBus(nextRefresh); + controller.state.change(nextRefresh); + nextRefresh.record(controller.recorder); + controller.wrapper.send(nextRefresh); + controller.recorder.removeTransactionFromSystem(nextRefresh.getEnd(),refreshTransaction); + } + } + else + { + ScheduledCommand precharge(refreshTransaction, Command::PrechargeAll, time, + controller.config.Timings.tRP); + ScheduledCommand nextRefresh(refreshTransaction, Command::AutoRefresh, + precharge.getEnd(), timing.tRFC); + controller.state.change(precharge); + controller.state.change(nextRefresh); + precharge.record(controller.recorder); + nextRefresh.record(controller.recorder); + controller.wrapper.send(precharge); + controller.wrapper.send(nextRefresh); + controller.recorder.removeTransactionFromSystem(nextRefresh.getEnd(),refreshTransaction); + } + + planNextRefresh(); + } } -void RefreshManagerForBank::scheduleRefresh(ScheduledCommand& refresh) +void RefreshManagerForBank::planNextRefresh() { - if(controller.config.RefreshBankwise) - controller.busChecker.findSlotOnBus(refresh); - - controller.state.change(refresh); - controller.wrapper.send(refresh); - planNextRefresh(refresh); + nextPlannedRefresh += timing.tREFI; + controller.wrapper.send(RefreshTrigger, nextPlannedRefresh, refreshTransaction); } -void RefreshManagerForBank::planNextRefresh(ScheduledCommand& refresh) //TODO nicer to return the reference ? -{ - refresh.delayStart(timing.tREFI); - controller.wrapper.send(RefreshTrigger, refresh.getStart()); -} - -void RefreshManagerForBank::setupTransaction(tlm::tlm_generic_payload& transaction, Bank bank) +void RefreshManagerForBank::setupTransaction(tlm::tlm_generic_payload& transaction) { transaction.set_address(getStartAddress(bank)); transaction.set_command(tlm::TLM_READ_COMMAND); @@ -74,7 +110,6 @@ void RefreshManagerForBank::setupTransaction(tlm::tlm_generic_payload& transacti transaction.set_dmi_allowed(false); transaction.set_byte_enable_length(0); transaction.set_streaming_width(0); - transaction.set_extension(new DramExtension(Thread(0), bank, Row(0), Column(0))); //payload takes ownership } diff --git a/dram/src/core/refresh/RefreshManagerForBank.h b/dram/src/core/refresh/RefreshManagerForBank.h index 975b19e1..2ebc0507 100644 --- a/dram/src/core/refresh/RefreshManagerForBank.h +++ b/dram/src/core/refresh/RefreshManagerForBank.h @@ -8,33 +8,34 @@ #ifndef REFRESHMANAGER_H_ #define REFRESHMANAGER_H_ -#include "IRefreshManager.h" +#include "../TimingConfiguration.h" +#include "../scheduling/CommandSchedule.h" #include "../../common/dramExtension.h" +#include namespace core { -class DramController; +class Controller; class RefreshManagerForBank { public: - RefreshManagerForBank(DramController& controller, Bank bank); - virtual ~RefreshManagerForBank(); + RefreshManagerForBank(Controller& controller, Bank bank); + ~RefreshManagerForBank(); - virtual bool hasCollision(const CommandSchedule& schedule); - virtual void scheduleRefresh(sc_time time); + bool hasCollision(const CommandSchedule& schedule); + void scheduleRefresh(sc_time time); private: - DramController& controller; + Controller& controller; RefreshTiming& timing; + Bank bank; tlm::tlm_generic_payload refreshTransaction; - ScheduledCommand* nextPlannedRefresh; + sc_time nextPlannedRefresh; - void scheduleRefresh(ScheduledCommand& refresh); - void planNextRefresh(ScheduledCommand& refresh); - - static void setupTransaction(tlm::tlm_generic_payload& transaction, Bank bank); + void planNextRefresh(); + void setupTransaction(tlm::tlm_generic_payload& transaction); }; } /* namespace controller */ diff --git a/dram/src/core/scheduling/CommandSchedule.h b/dram/src/core/scheduling/CommandSchedule.h index 48b6be69..c6806da8 100644 --- a/dram/src/core/scheduling/CommandSchedule.h +++ b/dram/src/core/scheduling/CommandSchedule.h @@ -10,8 +10,8 @@ #include #include "../../common/dramExtension.h" +#include "../../common/TlmRecorder.h" #include "ScheduledCommand.h" - namespace core { class CommandSchedule @@ -58,6 +58,14 @@ public: return extension.getBank(); } + void record(TlmRecorder& recorder) + { + for(ScheduledCommand& command : scheduledCommands) + { + command.record(recorder); + } + } + private: std::vector scheduledCommands; tlm::tlm_generic_payload* transaction; diff --git a/dram/src/core/scheduling/CommandSequenceGenerator.cpp b/dram/src/core/scheduling/CommandSequenceGenerator.cpp index ababbbfd..b01aaa81 100644 --- a/dram/src/core/scheduling/CommandSequenceGenerator.cpp +++ b/dram/src/core/scheduling/CommandSequenceGenerator.cpp @@ -43,7 +43,7 @@ CommandSequence CommandSequenceGenerator::generateCommandSequence( CommandSequence CommandSequenceGenerator::getBankMissCommandSequence(tlm::tlm_generic_payload& transaction) { vector result; - result.push_back(Activate); + result.push_back(Command::Activate); result.push_back(getReadWriteCommand(transaction)); return result; } @@ -51,8 +51,8 @@ CommandSequence CommandSequenceGenerator::getBankMissCommandSequence(tlm::tlm_ge CommandSequence CommandSequenceGenerator::getRowMissCommandSequence(tlm::tlm_generic_payload& transaction) { vector result; - result.push_back(Precharge); - result.push_back(Activate); + result.push_back(Command::Precharge); + result.push_back(Command::Activate); result.push_back(getReadWriteCommand(transaction)); return result; } @@ -69,11 +69,11 @@ Command CommandSequenceGenerator::getReadWriteCommand(tlm::tlm_generic_payload& if (transaction.get_command() == tlm::TLM_READ_COMMAND) { //TODO READA - return Read; + return Command::Read; } else { - return Write; + return Command::Write; } } diff --git a/dram/src/core/scheduling/CommandSequenceScheduler.h b/dram/src/core/scheduling/CommandSequenceScheduler.h index c5e130cc..58ab94c1 100644 --- a/dram/src/core/scheduling/CommandSequenceScheduler.h +++ b/dram/src/core/scheduling/CommandSequenceScheduler.h @@ -12,18 +12,18 @@ namespace core { -class DramController; +class Controller; class CommandSequenceScheduler { public: - CommandSequenceScheduler(DramController& controller) : controller(controller){} + CommandSequenceScheduler(Controller& controller) : controller(controller){} virtual ~CommandSequenceScheduler(){} CommandSchedule schedule(CommandSequence commands, sc_time start, tlm::tlm_generic_payload& transaction); private: - DramController& controller; + Controller& controller; }; } /* namespace controller */ diff --git a/dram/src/core/scheduling/ScheduledCommand.h b/dram/src/core/scheduling/ScheduledCommand.h index 1cfee85d..954c1bff 100644 --- a/dram/src/core/scheduling/ScheduledCommand.h +++ b/dram/src/core/scheduling/ScheduledCommand.h @@ -12,6 +12,7 @@ #include #include "../Command.h" #include "../../common/dramExtension.h" +#include "../../common/TlmRecorder.h" namespace core { @@ -19,21 +20,21 @@ class ScheduledCommand { public: - ScheduledCommand(tlm::tlm_generic_payload& transaction, Command command, sc_time time, + ScheduledCommand(tlm::tlm_generic_payload& payload, Command command, sc_time time, sc_time executionTime) : - transaction(&transaction), command(command), start(time), executionTime(executionTime), extension( - DramExtension::getExtension(&transaction)) + payload(&payload), command(command), start(time), executionTime(executionTime), extension( + DramExtension::getExtension(payload)) { } ScheduledCommand() : - transaction(NULL), command(NOP), start(SC_ZERO_TIME), executionTime(SC_ZERO_TIME), extension() + payload(NULL), command(Command::NOP), start(SC_ZERO_TIME), executionTime(SC_ZERO_TIME), extension() { } bool isNoCommand() const { - return (command == NOP && start == SC_ZERO_TIME && executionTime == SC_ZERO_TIME); + return (command == Command::NOP && start == SC_ZERO_TIME && executionTime == SC_ZERO_TIME); } bool isValidCommand() const @@ -73,8 +74,8 @@ public: tlm::tlm_generic_payload& getTransaction() const { - sc_assert(transaction); - return *transaction; + sc_assert(payload); + return *payload; } Bank getBank() const @@ -94,11 +95,16 @@ public: void invalidateTransaction() { - transaction = NULL; + payload = NULL; + } + + void record(TlmRecorder& recorder) + { + recorder.recordPhase(*payload, commandToString(command), getStart(), getEnd()); } private: - tlm::tlm_generic_payload* transaction; + tlm::tlm_generic_payload* payload; Command command; sc_time start; diff --git a/dram/src/core/scheduling/checker/ActivateChecker.cpp b/dram/src/core/scheduling/checker/ActivateChecker.cpp index e519c6af..dc1a1078 100644 --- a/dram/src/core/scheduling/checker/ActivateChecker.cpp +++ b/dram/src/core/scheduling/checker/ActivateChecker.cpp @@ -16,7 +16,7 @@ namespace core { void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand& command) const { - sc_assert(command.getCommand() == Activate); + sc_assert(command.getCommand() == Command::Activate); ScheduledCommand lastCommandOnBank = state.getLastCommand(command.getBank()); if(lastCommandOnBank.isValidCommand()) @@ -32,13 +32,13 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand& command) const sc_time ActivateChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const { - assert(command == Activate); + assert(command == Command::Activate); return config.Timings.tRCD; } void ActivateChecker::satisfy_activateToActivate_differentBank(ScheduledCommand& command) const { - ScheduledCommand lastActivate = state.getLastCommand(Activate); + ScheduledCommand lastActivate = state.getLastCommand(Command::Activate); if (lastActivate.isValidCommand()) command.delayStart( delayByConstraint(lastActivate.getStart(), command.getStart(), @@ -47,7 +47,7 @@ void ActivateChecker::satisfy_activateToActivate_differentBank(ScheduledCommand& void ActivateChecker::satisfy_activateToActivate_sameBank(ScheduledCommand& command) const { - ScheduledCommand lastActivateOnBank = state.getLastCommand(Activate, command.getBank()); + ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::Activate, command.getBank()); if (lastActivateOnBank.isValidCommand()) command.delayStart( delayByConstraint(lastActivateOnBank.getStart(), command.getStart(), diff --git a/dram/src/core/scheduling/checker/PrechargeChecker.cpp b/dram/src/core/scheduling/checker/PrechargeChecker.cpp index 412cc805..a5ede2a0 100644 --- a/dram/src/core/scheduling/checker/PrechargeChecker.cpp +++ b/dram/src/core/scheduling/checker/PrechargeChecker.cpp @@ -11,7 +11,7 @@ namespace core { void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand& command) const { - sc_assert(command.getCommand() == Precharge || command.getCommand() == PrechargeAll); + sc_assert(command.getCommand() == Command::Precharge || command.getCommand() == Command::PrechargeAll); ScheduledCommand lastCommandOnBank = state.getLastCommand(command.getBank()); if(lastCommandOnBank.isValidCommand()) sc_assert(command.getStart() >= state.getLastCommand(command.getBank()).getStart()); @@ -20,7 +20,7 @@ void PrechargeChecker::delayToSatisfyConstraints(ScheduledCommand& command) cons sc_time PrechargeChecker::getExecutionTime(const tlm::tlm_generic_payload& payload, Command command) const { - sc_assert(command == Precharge || command == PrechargeAll); + sc_assert(command == Command::Precharge || command == Command::PrechargeAll); return config.Timings.tRP; } diff --git a/dram/src/core/scheduling/checker/ReadChecker.cpp b/dram/src/core/scheduling/checker/ReadChecker.cpp index 9075a3a6..ff633b0e 100644 --- a/dram/src/core/scheduling/checker/ReadChecker.cpp +++ b/dram/src/core/scheduling/checker/ReadChecker.cpp @@ -23,7 +23,7 @@ void ReadChecker::delayToSatisfyConstraints(ScheduledCommand& command) const sc_time ReadChecker::getExecutionTime(const tlm::tlm_generic_payload& payload, Command command) const { - assert(command == Read || command == ReadA); + assert(command == Command::Read || command == Command::ReadA); //return config.Timings.tRL + config.Timings.clk*getBurstLengthInBytes(transaction, config.buswidth); sc_time result = config.Timings.tRL + config.Timings.clk*payload.get_streaming_width(); return result; diff --git a/dram/src/core/scheduling/checker/WriteChecker.cpp b/dram/src/core/scheduling/checker/WriteChecker.cpp index dd465dee..305d0d60 100644 --- a/dram/src/core/scheduling/checker/WriteChecker.cpp +++ b/dram/src/core/scheduling/checker/WriteChecker.cpp @@ -22,7 +22,7 @@ void WriteChecker::delayToSatisfyConstraints(ScheduledCommand& command) const sc_time WriteChecker::getExecutionTime(const tlm::tlm_generic_payload& payload, Command command) const { - assert(command == Write || command == WriteA); + assert(command == Command::Write || command == Command::WriteA); return config.Timings.clk*8; } diff --git a/dram/src/core/utils/Utils.cpp b/dram/src/core/utils/Utils.cpp index 7efb74dc..1953ce20 100644 --- a/dram/src/core/utils/Utils.cpp +++ b/dram/src/core/utils/Utils.cpp @@ -16,6 +16,7 @@ unsigned int getBurstLengthInBytes(const tlm::tlm_generic_payload& payload, unsi { return payload.get_data_length() / (buswidth/8); } + sc_time delayByConstraint(sc_time previous, sc_time start, sc_time constraint) { if (previous + constraint > start) diff --git a/dram/src/core/utils/Utils.h b/dram/src/core/utils/Utils.h index c9850e78..30dd817a 100644 --- a/dram/src/core/utils/Utils.h +++ b/dram/src/core/utils/Utils.h @@ -18,7 +18,6 @@ unsigned int getBurstLengthInBytes(const tlm::tlm_generic_payload& payload, unsi sc_time delayByConstraint(sc_time previous, sc_time start, sc_time constraint); enum Alignment {UP, DOWN}; - const sc_time clkAlign(sc_time time, sc_time clk, Alignment alignment = UP); bool isClkAligned(sc_time time, sc_time clk); diff --git a/dram/src/simulation/MemoryManager.cpp b/dram/src/simulation/MemoryManager.cpp index 35cf28b0..7777836d 100644 --- a/dram/src/simulation/MemoryManager.cpp +++ b/dram/src/simulation/MemoryManager.cpp @@ -29,17 +29,17 @@ MemoryManager::~MemoryManager() gp* MemoryManager::allocate() { - //if(freePayloads.empty()) - //{ - //numberOfAllocations++; + if(freePayloads.empty()) + { + numberOfAllocations++; return new gp(this); - //} - //else - //{ -// gp* result = freePayloads.back(); -// freePayloads.pop_back(); -// return result; -// } + } + else + { + gp* result = freePayloads.back(); + freePayloads.pop_back(); + return result; + } } void MemoryManager::free(gp* payload) diff --git a/dram/src/simulation/controllerwrapper.h b/dram/src/simulation/controllerwrapper.h index 6d175071..e178d09e 100644 --- a/dram/src/simulation/controllerwrapper.h +++ b/dram/src/simulation/controllerwrapper.h @@ -15,9 +15,11 @@ #include #include #include +#include #include "../common/protocol.h" -#include "../common/tlmDBPhaseRecorder.h" +#include "../common/TlmRecorder.h" +#include "../common/DebugManager.h" #include "../core/IWrapperConnector.h" #include "../core/Controller.h" #include "../scheduler/Scheduler.h" @@ -36,12 +38,12 @@ public: tlm_utils::simple_initiator_socket iSocket; tlm_utils::simple_target_socket tSocket; - ControllerWrapper(sc_module_name name, tlmDBPhaseRecorder& tpr): + ControllerWrapper(sc_module_name name, TlmRecorder& recorder): frontendPEQ(this, &ControllerWrapper::frontendPEQCallback), dramPEQ( this, &ControllerWrapper::dramPEQCallback), controllerPEQ(this, - &ControllerWrapper::controllerPEQCallback), tpr(tpr) + &ControllerWrapper::controllerPEQCallback), recorder(recorder), debugManager(DebugManager::getInstance()) { - controller = new DramController(*this); + controller = new Controller(*this, recorder); scheduler = new Fifo(controller->getBankStates()); inputBufferDelay = controller->config.Timings.clk; iSocket.register_nb_transport_bw(this, &ControllerWrapper::nb_transport_bw); @@ -60,43 +62,43 @@ public: virtual void send(const ScheduledCommand& command) override { assert(command.getStart() >= sc_time_stamp()); - sc_time delay = command.getStart() - sc_time_stamp(); - tlm::tlm_phase phase; switch (command.getCommand()) { - case Read: - phase = BEGIN_RD; + case Command::Read: + dramPEQ.notify(command.getTransaction(),BEGIN_RD, command.getStart() - sc_time_stamp()); + dramPEQ.notify(command.getTransaction(),END_RD, command.getEnd() - sc_time_stamp()); break; - case Write: - phase = BEGIN_WR; + case Command::Write: + dramPEQ.notify(command.getTransaction(),BEGIN_WR, command.getStart() - sc_time_stamp()); + dramPEQ.notify(command.getTransaction(),END_WR, command.getEnd() - sc_time_stamp()); break; - case Refresh: - phase = BEGIN_AUTO_REFRESH; + case Command::AutoRefresh: + dramPEQ.notify(command.getTransaction(),BEGIN_AUTO_REFRESH, command.getStart() - sc_time_stamp()); + dramPEQ.notify(command.getTransaction(),END_AUTO_REFRESH, command.getEnd() - sc_time_stamp()); break; - case Activate: - phase = BEGIN_ACT; + case Command::Activate: break; - case Precharge: - phase = BEGIN_PRE; + case Command::Precharge: + break; + case Command::PrechargeAll: break; default: SC_REPORT_FATAL(0, "unsupported command in controller wrapper"); break; } - dramPEQ.notify(command.getTransaction(), phase, delay); } - virtual void send(Trigger trigger, sc_time time) override + virtual void send(Trigger trigger, sc_time time, tlm_generic_payload& payload) override { assert(time >= sc_time_stamp()); sc_time delay = time - sc_time_stamp(); - controllerPEQ.notify(triggerDummy, REFRESH_TRIGGER, delay); + controllerPEQ.notify(payload, REFRESH_TRIGGER, delay); } private: - DramController* controller; + Controller* controller; Scheduler* scheduler; map bankIsFreeForRequest; @@ -105,15 +107,12 @@ private: tlm_utils::peq_with_cb_and_phase controllerPEQ; sc_time inputBufferDelay; - tlm::tlm_generic_payload triggerDummy; - tlmDBPhaseRecorder& tpr; - + TlmRecorder& recorder; + DebugManager& debugManager; void payloadEntersSystem(tlm_generic_payload& payload) { - //std::cout << "----------------------------------------------------------------------- " << std::endl; - //std::cout << "Transaction enters system at " << sc_time_stamp() << std::endl; - + printDebugMessage("Transaction enters system"); Bank bank = DramExtension::getExtension(payload).getBank(); scheduler->schedule(&payload); scheduleNextPayload(bank); @@ -121,23 +120,18 @@ private: void scheduleNextPayload(Bank bank) { - //std::cout << "----------------------------------------------------------------------- " << std::endl; - //std::cout << "In trigger for bank " << bank.ID() << std::endl; - + printDebugMessage("In trigger for bank " + to_string(bank.ID())); if(controller->isBusy(sc_time_stamp(), bank)) return; + else if(scheduler->hasTransactionForBank(bank)) { tlm_generic_payload* nextTransaction = scheduler->getTransactionForBank(bank); if(controller->schedule(sc_time_stamp(), *nextTransaction)) { - //std::cout << "Next payload was scheduled by core " << std::endl; + printDebugMessage("Next payload was scheduled by core"); scheduler->popTransactionForBank(bank); } - else - { - //std::cout << "Next payload was not scheduled because of refresh " << std::endl; - } } } @@ -147,10 +141,8 @@ private: } - // Initiated by dram tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay) { - dramPEQ.notify(payload, phase, bwDelay); return TLM_ACCEPTED; } @@ -158,7 +150,7 @@ private: tlm_sync_enum nb_transport_fw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& fwDelay) { DramExtension::getExtension(payload); - tpr.recordPhase(payload,phase,sc_time_stamp()); + recorder.recordPhase(payload,phase,sc_time_stamp()); if (phase == BEGIN_REQ) { @@ -181,7 +173,7 @@ private: { payloadEntersSystem(payload); payload.set_response_status(tlm::TLM_OK_RESPONSE); - tpr.recordPhase(payload, END_REQ, sc_time_stamp()); + recorder.recordPhase(payload, END_REQ, sc_time_stamp()); sendToFrontend(payload, END_REQ, SC_ZERO_TIME); } else @@ -193,24 +185,13 @@ private: void dramPEQCallback(tlm_generic_payload& payload, const tlm_phase& phase) { - tpr.recordPhase(payload,phase,sc_time_stamp()); - DramExtension *result = NULL; - payload.get_extension(result); - if(result==NULL) - { - cout << "ERROR AT TIME " << sc_time_stamp() << std::endl; - cout << "Payload " << payload.get_address() << " " << phase; - - assert(result != NULL); - } if (phase == BEGIN_RD || phase == BEGIN_WR) { - //std::cout << "BEGIN_RD at " <scheduleRefresh(sc_time_stamp()); + controller->scheduleRefresh(payload, sc_time_stamp()); } else { @@ -262,6 +245,11 @@ private: tSocket->nb_transport_bw(payload, TPhase, TDelay); } + void printDebugMessage(string message, Importance importance = Importance::Info) + { + debugManager.printDebugMessage(message,Sender::DramWrapper,importance); + } + }; #endif /* CONTROLLERWRAPPER_H_ */ diff --git a/dram/src/simulation/dram.h b/dram/src/simulation/dram.h index bed5a8ac..b5dbbc58 100644 --- a/dram/src/simulation/dram.h +++ b/dram/src/simulation/dram.h @@ -25,7 +25,6 @@ using namespace sc_dt; using namespace std; using namespace tlm; -xmlConfig xc; template struct Dram: sc_module @@ -33,6 +32,7 @@ struct Dram: sc_module tlm_utils::simple_target_socket tSocket; sc_event target_done_event; tlm_utils::peq_with_cb_and_phase m_peq; + xmlConfig xc; SC_CTOR(Dram) : tSocket("socket") ,m_peq(this, &Dram::peq_cb) { diff --git a/dram/src/simulation/main.cpp b/dram/src/simulation/main.cpp index 8b978fd8..b1e4044e 100644 --- a/dram/src/simulation/main.cpp +++ b/dram/src/simulation/main.cpp @@ -10,7 +10,7 @@ #include #include #include -#include "../common/tlmDBPhaseRecorder.h" +#include "../common/TlmRecorder.h" #include "../common/DebugManager.h" #include "../common/xmlAddressdecoder.h" #include "controllerwrapper.h" @@ -29,11 +29,13 @@ string pathOfFile(string file) int sc_main(int argc, char **argv) { - string resources = pathOfFile(argv[0]) + string("/../resources/"); + sc_set_time_resolution(1,SC_NS); + + string resources = pathOfFile(argv[0]) + string("/../resources/"); + xmlAddressDecoder::addressConfigURI = resources + string("configs/addressConfig.xml"); + TlmRecorder recorder("tpr.tdb", resources + string("scripts/createTraceDB.sql")); + TracePlayer<> player("player", resources + string("traces/chstone-mips_32.stl")); - xmlAddressDecoder::URI = resources + string("configs/addressConfig.xml"); - tlmDBPhaseRecorder recorder("tpr.tdb", resources + string("scripts/createTraceDB.sql")); - TracePlayer<> player("player", resources + string("traces/mediabench-h263encode_32.stl")); Dram<> dram("dram"); Arbiter<> arbiter("arbiter"); ControllerWrapper<> controller("controller", recorder); @@ -42,10 +44,12 @@ int sc_main(int argc, char **argv) arbiter.iSocket.bind(controller.tSocket); controller.iSocket.bind(dram.tSocket); - //DebugManager::getInstance().addToWhiteList(Sender::TraceRecorder); + DebugManager::getInstance().addToWhiteList(Sender::TraceRecorder); + DebugManager::getInstance().addToWhiteList(Sender::TracePlayer); cout << "Toplevel: simulation start" << std::endl; clock_t begin = clock(); + sc_start(); clock_t end = clock(); double elapsed_secs = double(end - begin) / CLOCKS_PER_SEC; @@ -58,7 +62,7 @@ int sc_main(int argc, char **argv) //system(runTestCommand.c_str()); string run_tpr = - "/home/jonny/git/analyzer/build-traceAnalyzer-Desktop-Debug/traceAnalyzer tpr.tdb"; + "/home/robert/analyzer/build/traceAnalyzer tpr.tdb"; system(run_tpr.c_str()); return 0; } diff --git a/dram/src/simulation/traceplayer.h b/dram/src/simulation/traceplayer.h index b8c19b15..4a9ac641 100644 --- a/dram/src/simulation/traceplayer.h +++ b/dram/src/simulation/traceplayer.h @@ -28,7 +28,6 @@ struct TracePlayer: public sc_module { public: tlm_utils::simple_initiator_socket iSocket; - unsigned int transactionsSent; TracePlayer(sc_module_name name, string pathToTrace) : payloadEventQueue(this, &TracePlayer::peqCallback), file(pathToTrace), numberOfPendingTransactions(0), transactionsSent(0) @@ -51,6 +50,8 @@ private: MemoryManager memoryManager; ifstream file; unsigned int numberOfPendingTransactions; + unsigned int transactionsSent; + void scheduleNextPayload() { @@ -115,7 +116,7 @@ private: payload.acquire(); sendToTarget(payload,phase,SC_ZERO_TIME); transactionsSent++; - DebugManager::getInstance().printDebug("Sending transaction number: " + std::to_string(transactionsSent), Sender::TracePlayer); + DebugManager::getInstance().printDebugMessage("Sending transaction number: " + std::to_string(transactionsSent), Sender::TracePlayer); } else if (phase == END_REQ) @@ -128,7 +129,7 @@ private: sendToTarget(payload,END_RESP,SC_ZERO_TIME); numberOfPendingTransactions--; - DebugManager::getInstance().printDebug("Number of pending transactions: " + std::to_string(numberOfPendingTransactions), Sender::TracePlayer); + DebugManager::getInstance().printDebugMessage("Number of pending transactions: " + std::to_string(numberOfPendingTransactions), Sender::TracePlayer); if(numberOfPendingTransactions == 0) payloadEventQueue.notify(payload, END_RESP, SC_ZERO_TIME); }