Timing Compliance Test

This commit is contained in:
Felipe S. Prado
2016-10-11 14:31:40 +02:00
parent 4aaf84766f
commit 04822fbff2
3 changed files with 159 additions and 0 deletions

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<memconfig>
<BankwiseLogic value="1"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FIFO_STRICT" />
<Capsize value="5" />
<PowerDownMode value="TimeoutSREF" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
<StoreMode value="NoStorage" />
</memconfig>

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<simulation>
<!-- General Simulator Configuration (used for all simulation setups) -->
<simconfig>
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="0" />
<EnableWindowing value = "0" />
<WindowSize value="1000" />
<NumberOfTracePlayers value="1"/>
<NumberOfMemChannels value="4"/>
<ControllerCoreDisableRefresh value="0"/>
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfDevicesOnDIMM value = "1" />
<CheckTLM2Protocol value = "0" />
</simconfig>
<!-- Temperature Simulator Configuration (used for all simulation setups) -->
<thermalsimconfig>
<TemperatureScale value="Celsius" />
<StaticTemperatureDefaultValue value="89" />
<ThermalSimPeriod value="10" />
<ThermalSimUnit value="ms" />
<PowerInfoFile value="../../DRAMSys/simulator/resources/configs/thermalsim/powerInfo.xml"/>
<IceServerIp value="127.0.0.1" />
<IceServerPort value="11880" />
<SimPeriodAdjustFactor value="10" />
<NPowStableCyclesToIncreasePeriod value="5" />
<GenerateTemperatureMap value="1" />
<GeneratePowerMap value="1" />
</thermalsimconfig>
<memspecs>
<memspec src="../../DRAMSys/simulator/resources/configs/memspecs/WideIO.xml"></memspec>
</memspecs>
<addressmappings>
<addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
</addressmappings>
<memconfigs>
<memconfig src="../../DRAMSys/tests/timing_compliance/fifoStrict.xml"/>
</memconfigs>
<tracesetups>
<tracesetup id="timing_compliance_test_fifoStrict">
<device clkMhz="200">chstone-jpeg_32.stl</device>
</tracesetup>
</tracesetups>
</simulation>

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#!/usr/bin/perl -w
# Copyright (c) 2016, University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors:
# Matthias Jung, Felipe S. Prado
#
# Test Timing Compliance:
# This test runs the simulation with standard configuration
# Run Simulation:
$bankwiseLogicLine = `grep -n '<BankwiseLogic value=' fifoStrict.xml | cut -d: -f 1`;
chomp $bankwiseLogicLine;
$powerAnalysisLine = `grep -n '<PowerAnalysis value=' sim-batch.xml | cut -d: -f 1`;
chomp $powerAnalysisLine;
$powerDownModeLine = `grep -n '<PowerDownMode value=' fifoStrict.xml | cut -d: -f 1`;
chomp $powerDownModeLine;
$powerDownModes = `grep 'enum class EPowerDownMode' ../../simulator/src/controller/core/configuration/Configuration.h | cut -d } -f 1 | sed 's/ //g' | cut -d { -f 2`;
@powerDownModes = split(/,/,$powerDownModes);
chomp @powerDownModes;
chdir("../../../build/simulator/");
foreach (@powerDownModes)
{
system("sed -i '" . $powerAnalysisLine . "s^.*^ <PowerAnalysis value=\"1\" />^' ../../DRAMSys/tests/timing_compliance/sim-batch.xml");
system("sed -i '" . $bankwiseLogicLine . "s^.*^ <BankwiseLogic value=\"0\"/>^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
system("sed -i '" . $powerDownModeLine . "s^.*^ <PowerDownMode value=\"$_\" />^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
`./dramSys ../../DRAMSys/tests/timing_compliance/sim-batch.xml`;
@files = `ls sim-batch/timing_compliance_test_fifoStrict_channel*.tdb`;
chomp @files;
foreach (@files)
{
`python3.5 ../../DRAMSys/analyzer/scripts/tests.py $_ > ../../DRAMSys/tests/timing_compliance/output.txt`;
if("All tests passed\n" ne `grep "All tests passed" ../../DRAMSys/tests/timing_compliance/output.txt`)
{
exit -1;
}
}
system("sed -i '" . $powerAnalysisLine . "s^.*^ <PowerAnalysis value=\"0\" />^' ../../DRAMSys/tests/timing_compliance/sim-batch.xml");
system("sed -i '" . $bankwiseLogicLine . "s^.*^ <BankwiseLogic value=\"1\"/>^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
`./dramSys ../../DRAMSys/tests/timing_compliance/sim-batch.xml`;
foreach (@files)
{
`python3.5 ../../DRAMSys/analyzer/scripts/tests.py $_ > ../../DRAMSys/tests/timing_compliance/output.txt`;
if("All tests passed\n" ne `grep "All tests passed" ../../DRAMSys/tests/timing_compliance/output.txt`)
{
exit -1;
}
}
}
exit 0;