Timing Compliance Test
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15
DRAMSys/tests/timing_compliance/fifoStrict.xml
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15
DRAMSys/tests/timing_compliance/fifoStrict.xml
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<memconfig>
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<BankwiseLogic value="1"/>
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<OpenPagePolicy value="1" />
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<MaxNrOfTransactions value="8" />
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<Scheduler value="FIFO_STRICT" />
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<Capsize value="5" />
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<PowerDownMode value="TimeoutSREF" />
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<PowerDownTimeout value="100" />
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<!-- Error Modelling -->
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<ErrorChipSeed value="42" />
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<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
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<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
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<StoreMode value="NoStorage" />
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</memconfig>
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52
DRAMSys/tests/timing_compliance/sim-batch.xml
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52
DRAMSys/tests/timing_compliance/sim-batch.xml
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<simulation>
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<!-- General Simulator Configuration (used for all simulation setups) -->
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<simconfig>
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<Debug value="0" />
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<DatabaseRecording value="1" />
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<PowerAnalysis value="0" />
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<EnableWindowing value = "0" />
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<WindowSize value="1000" />
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<NumberOfTracePlayers value="1"/>
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<NumberOfMemChannels value="4"/>
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<ControllerCoreDisableRefresh value="0"/>
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<ThermalSimulation value="0"/>
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<SimulationProgressBar value="1"/>
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<NumberOfDevicesOnDIMM value = "1" />
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<CheckTLM2Protocol value = "0" />
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</simconfig>
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<!-- Temperature Simulator Configuration (used for all simulation setups) -->
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<thermalsimconfig>
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<TemperatureScale value="Celsius" />
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<StaticTemperatureDefaultValue value="89" />
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<ThermalSimPeriod value="10" />
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<ThermalSimUnit value="ms" />
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<PowerInfoFile value="../../DRAMSys/simulator/resources/configs/thermalsim/powerInfo.xml"/>
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<IceServerIp value="127.0.0.1" />
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<IceServerPort value="11880" />
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<SimPeriodAdjustFactor value="10" />
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<NPowStableCyclesToIncreasePeriod value="5" />
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<GenerateTemperatureMap value="1" />
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<GeneratePowerMap value="1" />
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</thermalsimconfig>
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<memspecs>
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<memspec src="../../DRAMSys/simulator/resources/configs/memspecs/WideIO.xml"></memspec>
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</memspecs>
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<addressmappings>
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<addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
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</addressmappings>
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<memconfigs>
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<memconfig src="../../DRAMSys/tests/timing_compliance/fifoStrict.xml"/>
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</memconfigs>
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<tracesetups>
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<tracesetup id="timing_compliance_test_fifoStrict">
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<device clkMhz="200">chstone-jpeg_32.stl</device>
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</tracesetup>
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</tracesetups>
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</simulation>
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92
DRAMSys/tests/timing_compliance/test.pl
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92
DRAMSys/tests/timing_compliance/test.pl
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#!/usr/bin/perl -w
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# Copyright (c) 2016, University of Kaiserslautern
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors:
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# Matthias Jung, Felipe S. Prado
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#
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# Test Timing Compliance:
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# This test runs the simulation with standard configuration
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# Run Simulation:
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$bankwiseLogicLine = `grep -n '<BankwiseLogic value=' fifoStrict.xml | cut -d: -f 1`;
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chomp $bankwiseLogicLine;
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$powerAnalysisLine = `grep -n '<PowerAnalysis value=' sim-batch.xml | cut -d: -f 1`;
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chomp $powerAnalysisLine;
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$powerDownModeLine = `grep -n '<PowerDownMode value=' fifoStrict.xml | cut -d: -f 1`;
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chomp $powerDownModeLine;
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$powerDownModes = `grep 'enum class EPowerDownMode' ../../simulator/src/controller/core/configuration/Configuration.h | cut -d } -f 1 | sed 's/ //g' | cut -d { -f 2`;
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@powerDownModes = split(/,/,$powerDownModes);
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chomp @powerDownModes;
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chdir("../../../build/simulator/");
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foreach (@powerDownModes)
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{
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system("sed -i '" . $powerAnalysisLine . "s^.*^ <PowerAnalysis value=\"1\" />^' ../../DRAMSys/tests/timing_compliance/sim-batch.xml");
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system("sed -i '" . $bankwiseLogicLine . "s^.*^ <BankwiseLogic value=\"0\"/>^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
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system("sed -i '" . $powerDownModeLine . "s^.*^ <PowerDownMode value=\"$_\" />^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
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`./dramSys ../../DRAMSys/tests/timing_compliance/sim-batch.xml`;
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@files = `ls sim-batch/timing_compliance_test_fifoStrict_channel*.tdb`;
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chomp @files;
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foreach (@files)
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{
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`python3.5 ../../DRAMSys/analyzer/scripts/tests.py $_ > ../../DRAMSys/tests/timing_compliance/output.txt`;
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if("All tests passed\n" ne `grep "All tests passed" ../../DRAMSys/tests/timing_compliance/output.txt`)
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{
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exit -1;
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}
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}
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system("sed -i '" . $powerAnalysisLine . "s^.*^ <PowerAnalysis value=\"0\" />^' ../../DRAMSys/tests/timing_compliance/sim-batch.xml");
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system("sed -i '" . $bankwiseLogicLine . "s^.*^ <BankwiseLogic value=\"1\"/>^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
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`./dramSys ../../DRAMSys/tests/timing_compliance/sim-batch.xml`;
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foreach (@files)
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{
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`python3.5 ../../DRAMSys/analyzer/scripts/tests.py $_ > ../../DRAMSys/tests/timing_compliance/output.txt`;
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if("All tests passed\n" ne `grep "All tests passed" ../../DRAMSys/tests/timing_compliance/output.txt`)
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{
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exit -1;
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}
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}
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}
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exit 0;
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