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Derek Christ
2024-03-20 16:03:13 +00:00
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@@ -100,14 +100,14 @@ In summary, this paper makes the following contributions:
\item A Rust library to provide the PIM functionality up to the software level
\end{itemize}
The paper is structured as follows. Section 2 Shows the realted work in the area of PIM-Simulation. Section 3 gives a brief background on the relative PIM-Architectures, whereas Section 4 explains the proposed PIM Virtual Plattform. Chapter 5 and 6 show experimental simulation setup and the results, which are compared them with already published results from PIM vendors. The paper is concluded in Section 7.
The paper is structured as follows. Section 2 Shows the related work in the area of PIM-Simulation. Section 3 gives a brief background on the relative PIM-Architectures, whereas Section 4 explains the proposed PIM Virtual Platform. Chapter 5 and 6 show experimental simulation setup and the results, which are compared them with already published results from PIM vendors. The paper is concluded in Section 7.
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\section{Related Work}
Several virtual prototypes of \ac{pim} architectures have been object to research in the past.
The authors of \cite{singh2019} used Ramulator-PIM, which is based on the ZSim \cite{sanchez2013} x86 simulator and the \ac{dram} simulator Ramulator \cite{kim2016a}, to build a high-level performance and energy estimation framework.
The investigated workloads achieved an \ac{edp} reduction up to \qty{5.1}{\times} for offloading parts of the execution to \ac{pim} units.
Similarly, the authors of \cite{corda2021} leveraged Ramulator-PIM to achieve an \ac{edp} reduction between \qtyrange{0.6}{110}{\times} for different workloads.
Y. Chao et al. \cite{yu2021} introduced MultiPIM, a high-level \ac{pim} simulator capable of simulating multiple memory stacks in a memory network and parallel \ac{pim} cores.
C. Yu et al. \cite{yu2021} introduced MultiPIM, a high-level \ac{pim} simulator capable of simulating multiple memory stacks in a memory network and parallel \ac{pim} cores.
Also based on Ramulator and ZSim, MultiPIM achieved a performance speedup for \ac{pim} in the range of \qtyrange{7.7}{15.1}{\times} for an ideal memory network topology.
However, all these approaches operate at a high level and assume general-purpose \ac{pim} processors rather than focusing on a specific \ac{pim} architecture.