diff --git a/acronyms.tex b/acronyms.tex index ff19b35..c20effd 100644 --- a/acronyms.tex +++ b/acronyms.tex @@ -107,3 +107,19 @@ short = WR, long = write, } +\DeclareAcronym{risc}{ + short = RISC, + long = reduced instruction set computer, +} +\DeclareAcronym{ld}{ + short = LD, + long = load, +} +\DeclareAcronym{st}{ + short = ST, + long = store, +} +\DeclareAcronym{aam}{ + short = AAM, + long = address aligned mode, +} diff --git a/references.bib b/references.bib index 24d7363..96c4203 100644 --- a/references.bib +++ b/references.bib @@ -20,7 +20,7 @@ urldate = {2024-01-09}, isbn = {978-1-72817-383-2}, keywords = {reviewed}, - file = {C:\Users\christ\Nextcloud2\Verschiedenes\Zotero\storage\7M7QNRVN\He et al. - 2020 - Newton A DRAM-maker’s Accelerator-in-Memory (AiM).pdf} + file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/7M7QNRVN/He et al. - 2020 - Newton A DRAM-maker’s Accelerator-in-Memory (AiM).pdf} } @inproceedings{kang2022, @@ -38,7 +38,7 @@ isbn = {978-1-4503-9149-8}, langid = {english}, keywords = {reviewed}, - file = {C:\Users\christ\Nextcloud2\Verschiedenes\Zotero\storage\YPD3XGJ6\Kang et al. - 2022 - An FPGA-based RNN-T Inference Accelerator with PIM.pdf} + file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/YPD3XGJ6/Kang et al. - 2022 - An FPGA-based RNN-T Inference Accelerator with PIM.pdf} } @inproceedings{kwon2021, @@ -55,7 +55,7 @@ isbn = {978-1-72819-549-0}, langid = {english}, keywords = {reviewed}, - file = {C:\Users\christ\Nextcloud2\Verschiedenes\Zotero\storage\UMUTRR6K\Kwon et al. - 2021 - 25.4 A 20nm 6GB Function-In-Memory DRAM, Based on .pdf} + file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/UMUTRR6K/Kwon et al. - 2021 - 25.4 A 20nm 6GB Function-In-Memory DRAM, Based on .pdf} } @inproceedings{lee2021, @@ -74,7 +74,25 @@ isbn = {978-1-66543-333-4}, langid = {english}, keywords = {reviewed}, - file = {C:\Users\christ\Nextcloud2\Verschiedenes\Zotero\storage\YWUR6TWQ\Lee et al. - 2021 - Hardware Architecture and Software Stack for PIM B.pdf} + file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/YWUR6TWQ/Lee et al. - 2021 - Hardware Architecture and Software Stack for PIM B.pdf} +} + +@article{steiner2022a, + title = {{{DRAMSys4}}.0: {{An Open-Source Simulation Framework}} for {{In-depth DRAM Analyses}}}, + shorttitle = {{{DRAMSys4}}.0}, + author = {Steiner, Lukas and Jung, Matthias and Prado, Felipe S. and Bykov, Kirill and Wehn, Norbert}, + year = {2022}, + month = apr, + journal = {International Journal of Parallel Programming}, + volume = {50}, + number = {2}, + pages = {217--242}, + issn = {0885-7458, 1573-7640}, + doi = {10.1007/s10766-022-00727-4}, + urldate = {2024-01-08}, + abstract = {Abstract The simulation of Dynamic Random Access Memories (DRAMs) on system level requires highly accurate models due to their complex timing and power behavior. However, conventional cycle-accurate DRAM subsystem models often become a bottleneck for the overall simulation speed. A promising alternative are simulators based on Transaction Level Modeling, which can be fast and accurate at the same time. In this paper we present DRAMSys4.0, which is, to the best of our knowledge, the fastest and most extensive open-source cycle-accurate DRAM simulation framework. DRAMSys4.0 includes a novel software architecture that enables a fast adaption to different hardware controller implementations and new JEDEC standards. In addition, it already supports the latest standards DDR5 and LPDDR5. We explain how to apply optimization techniques for an increased simulation speed while maintaining full temporal accuracy. Furthermore, we demonstrate the simulator's accuracy and analysis tools with two application examples. Finally, we provide a detailed investigation and comparison of the most prominent cycle-accurate open-source DRAM simulators with regard to their supported features, analysis capabilities and simulation speed.}, + langid = {english}, + file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/SPK4JAZI/Steiner et al. - 2022 - DRAMSys4.0 An Open-Source Simulation Framework fo.pdf} } @incollection{sudarshan2022, @@ -91,5 +109,5 @@ urldate = {2024-01-21}, isbn = {978-3-031-15073-9 978-3-031-15074-6}, langid = {english}, - file = {C:\Users\christ\Nextcloud2\Verschiedenes\Zotero\storage\73HULZKB\Sudarshan et al. - 2022 - A Critical Assessment of DRAM-PIM Architectures - .pdf} + file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/73HULZKB/Sudarshan et al. - 2022 - A Critical Assessment of DRAM-PIM Architectures - .pdf} } diff --git a/samplepaper.tex b/samplepaper.tex index 53a70c1..05224f1 100644 --- a/samplepaper.tex +++ b/samplepaper.tex @@ -4,10 +4,14 @@ % \documentclass[runningheads]{llncs} % -\usepackage{graphicx} \usepackage{siunitx} \usepackage[nameinlink,capitalize,noabbrev]{cleveref} \usepackage{acro} +\usepackage[usenames,dvipsnames]{xcolor} +\usepackage{tikz} +\usepackage{mathdots} + +\usepackage{graphicx} % Used for displaying a sample figure. If possible, figure files should % be included in EPS format. % @@ -16,6 +20,15 @@ % \renewcommand\UrlFont{\color{blue}\rmfamily} \sisetup{per-mode = symbol} + +\usetikzlibrary{positioning} + +\definecolor{_darkblue}{RGB}{68, 114, 196} +\definecolor{_blue}{RGB}{91, 155, 213} +\definecolor{_green}{RGB}{112, 173, 71} +\definecolor{_orange}{RGB}{237, 125, 49} +\definecolor{_yellow}{RGB}{255, 192, 0} + \input{acronyms} \begin{document} @@ -70,6 +83,7 @@ Onur Ramulator Samsung DRAMSim2 % TODO Derek/Lukas \section{Background DRAM-PIM} +\label{sec:dram_pim} % TODO Derek Many types of \acp{dnn} used for language and speech processing, such as \acp{rnn}, \acp{mlp} and some layers of \acp{cnn}, are severely limited by the memory bandwidth that the DRAM can provide, making them \textit{memory-bound} \cite{he2020}. As already discussed in \cref{sec:intro}, PIM is a good fit for accelerating memory-bound workloads with low operational intensity. @@ -110,9 +124,72 @@ In this mode, a single memory access initiates the concurrent execution of the n In addition, the I/O circuits of the \ac{dram} are completely disabled in this mode, reducing the power required during \ac{pim} operation. Both in \ac{ab} mode and in \ac{abp} mode, the total \aca{hbm2} bandwidth per \ac{pch} of $\qty{16}{\giga\byte\per\second}$ is $\qty{8}{\times}$ higher with $\qty{128}{\giga\byte\per\second}$ or in total $\qty{2}{\tera\byte\per\second}$ for 16 \acp{pch}. +Due to the focus on \ac{dnn} applications in \aca{fimdram}, the native data type for the \acp{fpu} is \ac{fp16}, which is motivated by the significantly lower area and power requirements for \acp{fpu} compared to 32-bit \ac{fp} numbers. +The \ac{simd} \acp{fpu} of the processing units is implemented once as a \ac{fp16} multiplier unit, and once as a \ac{fp16} adder unit, providing support for these basic algorithmic operations. +In addition to the \acp{fpu}, a processing unit consists also of \acp{crf}, \acp{srf} and \acp{grf}. +The \ac{crf} acts as an instruction buffer, holding the 32 32-bit instructions to be executed by the processor when performing a memory access. +One program that is stored in the \ac{crf} is called a \textit{microkernel}. +Each \ac{grf} consists of 16 registers, each with the \aca{hbm2} prefetch size of 256 bits, where each entry can hold the data of a full memory burst. +The \ac{grf} of a processing unit is divided into two halves (\ac{grf}-A and \ac{grf}-B), with 8 register entries allocated to each of the two banks. +Finally, in the \acp{srf}, a 16-bit scalar value is replicated 16 times as it is fed into the 16-wide \ac{simd} \ac{fpu} as a constant summand or factor for an addition or multiplication. +It is also divided into two halves (\ac{srf}-A and \ac{srf}-M) for addition and multiplication with 8 entries each. +The \aca{fimdram} instruction set provides a total of 9 32-bit \ac{risc} instructions, each of which falls into one of three groups: control flow instructions (NOP, JUMP, EXIT), arithmetic instructions (ADD, MUL, MAC, MAD) and data movement instructions (MOV, FILL). + +Since the execution of an instruction in the microkernel is initiated by a memory access, the host processor must execute \ac{ld} or \ac{st} store instructions in a sequence that perfectly matches the loaded \ac{pim} microkernel. +When an instruction executes directly on data that is provided by a memory bank, the addresses of these memory accesses specify the exact row and column where the data should be loaded from or stored to. +This means that the order of the respective memory accesses for such instructions is important and must not be reordered by the processor or memory controller, as it must match the corresponding instruction in the microkernel. +One solution to this problem would be to introduce memory barriers between each \ac{ld} and \ac{st} instruction of the processor, to prevent any reordering, however this comes at a significant performance cost and results in memory bandwidth being underutilized. +To solve this overhead, Samsung has introduced the \ac{aam} mode for arithmetic instructions. +In the \ac{aam} mode, the register indices of an instruction are ignored and decoded from the column and row address of the memory access itself. +With this method, the register indices and the bank address cannot get out of sync, as they are tightly coupled, even if the memory controller reorders the order of the accesses. + \section{VP} % TODO Derek +To build a virtual prototype of \aca{fimdram}, an accurate \ac{hbm2} model is needed, where the additional \ac{pim}-\acp{pu} are integrated. +For this the cycle-accurate \ac{dram} simulator DRAMSys \cite{steiner2022a} has been used and its \ac{hbm2} model extended to incorporate the \acp{pu} into the \acp{pch} of the \ac{pim}-activated channels. +The \aca{fimdram} model itself does not need to model any timing behavior: +Its submodel is essentially untimed, since it is already synchronized with the operation of the \ac{dram} model of DRAMSys. + +While \aca{fimdram} operates in the default \ac{sb} mode, it behaves exactly like a normal \aca{hbm2} memory. +Only when the host initiates a mode switch of one of the \ac{pim}-enabled \acp{pch}, the processing units become active. +When entering \ac{ab} mode, the \ac{dram} model ignores the specific bank address of incoming \ac{wr} commands and internally performs the write operation for either all even or all odd banks of the \ac{pch}, depending on the parity of the original bank index. +After the transition to the \ac{ab} mode, the \ac{dram} can further transition to the \ac{abp} mode, which allows the execution of instructions in the processing units. +The \ac{abp} mode is similar to the \ac{ab} mode in that it also ignores the concrete bank address except for its parity, while additionally passing the column and row address and, in the case of a read, also the respective fetched bank data to the processing units. +In the case of a write access, the output of the processing unit is written directly into the corresponding bank, ignoring the actual data of the transaction object coming from the host processor. +This is equivalent to the real \aca{fimdram} implementation, where the global I/O bus of the memory is not actually driven, and all data movement is done internally in the banks. + +The model's internal state of a processing unit consists of the \ac{grf} register files \ac{grf}-A and \ac{grf}-B, the \ac{srf} register files \ac{srf}-A and \ac{srf}-M, the program counter, and a jump counter that keeps track of the current iteration of a JUMP instruction. +Depending on a \ac{rd} or \ac{wr} command received from the \ac{dram} model, the control flow is dispatched into one of two functions that execute an instruction in the \ac{crf} and increment the program counter of the corresponding \ac{pim} unit. +Both functions calculate the register indices used by the \ac{aam} execution mode followed by a branch table that dispatches to the handler of the current instruction. +In case of the data movement instructions MOV and FILL, a simple move operation that loads to value of one register or the bank data and assigns it to the destination register is performed. +The arithmetic instructions fetch the operand data is from their respective sources and perform the operation, and write back the result by modifying the internal state of the \ac{pu}. +Note that while the MAC instruction can iteratively add to the same destination register, but it does not reduce the 16-wide \ac{fp16} vector itself in any way. +Instead it is the host processor's responsibility of reducing these 16 floating point numbers into one \ac{fp16} number. + +With this implementation of the processing units, it is now possible to write a user program that controls the execution of the \ac{pim}-\acp{pu} directly in the \ac{hbm2} model. +% TODO software library... + +The use of \ac{aam} requires a special memory layout so that the register indices are correctly calculated from the column and row addresses of a memory access. +The memory layout of a weight matrix used for e.g., a \ac{gemv} operation is illustrated in \cref{img:matrix_layout}. +\begin{figure} + \centering + \resizebox{0.8\linewidth}{!}{\input{images/matrix_layout}} + \caption{Mapping of the weight matrix onto the memory banks.} + \label{img:matrix_layout} +\end{figure} +To make use of all eight \ac{grf}-A registers, the input address has to increment linearly, while adhering a column-major matrix layout. +In a column-major matrix layout, the entries of a column are stored sequentially before switching to the next column, according to the \texttt{MATRIX[R][C]} C-like array notation. +However, the concrete element type of the array is not a single \ac{fp16} element, but a vector of 16 \acp{fp16} packed together. +This results in 16 \ac{fp16} matrix row elements being stored sequentially before switching to the next 16 \ac{fp16} elements in the next row of the same 16 columns, ensuring that a \ac{simd} processing unit always contains the data of only one matrix row. + +To guarantee the correct placement of the first matrix element at the boundary of the first bank of the \ac{pch}, an alignment for the matrix data structure of $\qty{512}{\byte}$ would need to be explicitly enforced. +However, when using the \ac{aam} execution mode, this is not sufficient. +As already mentioned in \cref{sec:dram_pim}, the \ac{grf}-A and \ac{grf}-B indices are calculated from the column and row address of the triggering memory access. +With an alignment of $\qty{512}{\byte}$, no assumptions can be made about the initial value of the \ac{grf}-A and \ac{grf}-B indices, while for the execution of a complete \ac{gemv} kernel, both indices should start with zero. +Therefore, the larger alignment requirement of $2^6 \cdot \qty{512}{\byte} = \qty{32768}{\byte}$ must be ensured for the weight matrix. + + \section{Results} % TODO Derek \section{Conclusion}