Use gem5 ops ISA method instead of ADDR method

pim-os/src/lib.rs

@@ -6,7 +6,7 @@ use core::sync::atomic::{compiler_fence, Ordering};
 mod alloc;
 pub mod boot;
 pub mod critical_section;
-pub mod m5ops;
+pub mod m5op;
 mod panic;
 pub mod pim;
 pub mod uart;
@@ -21,7 +21,8 @@ pub extern "C" fn entry() -> ! {
 
     unsafe { main() }
 
-    m5ops::exit();
+    m5op::exit();
+
     loop {
         compiler_fence(Ordering::SeqCst);
     }

pim-os/src/m5op.rs

@@ -0,0 +1,85 @@
+use aarch64_cpu::asm::barrier;
+use core::arch::global_asm;
+
+global_asm!(include_str!("m5op.s"));
+
+extern "C" {
+    fn m5_exit();
+    fn m5_reset_stats();
+    fn m5_dump_stats();
+    fn m5_dump_reset_stats();
+}
+
+pub fn exit() {
+    unsafe { m5_exit() }
+}
+
+pub fn reset_stats() {
+    unsafe { m5_reset_stats() }
+}
+
+pub fn dump_stats() {
+    unsafe { m5_dump_stats() }
+}
+
+pub fn dump_reset_stats() {
+    unsafe { m5_dump_reset_stats() }
+}
+
+// const M5OPS_ADDR: u64 = 0x10010000;
+
+// const EXIT_ADDR: *const u64 = (M5OPS_ADDR + (0x21 << 8)) as _;
+// const DUMP_STATS_ADDR: *const u64 = (M5OPS_ADDR + (0x40 << 8)) as _;
+// const RESET_STATS_ADDR: *const u64 = (M5OPS_ADDR + (0x41 << 8)) as _;
+// const DUMP_RESET_STATS_ADDR: *const u64 = (M5OPS_ADDR + (0x42 << 8)) as _;
+// const WORK_BEGIN_ADDR: *const u64 = (M5OPS_ADDR + (0x5A << 8)) as _;
+// const WORK_END_ADDR: *const u64 = (M5OPS_ADDR + (0x5B << 8)) as _;
+// // const CHECKPOINT_ADDR: *const u64 = (M5OPS_ADDR + (0x43 << 8)) as _;
+
+// pub fn exit() {
+//     unsafe {
+//         core::ptr::read_volatile(EXIT_ADDR);
+//     }
+
+//     barrier::dsb(barrier::SY);
+// }
+
+// pub fn dump_stats() {
+//     unsafe {
+//         core::ptr::read_volatile(DUMP_STATS_ADDR);
+//     }
+
+//     barrier::dsb(barrier::SY);
+// }
+
+// pub fn reset_stats() {
+//     unsafe {
+//         core::ptr::read_volatile(RESET_STATS_ADDR);
+//     }
+
+//     barrier::dsb(barrier::SY);
+// }
+
+// pub fn dump_reset_stats() {
+//     unsafe {
+//         core::ptr::read_volatile(DUMP_RESET_STATS_ADDR);
+//     }
+
+//     barrier::dsb(barrier::SY);
+// }
+
+// pub fn work_begin() {
+//     unsafe {
+//         core::ptr::read_volatile(WORK_BEGIN_ADDR);
+//     }
+
+//     barrier::dsb(barrier::SY);
+// }
+
+// pub fn work_end() {
+//     unsafe {
+//         core::ptr::read_volatile(WORK_END_ADDR);
+//     }
+
+//     barrier::dsb(barrier::SY);
+// }

pim-os/src/m5op.s

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2010-2013, 2016-2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+.macro	m5op_func, name, func
+        .globl \name
+        \name:
+        .long 0xff000110 | (\func << 16)
+        ret
+.endm
+
+.text
+m5op_func m5_exit, 0x21;
+m5op_func m5_reset_stats, 0x40;
+m5op_func m5_dump_stats, 0x41;
+m5op_func m5_dump_reset_stats, 0x42;

pim-os/src/m5ops.rs

@@ -1,16 +0,0 @@
-use core::arch::asm;
-
-const M5OPS_ADDR: u64 = 0x10010000;
-
-const EXIT_ADDR: *const u64 = (M5OPS_ADDR + (0x21 << 8)) as _;
-// const DUMP_STATS_ADDR: *const u64 = (M5OPS_ADDR + (0x40 << 8)) as _;
-// const RESET_STATS_ADDR: *const u64 = (M5OPS_ADDR + (0x41 << 8)) as _;
-// const DUMP_RESET_STATS_ADDR: *const u64 = (M5OPS_ADDR + (0x42 << 8)) as _;
-// const CHECKPOINT_ADDR: *const u64 = (M5OPS_ADDR + (0x43 << 8)) as _;
-
-pub fn exit() {
-    unsafe {
-        core::ptr::read_volatile(EXIT_ADDR);
-        asm!("dsb sy");
-    }
-}

pim-os/src/main.rs

@@ -10,6 +10,7 @@ use half::f16;
 use nalgebra::Matrix;
 use pim_isa::BankMode;
 use pim_os::{
+    m5op,
     pim::{
         self,
         array::{DummyArray, PimMatrixArena, PimStorage, NUMBER_OF_BANKS},
@@ -65,12 +66,18 @@ pub extern "C" fn main() {
 
         pim::state::set_bank_mode(BankMode::PimAllBank);
 
-        matrix_matrix_mul::execute(
+        m5op::reset_stats();
-            pim_matrix_arena0,
+
-            pim_matrix_arena1,
+        for _ in 0..100 {
-            pim_matrix_arena2,
+            matrix_matrix_mul::execute(
-            dummy_array.as_ref(),
+                pim_matrix_arena0,
-        );
+                pim_matrix_arena1,
+                pim_matrix_arena2,
+                dummy_array.as_ref(),
+            );
+        }
+
+        m5op::dump_stats();
 
         pim::state::set_bank_mode(BankMode::SingleBank);
     }

pim-os/src/pim/array.rs

@@ -105,6 +105,10 @@ pub trait PimRegion {
         barrier::dsb(barrier::SY);
     }
 
+    fn execute_instruction_read_single_bank_unsynchronized(&self, i: usize) {
+        self.read_data_bank(EVEN_BANK_INDEX + i * NUMBER_OF_BANKS);
+    }
+
     fn execute_instruction_read_dual_bank(&self) {
         let i = 0;
         if !cfg!(feature = "cacheless") {

pim-os/src/pim/kernel/matrix_matrix_mul.rs

@@ -138,8 +138,9 @@ pub fn execute(
 
         for column in 0..MATRIX_DIMENSION {
             for i in 0..MATRIX_DIMENSION {
-                pim_matrix_arena1
+                pim_matrix_arena1.execute_instruction_read_single_bank_unsynchronized(
-                    .execute_instruction_read_single_bank(column * MATRIX_DIMENSION + i);
+                    column * MATRIX_DIMENSION + i,
+                );
             }
         }