Implement ADD and JUMP instructions

pim-os/src/main.rs

@@ -5,10 +5,15 @@ use core::{
     arch::global_asm,
     fmt::Write,
     panic::PanicInfo,
-    sync::atomic::{self, Ordering},
+    sync::atomic::{compiler_fence, Ordering},
 };
-use pim::{array::ComputeArray, kernel::TEST_KERNEL};
-use pim_isa::{BankMode, PimConfig};
+use half::f16;
+use pim::{
+    array::{BankArray, ComputeArray},
+    kernel::TEST_KERNEL,
+    state::PimState,
+};
+use pim_isa::BankMode;
 use uart::Uart0;
 
 mod m5ops;
@@ -19,61 +24,46 @@ global_asm!(include_str!("start.s"));
 
 #[no_mangle]
 pub extern "C" fn entry() -> ! {
-    let mut pim_config = PimConfig {
-        bank_mode: BankMode::PimAllBank,
-        kernel: TEST_KERNEL,
-    };
-    let mut pim_writer = pim::config::PimWriter;
-
-    let mut test_array: ComputeArray<2> = ComputeArray::default();
-
-    let mut uart = Uart0 {};
+    let mut pim_state = PimState::new(&TEST_KERNEL);
+    let mut compute_array: ComputeArray<3> = ComputeArray([
+        BankArray([f16::from_f32(0.1); 512]),
+        BankArray([f16::from_f32(0.2); 512]),
+        BankArray([f16::ZERO; 512]),
+    ]);
+    let dummy_array = BankArray::default();
+    let mut uart = Uart0;
 
     writeln!(
         &mut uart,
         "PIM array is at {:x?}",
-        core::ptr::addr_of!(test_array)
+        core::ptr::addr_of!(compute_array)
     )
     .unwrap();
-    writeln!(&mut uart, "Read from all banks").unwrap();
 
     // Invalidate and flush array just in case
-    test_array.invalidate_flush();
+    compute_array.invalidate_flush();
+    dummy_array.invalidate_flush();
 
-    // Zero array to prevent fetch
-    let bank_array = &mut test_array.0[0];
-    bank_array.preload_zero();
+    pim_state.set_bank_mode(BankMode::PimAllBank);
+    compute_array.0[0].execute_instruction_read();
+    compute_array.0[1].execute_instruction_read();
+    compute_array.0[2].execute_instruction_write();
+    dummy_array.execute_instruction_read();
+    pim_state.set_bank_mode(BankMode::SingleBank);
 
-    pim_writer.write(
-        serde_json_core::to_string::<PimConfig, 1024>(&pim_config)
-            .unwrap()
-            .as_str(),
-    );
-
-    bank_array.write_data();
-
-    pim_config.bank_mode = BankMode::SingleBank;
-    pim_writer.write(
-        serde_json_core::to_string::<PimConfig, 1024>(&pim_config)
-            .unwrap()
-            .as_str(),
-    );
-
-    // Invalidate and flush
-    test_array.invalidate();
+    compute_array.invalidate();
 
     writeln!(
         &mut uart,
-        "{:?}: {:x?}",
-        core::ptr::addr_of!(test_array),
-        test_array
+        "BankArray 0: [{:?}, ...]\nBankArray 1: [{:?}, ...]\nBankArray 2: [{:?}, ...]",
+        compute_array.0[0].0[0], compute_array.0[1].0[0], compute_array.0[2].0[0]
     )
     .unwrap();
 
     m5ops::exit();
 
     loop {
-        atomic::compiler_fence(Ordering::SeqCst);
+        compiler_fence(Ordering::SeqCst);
     }
 }
 
@@ -82,6 +72,6 @@ fn panic(info: &PanicInfo) -> ! {
     writeln!(Uart0, "{info}").unwrap();
 
     loop {
-        atomic::compiler_fence(Ordering::SeqCst);
+        compiler_fence(Ordering::SeqCst);
     }
 }

pim-os/src/pim.rs

@@ -1,4 +1,4 @@
 pub mod array;
 pub mod config;
 pub mod kernel;
-pub mod operation;
+pub mod state;

pim-os/src/pim/array.rs

@@ -16,13 +16,9 @@ impl Default for BankArray {
 }
 
 impl BankArray {
-    pub fn write_data(&mut self) {
-        unsafe {
-            // Write to first bank
-            let first_bank = &mut self.0[0];
-            core::ptr::write_volatile(first_bank, f16::ZERO);
-            self.invalidate_flush_single_bank(0);
-        }
+    pub fn execute_instruction_read(&self) {
+        self.invalidate_single_bank(0);
+        self.read_data();
     }
 
     pub fn read_data(&self) {
@@ -30,7 +26,20 @@ impl BankArray {
             // Read from first bank
             let first_bank = &self.0[0];
             core::ptr::read_volatile(first_bank);
-            self.invalidate_flush_single_bank(0);
+        }
+    }
+
+    pub fn execute_instruction_write(&mut self) {
+        self.preload_zero();
+        self.write_data();
+        self.invalidate_flush_single_bank(0);
+    }
+
+    pub fn write_data(&mut self) {
+        unsafe {
+            // Write to first bank
+            let first_bank = &mut self.0[0];
+            core::ptr::write_volatile(first_bank, f16::ZERO);
         }
     }
 
@@ -90,12 +99,6 @@ impl<const N: usize> ComputeArray<N> {
     pub fn invalidate(&self) {
         self.0.iter().for_each(|bank_array| bank_array.invalidate());
     }
-
-    pub fn preload_zero(&self) {
-        self.0
-            .iter()
-            .for_each(|bank_array| bank_array.preload_zero());
-    }
 }
 
 impl<const N: usize> Default for ComputeArray<N> {

pim-os/src/pim/config.rs

@@ -1,11 +1,11 @@
 use core::arch::asm;
 
-
 #[link_section = ".pim_config"]
 static mut PIM_CONFIG_REGION: [u8; 0x4000] = [0; 0x4000];
 
 const CACHE_LINE_SIZE: usize = 32;
 
+#[derive(Debug)]
 pub struct PimWriter;
 
 impl PimWriter {

pim-os/src/pim/kernel.rs

@@ -1,25 +1,23 @@
 use pim_isa::{File, Instruction, Kernel};
 
 pub const TEST_KERNEL: Kernel = Kernel([
-    Instruction::FILL {
-        src: File::Grf { index: 0 },
-        dst: File::Bank,
-    },
     Instruction::MOV {
         src: File::Bank,
-        dst: File::Grf { index: 1 },
+        dst: File::Grf { index: 0 },
     },
-    Instruction::JUMP {
-        offset: 1,
-        count: 12,
+    Instruction::ADD {
+        src0: File::Bank,
+        src1: File::Grf { index: 0 },
+        dst: File::Grf { index: 0 },
     },
+    Instruction::FILL { src: File::Grf { index: 0 }, dst: File::Bank },
     Instruction::EXIT,
     Instruction::NOP,
-    Instruction::EXIT,
     Instruction::NOP,
-    Instruction::EXIT,
     Instruction::NOP,
-    Instruction::EXIT,
+    Instruction::NOP,
+    Instruction::NOP,
+    Instruction::NOP,
     Instruction::NOP,
     Instruction::NOP,
     Instruction::NOP,

pim-os/src/pim/operation.rs

@@ -1,18 +0,0 @@
-use super::array::BankArray;
-use core::arch::asm;
-
-fn execute_bank_write(bank_array: &BankArray) {
-    unsafe {
-        // Invalidate and flush cache line
-        asm!("dc civac, {val}", val = in(reg) bank_array);
-        asm!("dsb sy");
-
-        // Zero cache line
-        asm!("dc zva, {val}", val = in(reg) bank_array);
-        asm!("dsb sy");
-    }
-}
-
-fn execute_bank_read() {}
-
-fn execute_generic_inst() {}

pim-os/src/pim/state.rs

@@ -0,0 +1,32 @@
+use super::config::PimWriter;
+use pim_isa::{BankMode, Kernel, PimConfig};
+
+#[derive(Debug)]
+pub struct PimState {
+    kernel: Kernel,
+    bank_mode: BankMode,
+    writer: PimWriter,
+}
+
+impl PimState {
+    pub fn new(kernel: &Kernel) -> Self {
+        Self {
+            kernel: kernel.clone(),
+            bank_mode: BankMode::SingleBank,
+            writer: PimWriter,
+        }
+    }
+
+    // TODO return token and return to singlebank when dropped
+    pub fn set_bank_mode(&mut self, bank_mode: BankMode) {
+        self.bank_mode = bank_mode;
+        self.writer.write(
+            serde_json_core::to_string::<PimConfig, 1024>(&PimConfig {
+                kernel: self.kernel.clone(),
+                bank_mode: self.bank_mode,
+            })
+            .unwrap()
+            .as_str(),
+        );
+    }
+}

pim-os/src/uart.rs

@@ -2,6 +2,7 @@ use core::{fmt::Write, ptr::write_volatile};
 
 const UART0_ADDR: *mut u32 = 0x1c090000 as _;
 
+#[derive(Debug)]
 pub struct Uart0;
 
 impl Write for Uart0 {