Add support for cacheless PIM

pim-os/src/main.rs

@@ -1,8 +1,8 @@
 #![no_std]
 #![no_main]
 
+use aarch64_cpu::asm::barrier;
 use core::{
-    arch::global_asm,
     fmt::Write,
     panic::PanicInfo,
     sync::atomic::{compiler_fence, Ordering},
@@ -15,13 +15,11 @@ use pim::{
 };
 use pim_isa::BankMode;
 use uart::Uart0;
-
+mod boot;
 mod m5ops;
 mod pim;
 mod uart;
 
-global_asm!(include_str!("start.s"));
-
 #[no_mangle]
 pub extern "C" fn entry() -> ! {
     let mut pim_state = PimState::new(&TEST_KERNEL);
@@ -52,6 +50,7 @@ pub extern "C" fn entry() -> ! {
     // Invalidate and flush array just in case
     compute_array.invalidate_flush();
     dummy_array.invalidate_flush();
+    barrier::dsb(barrier::SY);
 
     pim_state.set_bank_mode(BankMode::PimAllBank);
     compute_array.0[0].execute_instruction_read();
@@ -62,6 +61,7 @@ pub extern "C" fn entry() -> ! {
     pim_state.set_bank_mode(BankMode::SingleBank);
 
     compute_array.invalidate();
+    barrier::dsb(barrier::SY);
 
     writeln!(
         &mut uart,