Simple hello world

.cargo/config

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+[build]
+target = "aarch64-unknown-none"
+
+rustflags = [
+    "-C", "link-arg=-Taarch64-gem5.ld",
+]

.gitignore

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+/target

Cargo.toml

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+[package]
+name = "aarch64"
+version = "0.1.0"
+edition = "2021"
+
+[dependencies]
+aarch64-cpu = "9.4.0"
+half = { version = "2.3.1", default-features = false }
+
+[profile.dev]
+panic = "abort"
+
+[profile.release]
+panic = "abort"

aarch64-gem5.ld

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+ENTRY(_start)
+SECTIONS
+{
+    . = 0x80000000;
+    .text.boot : { *(.text.boot) }
+    .text : { *(.text) }
+    .data : { *(.data) }
+    .rodata : { *(.rodata) }
+    .bss : { *(.bss) }
+
+    . = ALIGN(8);
+    . = . + 0x8000;
+    LD_STACK_PTR = .;
+}

src/main.rs

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+#![no_std]
+#![no_main]
+
+use crate::uart::Uart0;
+use core::sync::atomic::{self, Ordering};
+use core::{arch::global_asm, fmt::Write, panic::PanicInfo};
+
+mod uart;
+
+global_asm!(include_str!("start.s"));
+
+#[no_mangle]
+pub extern "C" fn entry() -> ! {
+    let mut uart = Uart0 {};
+
+    for i in 0..3 {
+        writeln!(&mut uart, "Hello from Rust {i}!").unwrap();
+    }
+
+    loop {
+        atomic::compiler_fence(Ordering::SeqCst);
+    }
+}
+
+#[panic_handler]
+fn panic(info: &PanicInfo) -> ! {
+    writeln!(Uart0, "{info}").unwrap();
+
+    loop {
+        atomic::compiler_fence(Ordering::SeqCst);
+    }
+}

src/start.s

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+.globl _start
+.extern LD_STACK_PTR
+
+.section ".text.boot"
+
+_start:
+    ldr     x30, =LD_STACK_PTR
+    mov     sp, x30
+    bl      entry
+
+.equ PSCI_SYSTEM_OFF, 0x84000008
+.globl system_off
+system_off:
+    ldr     x0, =PSCI_SYSTEM_OFF
+    hvc     #0

src/uart.rs

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+use core::{fmt::Write, ptr::write_volatile};
+
+const UART0_ADDR: *mut u32 = 0x1c090000 as _;
+
+pub struct Uart0;
+
+impl Write for Uart0 {
+    fn write_str(&mut self, s: &str) -> core::fmt::Result {
+        for &byte in s.as_bytes() {
+            unsafe {
+                write_volatile(UART0_ADDR, byte as _);
+            }
+        }
+        Ok(())
+    }
+}