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Add conveniance functions for a PIM array

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This commit is contained in:
Derek Christ
2023-12-01 18:00:28 +01:00
parent 54bf6bda11
commit 2547f7030d
6 changed files with 160 additions and 63 deletions
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94
pim-os/src/main.rs
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@@ -2,13 +2,12 @@
#![no_main]
use core::{
arch::{asm, global_asm},
arch::global_asm,
fmt::Write,
panic::PanicInfo,
sync::atomic::{self, Ordering},
};
use half::f16;
use pim::{array::BankArray, kernel::TEST_KERNEL};
use pim::{array::ComputeArray, kernel::TEST_KERNEL};
use pim_isa::{BankMode, PimConfig};
use uart::Uart0;
@@ -18,8 +17,6 @@ mod uart;
global_asm!(include_str!("start.s"));
static mut TEST_ARRAY: BankArray = BankArray([f16::ZERO; 512]);
#[no_mangle]
pub extern "C" fn entry() -> ! {
let mut pim_config = PimConfig {
@@ -28,67 +25,50 @@ pub extern "C" fn entry() -> ! {
};
let mut pim_writer = pim::config::PimWriter;
let mut test_array: ComputeArray<2> = ComputeArray::default();
let mut uart = Uart0 {};
unsafe {
writeln!(
&mut uart,
"PIM array is at {:x?}",
core::ptr::addr_of!(TEST_ARRAY)
)
.unwrap();
writeln!(&mut uart, "Read from all banks").unwrap();
// Invalidate and flush array just in case
for element in TEST_ARRAY.0.iter().step_by(8) {
asm!("dc civac, {val}", val = in(reg) element);
}
asm!("dsb sy");
writeln!(
&mut uart,
"PIM array is at {:x?}",
core::ptr::addr_of!(test_array)
)
.unwrap();
writeln!(&mut uart, "Read from all banks").unwrap();
// Fetch single cache line in array
// core::ptr::read_volatile(&TEST_ARRAY.0[0]);
// Invalidate and flush array just in case
test_array.invalidate_flush();
// Zero array to prevent fetch
// for element in TEST_ARRAY.0.iter().step_by(8) {
// asm!("dc zva, {val}", val = in(reg) element);
// }
asm!("dc zva, {val}", val = in(reg) &TEST_ARRAY.0[0]);
asm!("dsb sy");
// Zero array to prevent fetch
let bank_array = &mut test_array.0[0];
bank_array.preload_zero();
pim_writer.write(
serde_json_core::to_string::<PimConfig, 1024>(&pim_config)
.unwrap()
.as_str(),
);
pim_writer.write(
serde_json_core::to_string::<PimConfig, 1024>(&pim_config)
.unwrap()
.as_str(),
);
core::ptr::write_volatile(&mut TEST_ARRAY.0[0], f16::ZERO);
bank_array.write_data();
// Invalidate and flush
// for element in TEST_ARRAY.0.iter().step_by(8) {
asm!("dc civac, {val}", val = in(reg) &TEST_ARRAY.0[0]);
// }
asm!("dsb sy");
pim_config.bank_mode = BankMode::SingleBank;
pim_writer.write(
serde_json_core::to_string::<PimConfig, 1024>(&pim_config)
.unwrap()
.as_str(),
);
pim_config.bank_mode = BankMode::SingleBank;
pim_writer.write(
serde_json_core::to_string::<PimConfig, 1024>(&pim_config)
.unwrap()
.as_str(),
);
// Invalidate and flush
test_array.invalidate();
// Invalidate array
for element in TEST_ARRAY.0.iter().step_by(8) {
asm!("dc ivac, {val}", val = in(reg) element);
}
writeln!(
&mut uart,
"{:?}: {:x?}",
core::ptr::addr_of!(TEST_ARRAY),
TEST_ARRAY
)
.unwrap();
}
writeln!(
&mut uart,
"{:?}: {:x?}",
core::ptr::addr_of!(test_array),
test_array
)
.unwrap();
m5ops::exit();