391 lines
12 KiB
TeX
391 lines
12 KiB
TeX
\documentclass[aspectratio=169]{beamer}
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\usetheme{UniWue}
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\usepackage[style=verbose-ibid]{biblatex}
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\usepackage{datetime}
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\usepackage{tabularray}
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\usepackage[inkscapeversion=1]{svg}
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\addbibresource{references.bib}
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\setbeamerfont{footnote}{size=\tiny}
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\newdate{presentationday}{01}{10}{2024}
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\title{PIMSys}
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\subtitle{A Virtual Prototype for Processing in Memory}
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\author{
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Derek~Christ\inst{1}
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\and
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Lukas~Steiner\inst{2}
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\and
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Matthias~Jung\inst{3}
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\and
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Norbert~Wehn\inst{2}
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}
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\institute{
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\inst{1}
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Fraunhofer IESE
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\quad
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\inst{2}
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RPTU Kaiserslautern-Landau
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\quad
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\inst{3}
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University of Würzburg
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}
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\date{MEMSYS~2024}
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\begin{document}
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\frame{\titlepage}
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\section{Introduction}
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\begin{frame}{Energy Demand of Applications}
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Total compute energy approaches world’s energy production\autocite{src2021}
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\begin{figure}
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\includesvg[width=0.6\textwidth]{images/world_energy}
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\end{figure}
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\end{frame}
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\begin{frame}{Memory Bound Workloads}
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AI applications become increasingly memory-bound\autocite{ivobolsens2023}
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\begin{figure}
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\includesvg[width=0.5\textwidth]{images/gpt}
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\end{figure}
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\end{frame}
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\section{Processing-in-Memory}
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\begin{frame}{Workloads for PIM}
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Fully connected neural network layers:
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\begin{itemize}
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\item Large weight matrix - does not fit onto cache
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\item No data reuse - cache is useless
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\end{itemize}
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\begin{figure}
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\includesvg[width=0.6\textwidth]{images/dnn}
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\end{figure}
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\end{frame}
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\begin{frame}{Workloads for PIM}
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Convolutional layers:
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\begin{itemize}
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\item Small filter matrix - does fit onto cache
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\item Excessive data reuse - cache is useful
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\end{itemize}
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\begin{figure}
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TODO Tikz Image
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% \includesvg[width=0.6\textwidth]{images/dnn}
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\end{figure}
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\end{frame}
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\begin{frame}{Workloads for PIM}
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\begin{columns}[T]
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\begin{column}{0.5\textwidth}
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\begin{center} \includesvg[height=50px]{images/thumbs-up} \end{center}
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\begin{itemize}
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\item Fully connected layers in multilayer perceptrons (MLPs)
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\item Layers in recurrent neural networks (RNNs)
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\end{itemize}
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\end{column}
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\begin{column}{0.5\textwidth}
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\begin{center} \includesvg[height=50px]{images/thumbs-unsure} \end{center}
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\begin{itemize}
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\item Convolutional neural network (CNNs)
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\end{itemize}
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\end{column}
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\end{columns}
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\end{frame}
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\begin{frame}{PIM Architectures}
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\begin{columns}[T]
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\begin{column}{0.4\textwidth}
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\begin{itemize}
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\item<2-> Inside the memory subarray
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\item<3-> Near the subarray in the PSA output region
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\item<4-> Near the bank in its peripheral region
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\item<5-> In the I/O region of the memory
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\end{itemize}
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\end{column}
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\begin{column}{0.6\textwidth}
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\only<1>{\includesvg[height=115px]{images/pim_positions_0}}
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\only<2>{\includesvg[height=115px]{images/pim_positions_1}}
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\only<3>{\includesvg[height=115px]{images/pim_positions_2}}
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\only<4>{\includesvg[height=115px]{images/pim_positions_3}}
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\only<5->{\includesvg[height=115px]{images/pim_positions_4}}
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\end{column}
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\end{columns}
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\visible<6>{\begin{block}{Remark}The nearer the computation is to the memory cells, the higher the achievable bandwidth!\end{block}}
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\end{frame}
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\section{Samsung HBM-PIM/FIMDRAM}
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\begin{frame}{Samsung HBM-PIM/FIMDRAM\autocite{lee2021}}
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\begin{itemize}
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\item Real-world PIM implementation based on HBM2
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\item PIM units embedded at the bank level
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\end{itemize}
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\begin{figure}
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\includesvg[width=0.8\textwidth]{images/hbm-pim}
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\end{figure}
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\end{frame}
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\begin{frame}{Samsung HBM-PIM/FIMDRAM\autocite{lee2021}}
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\begin{columns}
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\begin{column}{0.4\textwidth}
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Processing units:
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\begin{itemize}
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\item Two 16-wide 16-bit FPUs
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\item Register files and control unit
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\end{itemize}
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Instructions:
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\begin{itemize}
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\item Control: NOP, JUMP, EXIT
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\item Data: MOV (ReLU), FILL
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\item Arithmetic: ADD, MUL, MAC, MAD
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\end{itemize}
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\end{column}
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\begin{column}{0.6\textwidth}
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\begin{figure}
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\includesvg[width=\textwidth]{images/pu}
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\end{figure}
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\end{column}
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\end{columns}
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\end{frame}
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\begin{frame}{HBM-PIM/FIMDRAM GEMV Operation}
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\begin{figure}
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\only<1>{\includesvg[width=0.8\textwidth]{images/gemv_normal}}
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\only<2>{\includesvg[width=0.9\textwidth]{images/gemv_interleaved}}
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\end{figure}
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\end{frame}
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\begin{frame}{HBM-PIM/FIMDRAM GEMV Operation\autocite{kang2022}}
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\begin{figure}
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\only<1>{\includesvg[width=0.55\textwidth]{images/gemv.svg}}
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\only<2>{\includesvg[width=0.55\textwidth]{images/gemv_0.svg}}
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\only<3>{\includesvg[width=0.55\textwidth]{images/gemv_1.svg}}
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\only<4>{\includesvg[width=0.55\textwidth]{images/gemv_2.svg}}
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\only<5>{\includesvg[width=0.55\textwidth]{images/gemv_3.svg}}
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\only<6>{\includesvg[width=0.55\textwidth]{images/gemv_4.svg}}
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\end{figure}
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\end{frame}
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\begin{frame}{HBM-PIM/FIMDRAM}
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\begin{huge}
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How fast is it?
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\end{huge}\\
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Research should ...
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\begin{itemize}
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\item ... conduct simulations to explore \alert{performance gains}
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\item ... consider also the programmability to identify \alert{challenges}
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\end{itemize}
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\end{frame}
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\section{Virtual Prototype}
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\begin{frame}{Virtual Prototype}
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\begin{itemize}
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\item Coupling of gem5 and DRAMSys
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\item Implementation of HBM-PIM in DRAM model
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\end{itemize}
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\begin{figure}
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\includesvg[width=0.8\textwidth]{images/dramsys.svg}
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\end{figure}
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\end{frame}
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\begin{frame}{Software Library}
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Software support library
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\begin{columns}
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\begin{column}{0.5\textwidth}
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\begin{itemize}
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\item Initialization
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\begin{itemize}
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\item Assembly and loading of microkernel
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\end{itemize}
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\item Execution
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\begin{itemize}
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\item Generation of RD and WR requests
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\item Insetion of memory barriers
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\end{itemize}
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\end{itemize}
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\end{column}
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\begin{column}{0.5\textwidth}
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\begin{figure}
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\includesvg[width=0.8\textwidth]{images/data_structures.svg}
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\end{figure}
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\end{column}
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\end{columns}
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\end{frame}
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\begin{frame}[fragile]{Example: GEMV Kernel}
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\begin{center}
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\only<1>{
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\inputminted[firstline=1,lastline=8, fontsize=\footnotesize]{gas}{kernel.s}
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\hrule
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\inputminted[firstline=7,lastline=10,fontsize=\footnotesize]{rust}{kernel.rs}
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}
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\only<2>{
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\inputminted[firstline=9,lastline=10, fontsize=\footnotesize]{gas}{kernel.s}
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\hrule
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\inputminted[firstline=12,lastline=20,fontsize=\footnotesize]{rust}{kernel.rs}
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}
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\only<3>{
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\inputminted[firstline=11,lastline=12,fontsize=\footnotesize]{gas}{kernel.s}
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\hrule
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\inputminted[firstline=22,lastline=30,fontsize=\footnotesize]{rust}{kernel.rs}
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}
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\end{center}
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\end{frame}
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\begin{frame}{Virtual Prototype Platform}
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\begin{columns}
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\begin{column}{0.5\textwidth}
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\begin{itemize}
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\item ARM processor model
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\item Bare-metal kernel
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\item Custom page table configuration
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\begin{itemize}
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\item Non-PIM DRAM region mapped as cacheable memory
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\item PIM DRAM region mapped as non-cacheable memory
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\end{itemize}
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\end{itemize}
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\end{column}
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\begin{column}{0.5\textwidth}
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\begin{figure}
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\includesvg[width=0.8\textwidth]{images/bare_metal.svg}
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\end{figure}
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\end{column}
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\end{columns}
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\end{frame}
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\section{Simulations}
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\begin{frame}{Microbenchmarks}
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\begin{columns}
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\begin{column}{0.5\textwidth}
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\begin{itemize}
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\item Vector benchmarks (BLAS level 1)
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\item VADD: $z = x + y$
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\item VMUL: $z = x \cdot y$
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\item HAXPY: $z = a \cdot x + y$
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\item Vector-Matrix benchmarks (BLAS level 2)
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\begin{itemize}
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\item GEMV: $z = A \cdot x$
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\item Simple DNN:
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\begin{itemize}
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\item $f(x) = z = ReLU(A \cdot x)$
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\item $z_{n+1} = f(z_n)$
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\item 5 layers in total
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\end{itemize}
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\end{itemize}
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\end{itemize}
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\end{column}
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\begin{column}{0.5\textwidth}
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\begin{figure}
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\begin{tblr}{
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hlines,
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column{1} = {c},
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column{2} = {r},
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column{3} = {r},
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column{4} = {r},
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row{1} = {l},
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hline{2} = {2}{-}{solid,black},
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}
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Level & Vector & GEMV & DNN \\
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X1 & 2M & (1k $\times$ 4k) & (256 $\times$ 256) \\
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X2 & 4M & (2k $\times$ 4k) & (512 $\times$ 512) \\
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X3 & 8M & (4k $\times$ 8k) & (1k $\times$ 1k) \\
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X4 & 16M & (8k $\times$ 8k) & (2k $\times$ 2k)
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\end{tblr}
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\end{figure}
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\end{column}
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\end{columns}
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\end{frame}
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\begin{frame}{System Configuration}
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\begin{columns}[t]
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\begin{column}{0.5\textwidth}
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Two simulated systems:
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\begin{itemize}
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\item Generic ARM system
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\item Infinite compute system
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\begin{itemize}
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\item Unrealistic high frequency of 100 GHz
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\item Completely memory bound
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\item Lower bound of possible speedup
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\end{itemize}
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\end{itemize}
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\end{column}
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\begin{column}{0.5\textwidth}
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Two real GPUs using HBM2:
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\begin{itemize}
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\item AMD RX Vega 56
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\item NVIDIA Tesla V100
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\end{itemize}
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\end{column}
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\end{columns}
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\end{frame}
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\begin{frame}{Speedups / Generic ARM System}
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\begin{figure}
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\includesvg[width=0.8\textwidth]{images/speedup_normal.svg}
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\end{figure}
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\end{frame}
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\begin{frame}{Speedups / Infinite Compute System}
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\begin{figure}
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\includesvg[width=0.8\textwidth]{images/speedup_inf.svg}
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\end{figure}
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\end{frame}
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\begin{frame}{Speedups / Samsung}
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\begin{figure}
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\includesvg[width=0.8\textwidth]{images/samsung.svg}
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\end{figure}
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\end{frame}
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\begin{frame}{Runtimes / Vector Benchmarks}
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\begin{figure}
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\includesvg[width=0.8\textwidth]{images/runtimes_vector.svg}
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\end{figure}
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\end{frame}
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\begin{frame}{Runtimes / Matrix Benchmarks}
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\begin{figure}
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\includesvg[width=0.8\textwidth]{images/runtimes_matrix.svg}
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\end{figure}
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\end{frame}
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\begin{frame}{Conclusion and Future Work}
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\begin{itemize}
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\item PIM can accelerate memory-bound workloads
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\item Special PIM-friendly memory layouts are required
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\end{itemize}
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Future work:
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\begin{itemize}
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\item Implementation of Linux driver
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\item Comparison with real neural networks
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\item Consider replacing library approach with compiler approach
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\item Implement a power model to analyze the power efficiency gains
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\end{itemize}
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\end{frame}
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\section{Thank you for your attention!}
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\begin{frame}
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\frametitle{Outline}
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\tableofcontents
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\end{frame}
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\end{document}
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