DRAMSys and VP chapter completed

src/chapters/vp.tex

@@ -7,13 +7,13 @@ It even may allow for the identification of potential improvements to the \ac{pi
 In addition, the suitability of different applications for \ac{pim} can be evaluated, as well as the influence of the specific memory layout requirements on the application software.
 
 To perform the such simulations, it is necessary to use a simulation model, commonly referred to as a \ac{vp}.
-\Ac{vp} act as executable software models of a physical hardware system, allowing the architecture of the system to be completely simulated in software.
+\Acp{vp} act as executable software models of a physical hardware system, allowing the architecture of the system to be completely simulated in software.
 This in turn enables the software development and the identification of potential platform-specific software bugs without the need for the actual hardware implementation \cite{antonino2018}.
 \Acp{vp} provide full visibility and control over the entire simulated system, helping to identify bottlenecks and potential specification errors in the design.
 They also allow the exploration of the design space, for example, in the case of \ac{hbm}-\ac{pim}, this includes the variation of the ratio of \ac{pim} units to the number of memory banks and the effect on the performance of the \ac{pim} microkernel.
 
 However, using the appropriate level of abstraction in the software model is critical to make well-informed statements about the system without compromising the performance of the software model itself by delving into excessively low-level details, such as the \ac{rtl}.
-A viable compromise is the \ac{at} abstraction level within the \ac{tlm} technique, which is widely used in the SystemC \cite{systemc2023} virtual prototyping framework.
+A viable compromise is the \ac{at} abstraction level within the \ac{tlm} technique, which is widely used in the SystemC \cite{systemc2023} virtual prototyping standard.
 The \ac{at} abstraction simplifies the modeling of communication between different system components by representing it only through synchronized function calls at different times.
 This approach eliminates the need to simulate complex bus protocols while maintaining the accuracy required for design space exploration and performance evaluation.
 
@@ -37,11 +37,26 @@ An example of such an external model is the \ac{dram} simulator DRAMSys, which i
 
 \subsection{DRAMSys}
 
+DRAMSys is an open-source framework for design space exploration and provides the ability to simulate the latest \ac{jedec} \ac{dram} standards \cite{steiner2022a}.
+The framework is optimized for high simulation speed and uses the \ac{at} coding style, while ensuring cycle-accurate results.
+\Cref{img:dramsys} provides an overview of the internal architecture of DRAMSys, which consists of a frontend, a backend and the memory models.
+
 \begin{figure}
 	\centering
 	\includegraphics[width=0.8\linewidth]{images/dramsys}
-	\caption[]{Arch \cite{jung2017a}.}
+	\caption[The internal architecture of DRAMSys]{The internal architecture of DRAMSys \cite{jung2017a}.}
 	\label{img:dramsys}
 \end{figure}
 
-\cite{steiner2022a}.
+The arbitration unit routes incoming packets to the appropriate channel controller based on the address mapping.
+Each independent channel controller is responsible for controlling a single DRAM channel and issuing the necessary DRAM commands for read and write operations.
+The scheduler, located within a channel controller, has the ability to reorder incoming requests to optimize for specific metrics.
+In conjunction with the response queue, requests can be completed out-of-order, improving overall system performance based on a specific metric.
+
+At the frontend of DRAMSys, a variety of initiators can be connected, including traffic generators that generate random accesses, as well as sophisticated processor model such as gem5.
+In cases where such a processor model is used to execute a user application, DRAMSys uses its internal memory model to store and retrieve the requested data, rather than ignoring the contents of the request.
+
+DRAMSys provides support for the latest \ac{jedec} \ac{dram} standards, including \aca{hbm}.
+Thus, gem5 and DRAMSys together form a robust platform for implementing and researching the \ac{hbm}-\ac{pim} architecture introduced by Samsung, entirely through a software model.
+To achieve this, the \aca{hbm} \ac{dram} model must be extended to include the \ac{pim} units integrated into each \ac{pch}.
+The following section provides a detailed description of this implementation of \ac{hbm}-\ac{pim}, the \ac{pim} virtual machine.