VPs and gem5

src/acronyms.tex

@@ -251,7 +251,23 @@
     short = FPGA,
     long = field-programmable gate array,
 }
+\DeclareAcronym{vp}{
+    short = VP,
+    long = virtual prototype,
+}
+\DeclareAcronym{rtl}{
+    short = RTL,
+    long = register-transfer level,
+}
 \DeclareAcronym{tlm}{
     short = TLM,
     long = transaction-level modeling,
 }
+\DeclareAcronym{at}{
+    short = AT,
+    long = approximately-timed,
+}
+\DeclareAcronym{api}{
+    short = API,
+    long = application programming interface,
+}

src/chapters/vp.tex

@@ -1,5 +1,47 @@
 \section{Virtual Prototypes and System-Level Modeling}
 \label{sec:vp}
 
+To evaluate the impact of \ac{pim} on the performance and power consumption of various applications, it is essential to perform simulations.
+Such an approach allows investigating critical factors such as the \ac{pim} microkernel setup overhead and the actual efficiency of the \ac{pim} kernel compared to traditional platforms.
+It even may allow for the identification of potential improvements to the \ac{pim} architecture.
+In addition, the suitability of different applications for \ac{pim} can be evaluated, as well as the influence of the specific memory layout requirements on the application software.
+
+To perform the such simulations, it is necessary to use a simulation model, commonly referred to as a \ac{vp}.
+\Ac{vp} act as executable software models of a physical hardware system, allowing the architecture of the system to be completely simulated in software.
+This in turn enables the software development and the identification of potential platform-specific software bugs without the need for the actual hardware implementation \cite{antonino2018}.
+\Acp{vp} provide full visibility and control over the entire simulated system, helping to identify bottlenecks and potential specification errors in the design.
+They also allow the exploration of the design space, for example, in the case of \ac{hbm}-\ac{pim}, this includes the variation of the ratio of \ac{pim} units to the number of memory banks and the effect on the performance of the \ac{pim} microkernel.
+
+However, using the appropriate level of abstraction in the software model is critical to make well-informed statements about the system without compromising the performance of the software model itself by delving into excessively low-level details, such as the \ac{rtl}.
+A viable compromise is the \ac{at} abstraction level within the \ac{tlm} technique, which is widely used in the SystemC \cite{systemc2023} virtual prototyping framework.
+The \ac{at} abstraction simplifies the modeling of communication between different system components by representing it only through synchronized function calls at different times.
+This approach eliminates the need to simulate complex bus protocols while maintaining the accuracy required for design space exploration and performance evaluation.
+
+Two different \ac{at} simulation frameworks used in the implementation of the \ac{hbm}-\ac{pim} software model, namely gem5 and DRAMSys, are introduced in the following sections.
+
 \subsection{The gem5 Simulator}
+
+The gem5 simulator is an open-source computer architecture simulation platform used for system-level architecture research \cite{lowe-power2020}.
+This powerful platform allows the measurement of various statistics, including runtime, memory bandwidth, and internal processor metrics across different hardware configurations.
+The gem5 simulator runs a user application and simulates it with it's sophisticated models with accurate timing.
+It consists of a simulator core and parameterized models for many components, including out-of-order processors, bus systems, and \ac{dram}.
+As a result, gem5 provides a comprehensive framework for simulating and analyzing complex computer systems.
+
+Two different modes can be used with gem5: full system simulation and system call emulation.
+In full system mode, gem5 boots a complete operating system kernel and runs the user's application on top of it to generate detailed statistics.
+In system call emulation mode, the simulated application uses the syscall interface of the host operating system, ignoring the timing effects of these operating system routines.
+Consequently, the full system mode provides better accuracy, while the system call emulation mode takes less time to complete the simulation.
+
+In addition to the integrated components of the platform, gem5 provides a SystemC \ac{api} to enable the use of external SystemC models.
+An example of such an external model is the \ac{dram} simulator DRAMSys, which is based on \ac{tlm} to provide cycle-accurate memory models without sacrificing simulation performance.
+
 \subsection{DRAMSys}
+
+\begin{figure}
+	\centering
+	\includegraphics[width=0.8\linewidth]{images/dramsys}
+	\caption[]{Arch \cite{jung2017a}.}
+	\label{img:dramsys}
+\end{figure}
+
+\cite{steiner2022a}.

src/doc.bib

@@ -5,6 +5,20 @@
   file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/N5Y7EZNT/2021 - Changing Exception level and Security state in an .pdf}
 }
 
+@inproceedings{antonino2018,
+  title = {Enabling {{Continuous Software Engineering}} for {{Embedded Systems Architectures}} with {{Virtual Prototypes}}},
+  booktitle = {Software {{Architecture}}},
+  author = {Antonino, Pablo Oliveira and Jung, Matthias and Morgenstern, Andreas and Faßnacht, Florian and Bauer, Thomas and Bachorek, Adam and Kuhn, Thomas and Nakagawa, Elisa Yumi},
+  editor = {Cuesta, Carlos E. and Garlan, David and Pérez, Jennifer},
+  date = {2018},
+  pages = {115--130},
+  publisher = {{Springer International Publishing}},
+  location = {{Cham}},
+  abstract = {Continuous software engineering aims at orchestrating engineering knowledge from various disciplines in order to deal with the rapid changes within the ecosystems of which software-based systems are part of. The literature claims that one means to ensure these prompt responses is to incorporate virtual prototypes of the system as early as possible in the development process, such that requirements and architecture decisions are verified early and continuously by means of simulations. Despite the maturity of practices for designing and assessing architectures, as well as for virtual prototyping, it is still not clear how to jointly consider the practices from these disciplines within development processes, in order to address the dynamics imposed by continuous software engineering. In this regard, we discuss in this paper how to orchestrate architecture drivers and design specification techniques with virtual prototypes, to address the demands of continuous software engineering in development processes. Our proposals are based on experiences from research and industry projects in various domains such as automotive, agriculture, construction, and medical devices.},
+  isbn = {978-3-030-00761-4},
+  file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/KGD8N29E/Antonino et al. - 2018 - Enabling Continuous Software Engineering for Embed.pdf}
+}
+
 @article{arm2015,
   title = {{{ARM Cortex-A Series Programmer}}’s {{Guide}} for {{ARMv8-A}}},
   author = {{ARM}},
@@ -503,6 +517,18 @@
   file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/SWBFKXLG/Sudarshan et al. - 2022 - A Weighted Current Summation Based Mixed Signal DR.pdf}
 }
 
+@book{systemc2023,
+  title = {1666-2023 - {{IEEE Standard}} for {{Standard SystemC Language Reference Manual}}},
+  date = {2023},
+  publisher = {{IEEE}},
+  location = {{New York}},
+  abstract = {SystemC® is defined in this standard. SystemC is an ISO standard C++ class library for system and hardware design for use by designers and architects who need to address complex systems that are a hybrid between hardware and software. This standard provides a precise and complete definition of the SystemC class library so that a SystemC implementation can be developed with reference to this standard alone. The primary audiences for this standard are the implementors of the SystemC class library, the implementors of tools supporting the class library, and the users of the class library},
+  isbn = {978-1-5044-9867-8},
+  langid = {english},
+  annotation = {OCLC: 1397698694},
+  file = {/home/derek/Nextcloud/Verschiedenes/Zotero/storage/46IIZIMH/2023 - 1666-2023 - IEEE Standard for Standard SystemC Lan.pdf}
+}
+
 @online{touvron2023,
   title = {{{LLaMA}}: {{Open}} and {{Efficient Foundation Language Models}}},
   shorttitle = {{{LLaMA}}},

src/index.tex

@@ -19,7 +19,7 @@
 \usepackage{lipsum}
 \usepackage{siunitx}
 \usepackage{url}
-\usepackage[urldate=long,sorting=none]{biblatex}
+\usepackage[urldate=long,sorting=none,maxbibnames=5]{biblatex}
 \usepackage{pgfplots}
 \usepackage{bytefield}
 \usepackage{mathdots}