VPs and gem5

src/chapters/vp.tex

@@ -1,5 +1,47 @@
 \section{Virtual Prototypes and System-Level Modeling}
 \label{sec:vp}
 
+To evaluate the impact of \ac{pim} on the performance and power consumption of various applications, it is essential to perform simulations.
+Such an approach allows investigating critical factors such as the \ac{pim} microkernel setup overhead and the actual efficiency of the \ac{pim} kernel compared to traditional platforms.
+It even may allow for the identification of potential improvements to the \ac{pim} architecture.
+In addition, the suitability of different applications for \ac{pim} can be evaluated, as well as the influence of the specific memory layout requirements on the application software.
+
+To perform the such simulations, it is necessary to use a simulation model, commonly referred to as a \ac{vp}.
+\Ac{vp} act as executable software models of a physical hardware system, allowing the architecture of the system to be completely simulated in software.
+This in turn enables the software development and the identification of potential platform-specific software bugs without the need for the actual hardware implementation \cite{antonino2018}.
+\Acp{vp} provide full visibility and control over the entire simulated system, helping to identify bottlenecks and potential specification errors in the design.
+They also allow the exploration of the design space, for example, in the case of \ac{hbm}-\ac{pim}, this includes the variation of the ratio of \ac{pim} units to the number of memory banks and the effect on the performance of the \ac{pim} microkernel.
+
+However, using the appropriate level of abstraction in the software model is critical to make well-informed statements about the system without compromising the performance of the software model itself by delving into excessively low-level details, such as the \ac{rtl}.
+A viable compromise is the \ac{at} abstraction level within the \ac{tlm} technique, which is widely used in the SystemC \cite{systemc2023} virtual prototyping framework.
+The \ac{at} abstraction simplifies the modeling of communication between different system components by representing it only through synchronized function calls at different times.
+This approach eliminates the need to simulate complex bus protocols while maintaining the accuracy required for design space exploration and performance evaluation.
+
+Two different \ac{at} simulation frameworks used in the implementation of the \ac{hbm}-\ac{pim} software model, namely gem5 and DRAMSys, are introduced in the following sections.
+
 \subsection{The gem5 Simulator}
+
+The gem5 simulator is an open-source computer architecture simulation platform used for system-level architecture research \cite{lowe-power2020}.
+This powerful platform allows the measurement of various statistics, including runtime, memory bandwidth, and internal processor metrics across different hardware configurations.
+The gem5 simulator runs a user application and simulates it with it's sophisticated models with accurate timing.
+It consists of a simulator core and parameterized models for many components, including out-of-order processors, bus systems, and \ac{dram}.
+As a result, gem5 provides a comprehensive framework for simulating and analyzing complex computer systems.
+
+Two different modes can be used with gem5: full system simulation and system call emulation.
+In full system mode, gem5 boots a complete operating system kernel and runs the user's application on top of it to generate detailed statistics.
+In system call emulation mode, the simulated application uses the syscall interface of the host operating system, ignoring the timing effects of these operating system routines.
+Consequently, the full system mode provides better accuracy, while the system call emulation mode takes less time to complete the simulation.
+
+In addition to the integrated components of the platform, gem5 provides a SystemC \ac{api} to enable the use of external SystemC models.
+An example of such an external model is the \ac{dram} simulator DRAMSys, which is based on \ac{tlm} to provide cycle-accurate memory models without sacrificing simulation performance.
+
 \subsection{DRAMSys}
+
+\begin{figure}
+	\centering
+	\includegraphics[width=0.8\linewidth]{images/dramsys}
+	\caption[]{Arch \cite{jung2017a}.}
+	\label{img:dramsys}
+\end{figure}
+
+\cite{steiner2022a}.