Minor changes

slides/implementation.md

@@ -38,28 +38,12 @@ figureCaption: Data structures for instructions and register files
 
 - Provides data structures for operand data and microkernels
 - Executes programmed microkernels
-
----
-layout: figure-side
-figureUrl: /bare_metal.svg
----
-
-## Virtual Prototype
-### Platform
-<hr/>
-
-<br>
-<br>
-
-- Bare-metal kernel executes on ARM processor model
-- Custom page table configuration
-  - Non-PIM DRAM region mapped as cacheable memory
-  - PIM DRAM region mapped as non-cacheable memory
+  - generate RD and WR requests
 
 ---
 
 ## Virtual Prototype
-### Platform
+### GEMV Kernel
 <hr/>
 
 <br>
@@ -68,7 +52,7 @@ figureUrl: /bare_metal.svg
 <div>
 
 DRAM-side
-```asm{all|1-8|9,10|11|12|all}{lines:true,at:1}
+```asm{all|1-8|9,10|11|12}{lines:true,at:1}
 MOV GRF_A #0, BANK
 MOV GRF_A #1, BANK
 MOV GRF_A #2, BANK
@@ -94,7 +78,7 @@ code {
 
 Host-side
 
-```rust {all|7-10|12-17|19-28|30-31|all}{lines:true,maxHeight:'15em',at:1}
+```rust {all|7-10|12-17|19-28|30-31}{lines:true,maxHeight:'15em',at:1}
 pub fn execute<const X16R: usize, const X16C: usize, const R: usize>(
     matrix: &Matrix<X16R, X16C>,
     input_vector: &Vector<X16C>,
@@ -131,4 +115,24 @@ pub fn execute<const X16R: usize, const X16C: usize, const R: usize>(
 </div>
 </div>
 
-<!-- </Transform> -->
+---
+layout: figure-side
+figureUrl: /bare_metal.svg
+---
+
+## Virtual Prototype
+### Platform
+<hr/>
+
+<br>
+<br>
+
+- ARM processor model
+- Bare-metal kernel
+- Custom page table configuration
+  - Non-PIM DRAM region mapped as cacheable memory
+  - PIM DRAM region mapped as non-cacheable memory
+
+<!--
+- bare metal offers most control
+-->