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Derek Christ
2024-04-09 16:10:45 +02:00
parent d634f97fb2
commit 6acaf838be
19 changed files with 31957 additions and 1598 deletions
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slides.md
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@@ -21,6 +21,10 @@ record: true
# System-Level Integration and Exploration of PIM-DRAM # System-Level Integration and Exploration of PIM-DRAM
<!--
- results of master thesis
-->
--- ---
src: ./slides/introduction.md src: ./slides/introduction.md
--- ---
@@ -47,3 +51,7 @@ layout: end
# Thank you for your attention # Thank you for your attention
<hr/> <hr/>
---
src: ./slides/appendix.md
---

49
slides/appendix.md
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@@ -1,42 +1,13 @@
---
layout: figure
figureUrl: /layout.svg
figureCaption: Mapping of the weight matrix onto the memory banks
---
## Appendix ## Appendix
### GEMV Kernel ### Memory Layout
<hr/> <hr/>
<Transform :scale="0.7"> <!--
- Data layout in program and address mapping must match
```rust {all}{lines:true} -->
pub fn execute<const X16R: usize, const X16C: usize, const R: usize>(
matrix: &Matrix<X16R, X16C>,
input_vector: &Vector<X16C>,
output_partial_sum_vector: &mut SVector<F16x16, R>,
dummy: &impl PimOperand,
) {
// Load input vector into GRF-A registers
for chunk in input_vector.0.iter() {
chunk.execute_read();
}
// Execute the MAC instructions without memory barriers
for sub_matrix in matrix.0.iter() {
for column_block in sub_matrix.fixed_rows::<1>(0).iter() {
column_block.execute_read_async();
}
}
// Verify all memory accesses have finished
barrier::dsb(barrier::SY);
// Copy the partial sums into the bank
for chunk in output_partial_sum_vector
.fixed_rows_with_step_mut::<X16R>(0, 16)
.iter_mut()
{
chunk.execute_write();
}
// Execute the EXIT instruction
dummy.execute_read();
}
```
</Transform>

2
slides/conclusion.md
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@@ -1,6 +1,7 @@
## Conclusion and Future Work ## Conclusion and Future Work
<hr/> <hr/>
<br>
<br> <br>
- PIM can accelerate memory-bound workloads - PIM can accelerate memory-bound workloads
@@ -9,6 +10,7 @@
<br> <br>
#### Future work: #### Future work:
- Simulate multiple channels
- Implementation of Linux driver - Implementation of Linux driver
- Comparison with complete neural networks - Comparison with complete neural networks
- Consider replacing library approach with compiler approach - Consider replacing library approach with compiler approach

2
slides/implementation.md
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@@ -78,7 +78,7 @@ code {
Host-side Host-side
```rust {all|7-10|12-17|19-28|30-31}{lines:true,maxHeight:'15em',at:1} ```rust {all|7-10|12-17|22-28|30-31}{lines:true,maxHeight:'15em',at:1}
pub fn execute<const X16R: usize, const X16C: usize, const R: usize>( pub fn execute<const X16R: usize, const X16C: usize, const R: usize>(
matrix: &Matrix<X16R, X16C>, matrix: &Matrix<X16R, X16C>,
input_vector: &Vector<X16C>, input_vector: &Vector<X16C>,

18
slides/introduction.md
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@@ -2,11 +2,10 @@
### Energy Demand of Applications ### Energy Demand of Applications
<hr/> <hr/>
<br>
- Total compute energy approaches world's energy production - Total compute energy approaches world's energy production
--> drastic improvements in energy efficiency needed --> Drastic improvements in energy efficiency needed
<div class="flex justify-center"> <div class="flex justify-center">
<img src="/world_energy.svg"> <img src="/world_energy.svg">
@@ -19,11 +18,10 @@
</Footnotes> </Footnotes>
<!-- <!--
- compute doubles every two years - compute 2x every two years
- energy production grows linearly at 2% per year - energy production 2% per year
- to meet future compute demands - to meet future compute demands, drastic improvements in energy efficiency
- -> drastic improvements in energy efficiency
--> -->
--- ---
@@ -32,9 +30,9 @@
### Memory Bound Workloads ### Memory Bound Workloads
<hr/> <hr/>
<br> - AI applications become increasingly memory-bound
- AI workloads become increasingly memory-bound --> Instead of bringing the data to the processing, bring the processing to the data
<br> <br>
@@ -52,5 +50,7 @@
- Emerging AI applications become increasingly memory-bound - Emerging AI applications become increasingly memory-bound
- Roofline model - Roofline model
- Not limited by compute power but by memory - Not limited by compute power but by memory
-> researchers begin to consider processing in memory to circumvent memory bottleneck - researchers begin to consider PIM to circumvent memory bottleneck
- (drastically more parameters in GPT-3, operational intensity goes down)
--> -->

69
slides/pim.md
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@@ -10,11 +10,6 @@
<img src="/dnn.svg"> <img src="/dnn.svg">
</div> </div>
<!--
- fully connected layers of a neural network
- Such that PIM is effective, workload must be memory-bound
-->
--- ---
preload: false preload: false
clicks: 1 clicks: 1
@@ -45,10 +40,6 @@ clicks: 1
</div> </div>
</Transform> </Transform>
<!--
- filter matrix is reused
-->
--- ---
## Processing-in-Memory ## Processing-in-Memory
@@ -58,19 +49,24 @@ clicks: 1
<br> <br>
<br> <br>
<br> <br>
<br>
<div class="grid grid-cols-2 gap-4"> <div class="grid grid-cols-2 gap-4">
<div> <div>
### Suitable candidates for PIM: ### Suitable candidates for PIM:
<br>
- Fully connected layers in multilayer perceptrons (MLPs) - Fully connected layers in multilayer perceptrons (MLPs)
- Layers in recurrent neural networks (RNNs) - Layers in recurrent neural networks (RNNs)
</div> </div>
<div> <div>
### Unsuitable candidates for PIM: ### Less suitable candidates for PIM:
<br>
- Convolutional neural networks (CNNs) - Convolutional neural networks (CNNs)
</div> </div>
@@ -175,7 +171,7 @@ To summarize...
--- ---
## Processing-in-Memory ## Processing-in-Memory
### Samsung's PIM-HBM ### Samsung's PIM-HBM | Processing Unit
<hr/> <hr/>
<br> <br>
@@ -183,9 +179,14 @@ To summarize...
- Two 16-wide 16-bit FPUs - Two 16-wide 16-bit FPUs
- Register files and control unit - Register files and control unit
<div class="flex justify-center items-center"> <br>
<img src="/pu.svg">
</div> #### Instructions:
- Control: NOP, JUMP, EXIT
- Data: MOV (ReLU), FILL
- Arithmetic: ADD, MUL, MAC, MAD
<img class="absolute right-80px top-180px" src="/pu.svg">
<Footnotes separator> <Footnotes separator>
<Footnote> <Footnote>
@@ -206,15 +207,27 @@ To summarize...
--> -->
--- ---
layout: figure
figureUrl: /gemv.svg ## Processing-in-Memory
figureCaption: Procedure to perform a (128×8)×(128) GEMV operation ### Samsung's PIM-HBM | GEMV Operation
<hr/>
<img v-click="[0,1]" class="absolute right-125px top-150px" src="/gemv_normal.svg">
<img v-click="1" class="absolute right-10px top-150px" src="/gemv_interleaved.svg">
--- ---
## Processing-in-Memory ## Processing-in-Memory
### Samsung's PIM-HBM ### Samsung's PIM-HBM | GEMV Operation
<hr/> <hr/>
<img v-click="[0,1]" class="absolute right-250px top-150px" src="/gemv.svg">
<img v-click="[1,2]" class="absolute right-250px top-150px" src="/gemv_0.svg">
<img v-click="[2,3]" class="absolute right-250px top-150px" src="/gemv_1.svg">
<img v-click="[3,4]" class="absolute right-250px top-150px" src="/gemv_2.svg">
<img v-click="[4,5]" class="absolute right-250px top-150px" src="/gemv_3.svg">
<img v-click="5" class="absolute right-250px top-150px" src="/gemv_4.svg">
<Footnotes separator> <Footnotes separator>
<Footnote> <Footnote>
Lee et al. „Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product“, 2021. Lee et al. „Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product“, 2021.
@@ -228,20 +241,6 @@ figureCaption: Procedure to perform a (128×8)×(128) GEMV operation
- partial sum, reduced by host - partial sum, reduced by host
--> -->
---
layout: figure
figureUrl: /layout.svg
figureCaption: Mapping of the weight matrix onto the memory banks
---
## Processing-in-Memory
### Samsung's PIM-HBM
<hr/>
<!--
- Data layout in program and address mapping must match
-->
--- ---
## Processing-in-Memory ## Processing-in-Memory
@@ -253,8 +252,8 @@ figureCaption: Mapping of the weight matrix onto the memory banks
<br> <br>
<br> <br>
- Simulations are needed to analyze the performance gains of PIM - To analyze the performance gains of PIM, simulations are needed
- Research should not only focus on hardware but also explore the software side - Research should not only focus on hardware but also explore the programmability
<br> <br>

6
slides/simulations.md
View File

@@ -59,18 +59,22 @@ Operand Dimensions
- Generic ARM system - Generic ARM system
- Infinite compute system - Infinite compute system
- unrealistic frequency of 100 GHz
- completely memory bound - completely memory bound
- lower bound of possible speedup
</div> </div>
<div> <div>
<br>
#### Two real GPUs using HBM2: #### Two real GPUs using HBM2:
<br> <br>
- AMD RX Vega 56 - AMD RX Vega 56
- NVIDIA V100 - NVIDIA Tesla V100
</div> </div>
</div> </div>