100 lines
2.2 KiB
VHDL
100 lines
2.2 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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library work;
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use work.lt16x32_internal.all;
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use work.lt16x32_global.all;
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use work.wishbone.all;
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use work.config.all;
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package lt16soc_peripherals is
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component wb_led is
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generic(
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memaddr : generic_addr_type;-- := CFG_BADR_LED;
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addrmask : generic_mask_type-- := CFG_MADR_LED;
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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led : out std_logic_vector(7 downto 0);
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type
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);
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end component;
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component wb_switches is
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generic(
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memaddr : generic_addr_type; --:= CFG_BADR_SW;
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addrmask : generic_mask_type --:= CFG_MADR_SW;
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type;
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buttons : in std_logic_vector(4 downto 0);
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switches : in std_logic_vector(15 downto 0)
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);
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end component;
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component wb_timer is
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generic(
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memaddr : generic_addr_type; --:= CFG_BADR_TIMER;
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addrmask : generic_mask_type --:= CFG_MADR_TIMER;
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type;
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interrupt : out std_logic
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);
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end component;
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component wb_segment is
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generic(
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memaddr : generic_addr_type; --:= CFG_BADR_SEG;
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addrmask : generic_mask_type --:= CFG_BADR_SEG;
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type;
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anodes : out std_logic_vector(7 downto 0);
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cathodes : out std_logic_vector(7 downto 0)
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);
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end component;
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component wb_segment_adv is
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generic(
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memaddr : generic_addr_type; --:= CFG_BADR_SEG;
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addrmask : generic_mask_type --:= CFG_BADR_SEG;
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type;
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anodes : out std_logic_vector(7 downto 0);
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cathodes : out std_logic_vector(7 downto 0)
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);
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end component;
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end lt16soc_peripherals;
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package body lt16soc_peripherals is
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--insert function bodies
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end lt16soc_peripherals;
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