138 lines
3.4 KiB
VHDL
138 lines
3.4 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.lt16x32_global.all;
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use work.wishbone.all;
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use work.config.all;
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entity wb_segment is
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generic(
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memaddr : generic_addr_type; --:= CFG_BADR_SEG;
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addrmask : generic_mask_type --:= CFG_MADR_SEG;
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type;
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anodes : out std_logic_vector(7 downto 0);
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cathodes : out std_logic_vector(7 downto 0)
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);
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end wb_segment;
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architecture Behavioral of wb_segment is
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signal ack : std_logic;
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signal hex_register : std_logic_vector(63 downto 0);
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signal data_out : std_logic_vector(63 downto 0);
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signal hex : std_logic_vector(4 downto 0);
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signal timer_overflow : std_logic;
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signal overflow_counter : integer range 0 to 7;
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component hex2physical
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port(
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hex : in std_logic_vector(4 downto 0);
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cathodes : out std_logic_vector(7 downto 0)
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);
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end component;
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component simple_timer
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generic(
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timer_start : std_logic_vector (31 downto 0)
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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timer_overflow : out std_logic
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);
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end component;
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begin
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converter : hex2physical
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port map(
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hex => hex,
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cathodes => cathodes
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);
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timer: simple_timer
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generic map (timer_start => x"00000008")
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port map(
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clk => clk,
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rst => rst,
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timer_overflow => timer_overflow
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);
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process(clk)
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begin
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if clk'event and clk='1' then
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if rst = '1' then
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ack <= '0';
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data_out <= (others=>'0');
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hex_register <= (others=>'0');
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else
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data_out <= (others=>'0');
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if wslvi.stb = '1' and wslvi.cyc = '1' then
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if wslvi.we='0' then
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data_out <= hex_register;
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else
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-- Write enable
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if wslvi.adr(2) = '0' then
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hex_register(31 downto 0) <= dec_wb_dat(wslvi.sel,wslvi.dat);
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else -- wslvi.adr(2) = '1'
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hex_register(63 downto 32) <= dec_wb_dat(wslvi.sel,wslvi.dat);
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end if;
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end if;
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if ack = '0' then
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ack <= '1';
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else
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ack <= '0';
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end if;
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else
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ack <= '0';
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end if;
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end if;
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end if;
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end process;
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process(clk)
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begin
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if clk'event and clk='1' then
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if rst = '1' then
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hex <= hex_register(4 downto 0);
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anodes <= (others => '0');
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overflow_counter <= 0;
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else
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if timer_overflow = '1' then
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if overflow_counter = 7 then
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overflow_counter <= 0;
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else
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overflow_counter <= overflow_counter + 1;
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end if;
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anodes <= (others => '0');
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anodes(overflow_counter) <= '1';
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hex <= hex_register(overflow_counter * 8 + 4 downto overflow_counter * 8);
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end if;
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end if;
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end if;
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end process;
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wslvo.dat <=
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data_out(31 downto 0) when wslvi.adr(2) = '0' else
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data_out(63 downto 32) when wslvi.adr(2) = '1';
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wslvo.ack <= ack;
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wslvo.wbcfg <= wb_membar(memaddr, addrmask);
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end Behavioral;
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