243 lines
6.5 KiB
VHDL
243 lines
6.5 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.lt16x32_global.all;
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use work.wishbone.all;
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use work.config.all;
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entity wb_scrolling is
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generic(
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memaddr : generic_addr_type; --:= CFG_BADR_SCR;
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addrmask : generic_mask_type --:= CFG_MADR_SCR;
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type;
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anodes : out std_logic_vector(7 downto 0);
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cathodes : out std_logic_vector(7 downto 0)
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);
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end wb_scrolling;
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architecture Behavioral of wb_scrolling is
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signal cnt_start : std_logic;
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signal cnt_done : std_logic;
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signal cnt_value : std_logic_vector(31 downto 0);
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signal buffer_clear : std_logic;
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signal buffer_write : std_logic;
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signal buffer_data : std_logic_vector(4 downto 0);
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signal seg_data : std_logic_vector(3 downto 0);
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signal seg_off : std_logic;
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signal seg_shift : std_logic;
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signal seg_write : std_logic;
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signal seg_clear : std_logic;
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signal on_off : std_logic;
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signal next_char : std_logic;
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signal hex_char : std_logic_vector(4 downto 0);
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signal data_out : std_logic_vector(63 downto 0);
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signal data_in : std_logic_vector(63 downto 0);
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signal data_in_changed : std_logic;
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signal ack : std_logic;
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component scrolling_timer is
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port(
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clk : in std_logic;
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rst : in std_logic;
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cnt_start : in std_logic;
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cnt_done : out std_logic;
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cnt_value : in std_logic_vector(31 downto 0)
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);
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end component;
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component scrolling_buffer
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port(
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clk : in std_logic;
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rst : in std_logic;
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buffer_clear : in std_logic;
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buffer_write : in std_logic;
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buffer_data : in std_logic_vector(4 downto 0);
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next_char : in std_logic;
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hex_char : out std_logic_vector(4 downto 0)
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);
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end component;
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component scrolling_controller
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port(
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clk : in std_logic;
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rst : in std_logic;
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on_off : in std_logic;
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cnt_start : out std_logic;
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cnt_done : in std_logic;
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next_char : out std_logic;
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hex_char : in std_logic_vector(4 downto 0);
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seg_data : out std_logic_vector(3 downto 0);
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seg_off : out std_logic;
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seg_shift : out std_logic;
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seg_write : out std_logic;
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seg_clear : out std_logic
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);
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end component;
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component seven_segment_display is
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port(
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clk : in std_logic;
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rst : in std_logic;
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seg_data : in std_logic_vector(3 downto 0);
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seg_off : in std_logic;
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seg_shift : in std_logic;
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seg_write : in std_logic;
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seg_clear : in std_logic;
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anodes : out std_logic_vector(7 downto 0);
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cathodes : out std_logic_vector(7 downto 0)
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);
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end component;
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begin
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timer: scrolling_timer
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port map(
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clk => clk,
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rst => rst,
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cnt_start => cnt_start,
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cnt_done => cnt_done,
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cnt_value => cnt_value
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);
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buf: scrolling_buffer
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port map(
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clk => clk,
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rst => rst,
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buffer_clear => buffer_clear,
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buffer_write => buffer_write,
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buffer_data => buffer_data,
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next_char => next_char,
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hex_char => hex_char
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);
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controller: scrolling_controller
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port map(
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clk => clk,
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rst => rst,
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on_off => on_off,
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cnt_start => cnt_start,
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cnt_done => cnt_done,
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next_char => next_char,
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hex_char => hex_char,
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seg_data => seg_data,
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seg_off => seg_off,
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seg_shift => seg_shift,
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seg_write => seg_write,
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seg_clear => seg_clear
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);
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seven_segment: seven_segment_display
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port map(
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clk => clk,
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rst => rst,
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seg_data => seg_data,
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seg_off => seg_off,
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seg_shift => seg_shift,
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seg_write => seg_write,
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seg_clear => seg_clear,
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anodes => anodes,
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cathodes => cathodes
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);
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process(clk)
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begin
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if clk'event and clk='1' then
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if rst = '1' then
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ack <= '0';
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data_in <= (others => '0');
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data_in_changed <= '0';
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else
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data_in <= (others => '0');
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data_in_changed <= '0';
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if wslvi.stb = '1' and wslvi.cyc = '1' then
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if wslvi.we='0' then
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-- data_out will have the correct value
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else
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-- Write enable
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data_in_changed <= '1';
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if wslvi.adr(2) = '0' then
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data_in(31 downto 0) <= dec_wb_dat(wslvi.sel,wslvi.dat);
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else
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data_in(63 downto 32) <= dec_wb_dat(wslvi.sel,wslvi.dat);
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end if;
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end if;
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if ack = '0' then
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ack <= '1';
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else
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ack <= '0';
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end if;
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else
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ack <= '0';
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end if;
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end if;
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end if;
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end process;
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process(clk)
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begin
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if clk'event and clk='1' then
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if rst = '1' then
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cnt_value <= (others => '0');
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buffer_write <= '0';
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buffer_clear <= '0';
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buffer_data <= (others => '0');
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on_off <= '0';
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else
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buffer_write <= '0';
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buffer_clear <= '0';
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buffer_data <= (others => '0');
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on_off <= '0';
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if data_in_changed = '1' and ack = '1' then
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if wslvi.adr(2) = '1' then
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cnt_value <= data_in(63 downto 32);
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else
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buffer_write <= data_in(24);
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buffer_clear <= data_in(8);
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buffer_data <= data_in(20 downto 16);
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on_off <= data_in(0);
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end if;
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end if;
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end if;
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end if;
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end process;
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data_out(31 downto 25) <= (others => '0');
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data_out(24) <= buffer_write;
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data_out(23 downto 21) <= (others => '0');
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data_out(20 downto 16) <= buffer_data;
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data_out(15 downto 9) <= (others => '0');
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data_out(8) <= buffer_clear;
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data_out(7 downto 1) <= (others => '0');
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data_out(0) <= on_off;
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data_out(63 downto 32) <= cnt_value;
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wslvo.dat <=
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data_out(31 downto 0) when wslvi.adr(2) = '0' else
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data_out(63 downto 32) when wslvi.adr(2) = '1';
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wslvo.ack <= ack;
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wslvo.wbcfg <= wb_membar(memaddr, addrmask);
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end Behavioral;
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