94 lines
2.1 KiB
VHDL
94 lines
2.1 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.lt16x32_internal.all;
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use work.lt16x32_global.all;
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use work.wishbone.all;
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use work.config.all;
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entity mem2wb is
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generic(
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memaddr : generic_addr_type := CFG_BADR_MEM;
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addrmask : generic_mask_type := CFG_MADR_MEM
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_dmem : out core_dmem;
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out_dmem : in dmem_core;
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type
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);
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end mem2wb;
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ARCHITECTURE Behavioral OF mem2wb IS
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signal indmem : core_dmem;
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signal ack : std_logic;
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BEGIN
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wbs2dmem: process(wslvi)
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begin
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--init
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indmem.write_en <= '0';
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indmem.write_addr(memory_width - 1 downto WB_ADR_BOUND) <= (others=>'0');
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indmem.write_addr(1 downto 0) <= "00";
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indmem.write_data <= (others=>'0');
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indmem.write_size <= "00";
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--
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indmem.read_en <= '0';
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indmem.read_addr(memory_width - 1 downto WB_ADR_BOUND) <= (others=>'0');
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indmem.read_addr(1 downto 0) <= "00";
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indmem.read_size <= "00";
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--end init
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if wslvi.stb = '1' and wslvi.cyc = '1' then
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if wslvi.we = '1' then
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indmem.write_en <= '1';
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indmem.write_addr <= wslvi.adr & sel2adr(wslvi.sel);
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indmem.write_data <= dec_wb_dat(wslvi.sel, wslvi.dat);
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indmem.write_size <= decsz(wslvi.sel);
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else
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indmem.read_en <= '1';
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indmem.read_addr <= wslvi.adr & sel2adr(wslvi.sel);
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indmem.read_size <= decsz(wslvi.sel);
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end if;
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end if;
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end process;
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---
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in_dmem <= indmem;
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dmem2wbs:process(out_dmem, indmem.read_addr, indmem.read_size)
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begin
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--init
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wslvo.dat <= (others=>'0');
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--end init
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wslvo.dat <= enc_wb_dat(indmem.read_addr(1 downto 0), indmem.read_size, out_dmem.read_data);
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end process;
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process(clk, rst)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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ack <= '0';
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else
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if wslvi.stb = '1' and wslvi.cyc = '1' and ack = '0' and out_dmem.ready = '1' then
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ack <= '1';
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else
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ack <= '0';
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end if;
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end if;
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end if;
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end process;
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wslvo.ack <= ack;
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wslvo.wbcfg <= wb_membar(memaddr, addrmask);
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END ARCHITECTURE;
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