144 lines
3.4 KiB
VHDL
144 lines
3.4 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 01/04/2023 01:55:04 PM
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-- Design Name:
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-- Module Name: internal_can - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity internal_can is
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port(
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-- clock signal
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clk : in std_logic;
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-- external reset button
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rst : in std_logic;
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led : out std_logic_vector(7 downto 0);
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btn : in std_logic_vector(4 downto 0);
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sw : in std_logic_vector(15 downto 0);
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anodes : out std_logic_vector(7 downto 0);
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cathodes : out std_logic_vector(7 downto 0);
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can_rx_i : in std_logic;
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can_tx_o : out std_logic
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);
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end entity;
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architecture Behavioral of internal_can is
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COMPONENT lt16soc_top IS
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generic(
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programfilename : string := "../../programs/project.ram"
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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led : out std_logic_vector(7 downto 0);
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btn : in std_logic_vector(4 downto 0);
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sw : in std_logic_vector(15 downto 0);
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anodes : out std_logic_vector(7 downto 0);
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cathodes : out std_logic_vector(7 downto 0);
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can_rx_i : in std_logic;
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can_tx_o : out std_logic
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);
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END COMPONENT;
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component phys_can_sim
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generic(
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peer_num : integer );
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port(
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rst : in std_logic;
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rx_vector : out std_logic_vector(peer_num - 1 downto 0);
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tx_vector : in std_logic_vector(peer_num - 1 downto 0) );
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end component phys_can_sim;
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constant peer_num_inst : integer := 2;
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signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
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signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
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signal rst_n : std_logic;
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signal btn_cpy : std_logic_vector(4 downto 0) := (others => '0');
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signal sw_cpy : std_logic_vector(15 downto 0) := (others => '0');
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signal anodes_cpy : std_logic_vector(7 downto 0);
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signal cathodes_cpy : std_logic_vector(7 downto 0);
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signal led_cpy : std_logic_vector(7 downto 0);
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begin
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soc0: lt16soc_top
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generic map(
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programfilename => "../../programs/project.ram"
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)
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port map(
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clk=>clk,
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rst=>rst,
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led=>led,
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btn=>btn,
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sw=>sw,
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anodes=>anodes,
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cathodes=>cathodes,
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can_rx_i=>rx_vector(0),
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can_tx_o=>tx_vector(0)
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);
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soc1: lt16soc_top
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generic map(
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programfilename => "../../programs/project.ram"
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)
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port map(
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clk=>clk,
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rst=>rst,
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led=>led_cpy,
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btn=>btn_cpy,
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sw=>sw_cpy,
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anodes=>anodes_cpy,
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cathodes=>cathodes_cpy,
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can_rx_i=>rx_vector(1),
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can_tx_o=>tx_vector(1)
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);
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can_interconnect : phys_can_sim
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generic map(
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peer_num => peer_num_inst
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)
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port map(
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rst => rst_n,
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rx_vector => rx_vector,
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tx_vector => tx_vector
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);
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rst_n <= not rst;
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can_tx_o <= tx_vector(1);
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-- TODO: für pmod !read enable auf low setzen
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end Behavioral;
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