436 lines
7.8 KiB
Plaintext
436 lines
7.8 KiB
Plaintext
reset:
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br always >main
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nop
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hardfault:
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reti
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nop
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memfault:
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reti
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nop
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switches_interrupt:
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br >switches_interrupt_handler
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nop
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can_interrupt:
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br >can_interrupt_handler
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nop
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.align
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dmem_start_addr: .word 0x00000400
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dmem_end_addr: .word 0x000004FC
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led_addr: .word 0x000F0000
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switches_addr: .word 0x000F0004
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scrolling_addr: .word 0x000F00A0
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scrolling_count_addr: .word 0x000F00A4
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priority_mask: .word 0xFFFFFF03
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write_mask: .word 0x1000000
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clear_mask: .word 0x100
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scrolling_cnt_value: .word 0x10FC000 // for real board
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// scrolling_cnt_value: .word 0x500 // for simulation
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// CAN
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can_control_addr: .word 0x000F0100
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can_command_addr: .word 0x000F0101
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can_interrupt_addr: .word 0x000F0103
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can_acceptance_code_addr: .word 0x000F0104
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can_acceptance_mask_addr: .word 0x000F0105
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can_bus_timing0_addr: .word 0x000F0106
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can_bus_timing1_addr: .word 0x000F0107
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can_output_control_addr: .word 0x000F0108
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// CAN Constants
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acceptance_code: .word 0x00
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acceptance_mask: .word 0xFF
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btr0: .word 0x45 // for Real board
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btr1: .word 0x16 // for Real board
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// btr0: .word 0x80
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// btr1: .word 0x48
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output_control: .word 0x02
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control: .word 0xFE
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rx_interrupt_mask: .word 0x01
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tx_interrupt_mask: .word 0x02
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main:
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// Initialize stack pointer to the end of the data memory
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ldr r12, >dmem_end_addr
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// Set runtime priority
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ldr r0, >priority_mask
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and r14, r0, r14
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// --- CAN init ---
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ldr r0, >can_acceptance_code_addr
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ldr r3, >acceptance_code
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st08 r0, r3
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ldr r0, >can_acceptance_mask_addr
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ldr r3, >acceptance_mask
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st08 r0, r3
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ldr r0, >can_bus_timing0_addr
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ldr r3, >btr0
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st08 r0, r3
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ldr r0, >can_bus_timing1_addr
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ldr r3, >btr1
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st08 r0, r3
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ldr r0, >can_output_control_addr
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ldr r3, >output_control
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st08 r0, r3
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ldr r0, >can_control_addr
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ldr r3, >control
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st08 r0, r3
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// Start scrolling controller
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ldr r0, >scrolling_addr
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clr r3
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addi r3, 0x01
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st32 r0, r3
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// (Re)set scrolling speed
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ldr r5, >scrolling_count_addr
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ldr r4, >scrolling_cnt_value
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st32 r5, r4
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// Set LED to state
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ldr r0, >led_addr
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clr r3
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addi r3, 0x7A
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st08 r0, r3
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loop:
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br >loop
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nop
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.align
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button_data_add: .word 0x10000
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button_data_clear: .word 0x20000
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button_frequency: .word 0x40000
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switches_interrupt_handler:
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// Read switch state
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ldr r0, >switches_addr
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ld32 r2, r0
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ldr r0, >led_addr
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st08 r0, r2
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clr r4
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ldr r3, >button_data_clear
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and r5, r2, r3
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cmp neq r5, r4
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br true >can_send_data_clear_frame
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nop
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ldr r3, >button_data_add
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and r5, r2, r3
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cmp neq r5, r4
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br true >can_send_data_add_frame
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nop
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ldr r3, >button_frequency
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and r5, r2, r3
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cmp neq r5, r4
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br true >can_send_frequency_frame
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nop
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// Unimplemented button function
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reti
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nop
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can_interrupt_handler:
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// Dispatch interrupt event
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ldr r0, >can_interrupt_addr
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ld08 r1, r0
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clr r4
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ldr r2, >rx_interrupt_mask
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and r5, r1, r2
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cmp neq r5, r4
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br true >can_rx_handler
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nop
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ldr r2, >tx_interrupt_mask
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and r5, r1, r2
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cmp neq r5, r4
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br true >can_tx_handler
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nop
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// Unimplemented CAN interrupt
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reti
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nop
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.align
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can_tx_data0_addr: .word 0x000F010C
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can_tx_data1_addr: .word 0x000F010D
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can_tx_data2_addr: .word 0x000F010E
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can_tx_identifier0_addr: .word 0x000F010A
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can_tx_identifier1_addr: .word 0x000F010B
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id0: .word 0xAA
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id1_0: .word 0xC1 // data length is also encoded here
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id1_1: .word 0xC2 // data length is also encoded here
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id1_2: .word 0xC3 // data length is also encoded here
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frame_data_add: .word 0x00
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frame_data_clear: .word 0x01
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frame_frequency: .word 0x02
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can_command_addr_ptr: .word =can_command_addr
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can_send_data_clear_frame:
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ldr r0, >can_tx_identifier0_addr
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ldr r3, >id0
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st08 r0, r3
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ldr r0, >can_tx_identifier1_addr
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ldr r3, >id1_0
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st08 r0, r3
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ldr r0, >can_tx_data0_addr
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ldr r3, >frame_data_clear
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st08 r0, r3
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// Save for tx interrupt
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clr r6
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add r6, r6, r3
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ldr r0, >can_command_addr_ptr
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ld32 r0, r0
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clr r3
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addi r3, 0x01
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st08 r0, r3
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reti
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nop
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.align
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byte_mask: .word 0xFF
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can_send_data_add_frame:
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ldr r0, >can_tx_identifier0_addr
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ldr r3, >id0
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st08 r0, r3
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ldr r0, >can_tx_identifier1_addr
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ldr r3, >id1_1
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st08 r0, r3
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ldr r0, >can_tx_data0_addr
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ldr r3, >frame_data_add
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st08 r0, r3
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// Save for tx interrupt
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clr r6
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add r6, r6, r3
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// r2 is still switches reg
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ldr r0, >can_tx_data1_addr
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st08 r0, r2
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// Save for tx interrupt
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clr r7
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add r7, r7, r2
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ldr r4, >byte_mask
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and r7, r7, r4
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ldr r0, >can_command_addr_ptr
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ld32 r0, r0
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clr r3
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addi r3, 0x01
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st08 r0, r3
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reti
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nop
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.align
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can_rx_data0_addr: .word 0x000F0116
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can_rx_handler:
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// Dispatch CAN frame
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ldr r0, >can_rx_data0_addr
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ld08 r6, r0
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ldr r2, >frame_data_clear
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cmp eq r2, r6
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br true >can_handle_data_clear_frame
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nop
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ldr r2, >frame_data_add
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cmp eq r2, r6
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br true >can_handle_data_add_frame
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nop
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ldr r2, >frame_frequency
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cmp eq r2, r6
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br true >can_handle_frequency_frame
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nop
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// Unimplemented CAN frame
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reti
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nop
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can_tx_handler:
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// Dispatch CAN frame
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ldr r2, >frame_data_clear
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cmp eq r2, r6
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br true >handle_data_clear_frame
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nop
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ldr r2, >frame_data_add
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cmp eq r2, r6
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br true >handle_data_add_frame
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nop
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ldr r2, >frame_frequency
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cmp eq r2, r6
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br true >handle_frequency_frame
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nop
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reti
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nop
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can_send_frequency_frame:
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ldr r0, >can_tx_identifier0_addr
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ldr r3, >id0
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st08 r0, r3
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ldr r0, >can_tx_identifier1_addr
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ldr r3, >id1_2
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st08 r0, r3
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ldr r0, >can_tx_data0_addr
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ldr r3, >frame_frequency
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st08 r0, r3
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// Save for tx interrupt
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clr r6
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add r6, r6, r3
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// r2 is still switches reg
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ldr r0, >can_tx_data1_addr
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st08 r0, r2
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// Save for tx interrupt
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clr r7
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add r7, r7, r2
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ldr r4, >byte_mask
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and r7, r7, r4
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ldr r0, >can_tx_data2_addr
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rsh r2, r2, 8
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st08 r0, r2
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// Save for tx interrupt
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clr r8
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add r8, r8, r2
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ldr r4, >byte_mask
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and r8, r8, r4
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ldr r0, >can_command_addr_ptr
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ld32 r0, r0
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clr r3
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addi r3, 0x01
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st08 r0, r3
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reti
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nop
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can_handle_data_clear_frame:
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// Release receive buffer
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ldr r0, >can_command_addr_ptr
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ld32 r0, r0
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clr r1
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addi r1, 0x04
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st08 r0, r1
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handle_data_clear_frame:
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ldr r0, >scrolling_addr_ptr
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ldr r1, >clear_mask_ptr
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ld32 r0, r0
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ld32 r1, r1
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st32 r0, r1
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reti
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nop
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.align
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scrolling_addr_ptr: .word =scrolling_addr
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write_mask_ptr: .word =write_mask
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can_command_addr_ptr0: .word =can_command_addr
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can_rx_data1_addr: .word 0x000F0117
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can_rx_data2_addr: .word 0x000F0118
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can_handle_data_add_frame:
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ldr r0, >can_rx_data1_addr
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ld08 r7, r0
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// Release receive buffer
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ldr r0, >can_command_addr_ptr0
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ld32 r0, r0
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clr r1
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addi r1, 0x04
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st08 r0, r1
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handle_data_add_frame:
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// Expect symbol to add in r7 register
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ldr r0, >scrolling_addr_ptr
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ld32 r0, r0
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ldr r1, >write_mask_ptr
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ld32 r1, r1
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lsh r7, r7, 16
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or r4, r7, r1
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st32 r0, r4
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reti
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nop
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.align
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clear_mask_ptr: .word =clear_mask
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scrolling_count_addr_ptr: .word =scrolling_count_addr
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can_handle_frequency_frame:
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ldr r0, >can_rx_data1_addr
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ld08 r7, r0
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ldr r0, >can_rx_data2_addr
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ld08 r8, r0
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// Release receive buffer
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ldr r0, >can_command_addr_ptr0
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ld32 r0, r0
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clr r1
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addi r1, 0x04
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st08 r0, r1
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handle_frequency_frame:
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// Expect count value in r7 and r8 register
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// For real board shift the count value by 16!
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// Concat bits
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lsh r8, r8, 8
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or r8, r8, r7
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lsh r8, r8, 16 // real board !!!
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ldr r0, >scrolling_count_addr_ptr
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ld32 r0, r0
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st32 r0, r8
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reti
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nop
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