87 lines
2.6 KiB
VHDL
87 lines
2.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity scrolling_buffer is
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port(
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clk : in std_logic;
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rst : in std_logic;
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buffer_clear : in std_logic;
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buffer_write : in std_logic;
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buffer_data : in std_logic_vector(4 downto 0);
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next_char : in std_logic;
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hex_char : out std_logic_vector(4 downto 0);
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elements : out std_logic_vector(4 downto 0)
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);
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end entity scrolling_buffer;
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architecture Behavioral of scrolling_buffer is
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constant BUFFER_SIZE : integer := 16;
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type ring_buffer_type is array (0 to BUFFER_SIZE - 1) of std_logic_vector(4 downto 0);
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signal ptr_write : integer range 0 to BUFFER_SIZE - 1;
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signal ptr_read : integer range 0 to BUFFER_SIZE - 1;
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signal ptr_last : integer range -1 to BUFFER_SIZE - 1;
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signal ring_buffer : ring_buffer_type;
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begin
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process(clk)
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begin
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if clk'event and clk='1' then
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if rst = '1' then
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ptr_last <= -1;
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ptr_write <= 0;
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ring_buffer <= (others => (others => '0'));
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elements <= (others => '0');
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else
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if buffer_write = '1' then
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ring_buffer(ptr_write) <= buffer_data;
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if ptr_last /= BUFFER_SIZE - 1 then
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ptr_last <= ptr_write;
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elements <= std_logic_vector(to_unsigned(ptr_write + 1, 5));
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end if;
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if ptr_write = BUFFER_SIZE - 1 then
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ptr_write <= 0;
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else
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ptr_write <= ptr_write + 1;
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end if;
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elsif buffer_clear = '1' then
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ptr_last <= -1;
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end if;
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end if;
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end if;
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end process;
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process(clk)
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begin
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if clk'event and clk='1' then
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if rst = '1' then
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ptr_read <= 0;
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hex_char <= (others => '0');
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else
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hex_char <= (others => '0');
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if next_char = '1' then
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if ptr_last = -1 then -- Special case
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hex_char <= (others => '0');
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else
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hex_char <= ring_buffer(ptr_read);
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if ptr_read = ptr_last then
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ptr_read <= 0;
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else
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ptr_read <= ptr_read + 1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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