120 lines
2.7 KiB
VHDL
120 lines
2.7 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use IEEE.std_logic_textio.all;
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library std;
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use std.standard.all;
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use std.textio.all;
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library work;
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use work.wishbone.all;
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use work.config.all;
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use work.wb_tp.all;
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use work.txt_util.all;
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use work.lt16soc_peripherals.all;
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use work.lt16soc_memories.all;
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ENTITY wb_intercon_simple_tb IS
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END wb_intercon_simple_tb;
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ARCHITECTURE behavior OF wb_intercon_simple_tb IS
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-- component Declaration for the Unit Under Test (UUT)
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component wb_intercon
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generic(
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slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"0000_0000_0000_0000";
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mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"0000"
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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msti : out wb_mst_in_vector;
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msto : in wb_mst_out_vector;
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slvi : out wb_slv_in_vector;
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slvo : in wb_slv_out_vector
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);
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end component;
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--Inputs
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signal clk : std_logic := '0';
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signal rst : std_logic := '0';
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signal msto : wb_mst_out_vector;
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signal slvo : wb_slv_out_vector;
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--Outputs
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signal msti : wb_mst_in_vector;
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signal slvi : wb_slv_in_vector;
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signal led : std_logic_vector(7 downto 0);
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signal data : std_logic_vector(31 downto 0);
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---------------------
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-- constant
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---------------------
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constant CLK_PERIOD : time := 10 ns;
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constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1110_0000_0000_0001";
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constant mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"1000";
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begin
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-- Instantiate the Unit Under Test (UUT)
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uut: wb_intercon
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generic map(
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slv_mask_vector => slv_mask_vector,
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mst_mask_vector => mst_mask_vector
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)
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port map(
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clk => clk,
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rst => rst,
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msti => msti,
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msto => msto,
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slvi => slvi,
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slvo => slvo
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);
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dmem : wb_dmem
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generic map(
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memaddr=>CFG_BADR_DMEM,
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addrmask=>CFG_MADR_DMEM)
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port map(clk,rst,slvi(CFG_DMEM),slvo(CFG_DMEM));
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leddev : wb_led
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generic map(
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CFG_BADR_LED,CFG_MADR_LED
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)
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port map(
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clk,rst,led,slvi(CFG_LED),slvo(CFG_LED)
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);
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clk_gen : process
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begin
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clk <= '0';
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wait for CLK_PERIOD/2;
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clk <= '1';
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wait for CLK_PERIOD/2;
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end process;
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stimuli: process
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begin
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rst <= '1';
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wait for CLK_PERIOD;
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rst <= '0';
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data <= x"EDAB3F5C";
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generate_sync_wb_burst_write(msto(0),slvo(CFG_DMEM),clk,data,4);
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data <= not data;
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-- generate_sync_wb_single_write(msto(0),slvo(CFG_DMEM),clk,data);
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wait for 2*CLK_PERIOD;
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generate_sync_wb_burst_read(msto(0),slvo(CFG_DMEM),clk,data,4);
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wait;
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end process stimuli;
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END;
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