89 lines
1.5 KiB
VHDL
89 lines
1.5 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY work;
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USE work.lt16soc_peripherals.ALL;
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ENTITY hex2physical_tb IS
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END ENTITY;
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ARCHITECTURE sim OF hex2physical_tb IS
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signal hex : std_logic_vector(4 downto 0) := "00000";
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signal cathodes : std_logic_vector(7 downto 0);
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component hex2physical
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port(
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hex : in std_logic_vector(4 downto 0);
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cathodes : out std_logic_vector(7 downto 0)
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);
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end component;
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BEGIN
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converter: hex2physical
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port map(
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hex => hex,
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cathodes => cathodes
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);
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stimuli: process
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begin
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hex <= "00000";
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wait for 2 ns;
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hex <= "00001";
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wait for 2 ns;
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hex <= "00010";
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wait for 2 ns;
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hex <= "00011";
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wait for 2 ns;
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hex <= "00100";
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wait for 2 ns;
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hex <= "00101";
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wait for 2 ns;
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hex <= "00110";
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wait for 2 ns;
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hex <= "00111";
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wait for 2 ns;
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hex <= "01000";
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wait for 2 ns;
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hex <= "01001";
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wait for 2 ns;
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hex <= "01010";
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wait for 2 ns;
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hex <= "01011";
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wait for 2 ns;
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hex <= "01100";
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wait for 2 ns;
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hex <= "01101";
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wait for 2 ns;
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hex <= "01110";
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wait for 2 ns;
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hex <= "01111";
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wait for 2 ns;
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hex <= "10000";
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wait for 2 ns;
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assert false report "Simulation terminated!" severity failure;
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end process stimuli;
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END ARCHITECTURE;
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