44 lines
928 B
VHDL
44 lines
928 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity simple_timer is
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generic(
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timer_start : std_logic_vector (31 downto 0)
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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timer_overflow : out std_logic
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);
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end entity simple_timer;
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architecture Behavioral of simple_timer is
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signal counter : integer range 1 to to_integer(unsigned(timer_start));
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signal overflow : std_logic;
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begin
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process(clk)
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begin
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if clk'event and clk='1' then
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if rst = '1' then
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counter <= to_integer(unsigned(timer_start));
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else
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overflow <= '0';
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if counter = 1 then
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counter <= to_integer(unsigned(timer_start));
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overflow <= '1';
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else
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counter <= counter - 1;
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end if;
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end if;
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end if;
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end process;
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timer_overflow <= overflow;
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end Behavioral;
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