80 lines
4.0 KiB
TeX
80 lines
4.0 KiB
TeX
\chapter{Interrupts}
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\section{Interrupt Controller}
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\label{sec:irq_ctrl}
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The interrupt controller features a configurable number of interrupt lines with a configurable amount of priorities.
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The configuration follows that of the \procname (see Section \ref{sec:config}).
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These intterupts lines need to be asserted for one clock cycle to trigger an interrupt request to the processor core.
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Additionally, trap requests from the core are handled (as described in \ref{sec:trap}).
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\section{Priority, NMI}
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\label{sec:nmi}
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The processor features multiple levels of runtime priority (configurable, see Section \ref{sec:config_priowidth}) where a greater number means higher priority.
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Additionally, non maskable interrupts (NMI) are supported which are always executed regardless the current processor runtime priority.
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The processor starts with the highest possible runtime priority by default to disable interrupts at startup (with the exception of NMI).
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This is needed as the stack pointer needs to be set to a valid address before any interrupt (including NMI) can be executed.
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\section{Interface and Timing Diagram}
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Both ports \inlinevhdl{in\_irq} and \inlinevhdl{out\_irq} (for type definitions see Listing \ref{lst:typedef_irq}) should be connected to a fitting interrupt controller (for example the implementation described in Section \ref{sec:irq_ctrl}).
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\begin{vhdl}[Type definitions for Interrupt Controller Ports]{lst:typedef_irq}
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-- collection of all signals from the
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-- interrupt controller to the core
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type irq_core is record
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-- interrupt number of requested interrupt
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num : unsigned(irq_num_width - 1 downto 0);
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-- priority of requested interrupt
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-- (higher number means higher priority)
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priority : unsigned(irq_prio_width - 1 downto 0);
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-- request signal, active high
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req : std_logic;
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-- non maskable interrupt flag, active high
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nmi : std_logic;
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end record;
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-- collection of all signals from the core
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-- to the interrupt controller
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type core_irq is record
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-- interrupt acknowledge
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-- high if requested interrupt is processed
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ack : std_logic;
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-- number of interrupt requested by
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-- internal trap instruction
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trap_num : unsigned(irq_num_width - 1 downto 0);
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-- request signal for internal trap, active high
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trap_req : std_logic;
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end record;
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\end{vhdl}
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\subsection{Interrupt Request}
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The external world (i.e. the interrupt controller) can request an interrupt by writing the interrupt number, its priority to \inlinevhdl{in\_irq} and setting the \inlinevhdl{nmi} bit accordingly.
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After these are set, \inlinevhdl{req} can be asserted and must be held high until the core acknowledges the interrupt request by asserting \inlinevhdl{ack} for one clock cycle (see Figure \ref{fig:signal_irq_req}).
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\begin{figure}[htb]
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\center
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\includegraphics[scale=1]{./figures/signal_irq_req.pdf}
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\caption{Signal Pattern for Interrupt Requests}
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\label{fig:signal_irq_req}
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\end{figure}
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\subsection{Trap Implementation}
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\label{sec:trap}
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When executing a trap instruction, an interrupt line to the interrupt controller is asserted for one clock cycle with the interrupt number asserted as well, see Figure \ref{fig:signal_irq_trap}.
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Note, that an arbitrary time (and number of instructions) may take place between a trap and the interrupt handler execution.
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\begin{figure}[htb]
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\centering
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\includegraphics[scale=1]{./figures/signal_irq_trap.pdf}
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\caption{Signal Pattern for Trap Instruction}
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\label{fig:signal_irq_trap}
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\end{figure}
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\subsection{Processor Interrupt Behavior}
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\label{sec:InterruptEntryCPU}
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When an interrupt is accepted by the processor, it saves the current PC and status register on the stack.
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Then it replaces the runtime priority in the status register with interrupt's priority and replaces the PC with the interupt vector number.
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The \textit{reti} instruction reverses this and resturn to the previous executed program.
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Note that the processor by itself does not save any registers apart from status register and program counter.
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Any other register that needs to be preserved needs to be saved manually.
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