-- See the file "LICENSE" for the full license governing this code. --
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

LIBRARY work;
USE work.lt16soc_peripherals.ALL;

ENTITY hex2physical_tb IS
END ENTITY;

ARCHITECTURE sim OF hex2physical_tb IS

	signal hex : std_logic_vector(4 downto 0) := "00000";
    signal cathodes : std_logic_vector(7 downto 0);

    component hex2physical
    port(
        hex : in std_logic_vector(4 downto 0);
        cathodes : out std_logic_vector(7 downto 0)
    );
    end component;

BEGIN

	converter: hex2physical
        port map(
			hex => hex,
            cathodes => cathodes
		);

	stimuli: process
	begin		
        hex <= "00000";
		wait for 2 ns;

        hex <= "00001";
		wait for 2 ns;

        hex <= "00010";
		wait for 2 ns;

        hex <= "00011";
		wait for 2 ns;

        hex <= "00100";
		wait for 2 ns;

        hex <= "00101";
		wait for 2 ns;

        hex <= "00110";
		wait for 2 ns;

        hex <= "00111";
		wait for 2 ns;

        hex <= "01000";
		wait for 2 ns;

        hex <= "01001";
		wait for 2 ns;

        hex <= "01010";
		wait for 2 ns;

        hex <= "01011";
		wait for 2 ns;

        hex <= "01100";
		wait for 2 ns;

        hex <= "01101";
		wait for 2 ns;

        hex <= "01110";
		wait for 2 ns;

        hex <= "01111";
		wait for 2 ns;

        hex <= "10000";
		wait for 2 ns;

		assert false report "Simulation terminated!" severity failure;
	end process stimuli;

END ARCHITECTURE;