-- See the file "LICENSE" for the full license governing this code. --
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

LIBRARY work;
USE work.lt16soc_peripherals.ALL;
USE work.wishbone.ALL;
USE work.wb_tp.ALL;
USE work.config.ALL;

ENTITY scrolling_top_tb IS
END ENTITY;

ARCHITECTURE sim OF scrolling_top_tb IS

	constant CLK_PERIOD : time := 10 ns;

	signal clk 	: std_logic := '0';
	signal rst	: std_logic;
	signal data	: std_logic_vector(WB_PORT_SIZE-1 downto 0) := (others => '0');
	
    signal anodes: std_logic_vector(7 downto 0);
    signal cathodes : std_logic_vector(7 downto 0);

	signal slvi	: wb_slv_in_type;
	signal slvo	: wb_slv_out_type;

BEGIN

	SIM_SLV: wb_scrolling
		generic map(
			memaddr		=> CFG_BADR_SCR,
			addrmask	=> CFG_MADR_SCR
		)
		port map(
			clk		=> clk,
			rst		=> rst,
			anodes => anodes,
			cathodes => cathodes,
			wslvi	=> slvi,
			wslvo	=> slvo
		);

	clk_gen: process
	begin
		clk	<= not clk;
		wait for CLK_PERIOD / 2;
	end process clk_gen;

	stimuli: process
	begin
		rst	<= '1';
		wait for CLK_PERIOD;
		rst	<= '0';
        
		wait for CLK_PERIOD;
		
        -- Set cnt_value
        data <= x"00000100";
		generate_sync_wb_single_write(slvi,slvo,clk,data, ADR_OFFSET => 4);
		
		wait for 2 ns;
		
        data <= (others => '0');
        data(24) <= '1'; -- buffer_write
        data(20 downto 16) <= '0' & x"D"; -- buffer_data
        data(8) <= '0'; -- buffer_clear
        data(0) <= '1'; -- on_off
		generate_sync_wb_single_write(slvi,slvo,clk,data);
		wait for CLK_PERIOD;
		
        data <= (others => '0');
        data(24) <= '1'; -- buffer_write
        data(20 downto 16) <= '0' & x"E"; -- buffer_data
        data(8) <= '0'; -- buffer_clear
        data(0) <= '0'; -- on_off
		generate_sync_wb_single_write(slvi,slvo,clk,data);
		wait for CLK_PERIOD;
		
        data <= (others => '0');
        data(24) <= '1'; -- buffer_write
        data(20 downto 16) <= '0' & x"A"; -- buffer_data
        data(8) <= '0'; -- buffer_clear
        data(0) <= '0'; -- on_off
		generate_sync_wb_single_write(slvi,slvo,clk,data);
		wait for CLK_PERIOD;
				
        data <= (others => '0');
        data(24) <= '1'; -- buffer_write
        data(20 downto 16) <= '0' & x"D"; -- buffer_data
        data(8) <= '0'; -- buffer_clear
        data(0) <= '0'; -- on_off
		generate_sync_wb_single_write(slvi,slvo,clk,data);
		wait for CLK_PERIOD;
		
		wait for 100 us;
		
        data <= (others => '0');
        data(24) <= '1'; -- buffer_write
        data(20 downto 16) <= '0' & x"B"; -- buffer_data
        data(8) <= '0'; -- buffer_clear
        data(0) <= '0'; -- on_off
		generate_sync_wb_single_write(slvi,slvo,clk,data);
		wait for CLK_PERIOD;
		
        data <= (others => '0');
        data(24) <= '1'; -- buffer_write
        data(20 downto 16) <= '0' & x"E"; -- buffer_data
        data(8) <= '0'; -- buffer_clear
        data(0) <= '0'; -- on_off
		generate_sync_wb_single_write(slvi,slvo,clk,data);
		wait for CLK_PERIOD;
				
        data <= (others => '0');
        data(24) <= '1'; -- buffer_write
        data(20 downto 16) <= '0' & x"E"; -- buffer_data
        data(8) <= '0'; -- buffer_clear
        data(0) <= '0'; -- on_off
		generate_sync_wb_single_write(slvi,slvo,clk,data);
		wait for CLK_PERIOD;
		
        data <= (others => '0');
        data(24) <= '1'; -- buffer_write
        data(20 downto 16) <= '0' & x"F"; -- buffer_data
        data(8) <= '0'; -- buffer_clear
        data(0) <= '0'; -- on_off
		generate_sync_wb_single_write(slvi,slvo,clk,data);
		wait for CLK_PERIOD;
		
        wait for 100 us;

		assert false report "Simulation terminated!" severity failure;
	end process stimuli;

END ARCHITECTURE;