-- See the file "LICENSE" for the full license governing this code. --

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lt16x32_global.all;
use work.wishbone.all;
use work.config.all;

entity wb_switches is
	generic(
		memaddr		:	generic_addr_type; --:= CFG_BADR_SW;
		addrmask	:	generic_mask_type --:= CFG_MADR_SW;
	);
	port(
		clk		: in  std_logic;
		rst		: in  std_logic;
		wslvi	:	in	wb_slv_in_type;
		wslvo	:	out	wb_slv_out_type;

        buttons : in std_logic_vector(4 downto 0);
        switches : in std_logic_vector(15 downto 0);

        interrupt : out std_logic
	);
end wb_switches;

architecture Behavioral of wb_switches is

	signal data : std_logic_vector(20 downto 0);
	signal ack	: std_logic;

    signal old_input : std_logic_vector(20 downto 0);

begin

	process(clk)
	begin
		if clk'event and clk='1' then
			if rst = '1' then
				ack		<= '0';
				data	<= (others=>'0');
			else
				if wslvi.stb = '1' and wslvi.cyc = '1' then
				    if wslvi.we='0' then
                        data(15 downto 0) <= switches;
                        data(20 downto 16) <= buttons;
                    end if;
				
					if ack = '0' then
						ack	<= '1';
					else
						ack	<= '0';
					end if;
				else
					ack <= '0';
				end if;
			end if;
		end if;
	end process;

    process(clk)
	begin
		if clk'event and clk='1' then
			if rst = '1' then
                interrupt <= '0';
                old_input <= (others => '0');
            else
                if buttons & switches /= old_input
                then
                    interrupt <= '1';
                else
                    interrupt <= '0';
                end if;

                old_input(15 downto 0) <= switches;
                old_input(20 downto 16) <= buttons;
            end if;
        end if;
    end process;

	wslvo.dat(20 downto 0)	<= data;
	wslvo.dat(31 downto 21)	<= (others=>'0');

	wslvo.ack	<= ack;
	wslvo.wbcfg	<= wb_membar(memaddr, addrmask);

end Behavioral;