Set up testbench with 2 SOCs that communicate with CAN

programs/interrupt_test.prog

@@ -20,15 +20,11 @@ can_interrupt:
 
 .align
 led_addr: .word 0x000F0000
-timer_counter_addr: .word 0x000F0008
+switches_addr: .word 0x000F0004
-timer_status_addr: .word 0x000F000C
 dmem_start_addr: .word 0x00000400
 dmem_end_addr: .word 0x000004FC
 priority_mask: .word 0xFFFFFF03
 
-// timer_target_value: .word 127 // for simulation
-timer_target_value: .word 0xF10000 // for real board
-
 main:
     // Initialize stack pointer to the end of the data memory
     ldr r12, >dmem_end_addr
@@ -37,29 +33,22 @@ main:
     ldr r0, >priority_mask
     and r14, r0, r14
 
-    ldr r0,>led_addr               // LED addr
+    ldr r0, >led_addr
-    ldr r1,>timer_status_addr      // Timer addr
+    ldr r1, >switches_addr
-    ldr r3,>timer_counter_addr     // Timer addr
-
-    // Set LED to pattern
-    clr r2
-    addi r2, 0x7A
-    st08 r0, r2
-
-    // Enable the timer...
-    ldr r2, >timer_target_value
-    st32 r3, r2
-
-    clr r2
-    addi r2, 0x1 // enable bit set
-    st32 r1, r2
 
 loop:
     br >loop
     nop
 
-timer_interrupt_handler:
+switches_interrupt_handler:
+    ld32 r2, r1
+
     // Set LED to pattern
-    clr r2
-    addi r2, 0x0C
     st08 r0, r2
+    
+    reti
+    nop
+
+can_interrupt_handler:
+    reti
+    nop

programs/project.prog

@@ -0,0 +1,142 @@
+reset:
+    br always >main
+    nop
+
+hardfault:
+    reti
+    nop
+
+memfault:
+    reti
+    nop
+
+switches_interrupt:
+    br >switches_interrupt_handler
+    nop
+
+can_interrupt:
+    br >can_interrupt_handler
+    nop
+
+.align
+led_addr: .word 0x000F0000
+switches_addr: .word 0x000F0004
+dmem_start_addr: .word 0x00000400
+dmem_end_addr: .word 0x000004FC
+priority_mask: .word 0xFFFFFF03
+
+// CAN
+can_control_addr: .word 0x000F0100
+can_command_addr: .word 0x000F0101
+can_acceptance_code_addr: .word 0x000F0104
+can_acceptance_mask_addr: .word 0x000F0105
+can_bus_timing0_addr: .word 0x000F0106
+can_bus_timing1_addr: .word 0x000F0107
+can_output_control_addr: .word 0x000F0108
+can_identifier0_addr: .word 0x000F010A
+can_identifier1_addr: .word 0x000F010B
+can_data0_addr: .word 0x000F010C
+can_data1_addr: .word 0x000F010D
+
+// CAN Constants
+acceptance_code: .word 0x00
+acceptance_mask: .word 0xFF
+// btr0: .word 0x45 Real board
+// btr1: .word 0x16 Real board
+btr0: .word 0x80
+btr1: .word 0x48
+output_control: .word 0x02
+control: .word 0xFE
+id0: .word 0xAA
+id1: .word 0xC2
+
+main:
+    // Initialize stack pointer to the end of the data memory
+    ldr r12, >dmem_end_addr
+
+    // Set runtime priority
+    ldr r0, >priority_mask
+    and r14, r0, r14
+
+    // --- CAN init ---
+    ldr r0, >can_acceptance_code_addr
+    ldr r3, >acceptance_code
+    st08 r0, r3
+
+    ldr r0, >can_acceptance_mask_addr
+    ldr r3, >acceptance_mask
+    st08 r0, r3
+
+    ldr r0, >can_bus_timing0_addr
+    ldr r3, >btr0
+    st08 r0, r3
+
+    ldr r0, >can_bus_timing1_addr
+    ldr r3, >btr1
+    st08 r0, r3
+
+    ldr r0, >can_output_control_addr
+    ldr r3, >output_control
+    st08 r0, r3
+
+    ldr r0, >can_control_addr
+    ldr r3, >control
+    st08 r0, r3
+
+    ldr r0, >can_identifier0_addr
+    ldr r3, >id0
+    st08 r0, r3
+
+    ldr r0, >can_identifier1_addr
+    ldr r3, >id1
+    st08 r0, r3
+
+    ldr r0, >can_data0_addr
+    clr r3
+    addi r3, 0x7A
+    st08 r0, r3
+
+    ldr r0, >can_data1_addr
+    clr r3
+    addi r3, 0x4F
+    st08 r0, r3
+
+    // Wait some clks
+    call >wait
+
+    ldr r0, >can_command_addr
+    clr r3
+    addi r3, 0x01
+    st08 r0, r3
+
+    ldr r0, >led_addr
+    ldr r1, >switches_addr
+
+    st08 r0, r2
+loop:
+    br >loop
+    nop
+
+switches_interrupt_handler:
+    ld32 r2, r1
+
+    // Set LED to pattern
+    st08 r0, r2
+    
+    reti
+    nop
+
+can_interrupt_handler:
+    reti
+    nop
+
+wait:
+	clr r7
+    clr r8
+    addi r8, 16
+inc_i:
+	cmp neq r7,r8
+	br true >inc_i
+	addi r7,1
+	ret
+    nop

programs/project_init.prog

@@ -0,0 +1,116 @@
+reset:
+    br always >main
+    nop
+
+hardfault:
+    reti
+    nop
+
+memfault:
+    reti
+    nop
+
+switches_interrupt:
+    br >switches_interrupt_handler
+    nop
+
+can_interrupt:
+    br >can_interrupt_handler
+    nop
+
+.align
+led_addr: .word 0x000F0000
+switches_addr: .word 0x000F0004
+dmem_start_addr: .word 0x00000400
+dmem_end_addr: .word 0x000004FC
+priority_mask: .word 0xFFFFFF03
+
+// CAN
+can_control_addr: .word 0x000F0100
+can_command_addr: .word 0x000F0101
+can_acceptance_code_addr: .word 0x000F0104
+can_acceptance_mask_addr: .word 0x000F0105
+can_bus_timing0_addr: .word 0x000F0106
+can_bus_timing1_addr: .word 0x000F0107
+can_output_control_addr: .word 0x000F0108
+can_identifier0_addr: .word 0x000F010A
+can_identifier1_addr: .word 0x000F010B
+can_data0_addr: .word 0x000F010C
+can_data1_addr: .word 0x000F010D
+
+// CAN Constants
+acceptance_code: .word 0x00
+acceptance_mask: .word 0xFF
+// btr0: .word 0x45 Real board
+// btr1: .word 0x16 Real board
+btr0: .word 0x80
+btr1: .word 0x48
+output_control: .word 0x02
+control: .word 0xFE
+id0: .word 0xAA
+id1: .word 0xC2
+
+main:
+    // Initialize stack pointer to the end of the data memory
+    ldr r12, >dmem_end_addr
+
+    // Set runtime priority
+    ldr r0, >priority_mask
+    and r14, r0, r14
+
+    // --- CAN init ---
+    ldr r0, >can_acceptance_code_addr
+    ldr r3, >acceptance_code
+    st08 r0, r3
+
+    ldr r0, >can_acceptance_mask_addr
+    ldr r3, >acceptance_mask
+    st08 r0, r3
+
+    ldr r0, >can_bus_timing0_addr
+    ldr r3, >btr0
+    st08 r0, r3
+
+    ldr r0, >can_bus_timing1_addr
+    ldr r3, >btr1
+    st08 r0, r3
+
+    ldr r0, >can_output_control_addr
+    ldr r3, >output_control
+    st08 r0, r3
+
+    ldr r0, >can_control_addr
+    ldr r3, >control
+    st08 r0, r3
+
+    ldr r0, >led_addr
+    ldr r1, >switches_addr
+
+    st08 r0, r2
+loop:
+    br >loop
+    nop
+
+switches_interrupt_handler:
+    ld32 r2, r1
+
+    // Set LED to pattern
+    st08 r0, r2
+    
+    reti
+    nop
+
+can_interrupt_handler:
+    reti
+    nop
+
+wait:
+	clr r7
+    clr r8
+    addi r8, 16
+inc_i:
+	cmp neq r7,r8
+	br true >inc_i
+	addi r7,1
+	ret
+    nop

soc/testbench/project.vhd

@@ -3,6 +3,11 @@ LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 USE ieee.numeric_std.ALL;
 
+use work.wishbone.all;
+use work.config.all;
+use work.lt16soc_memories.all;
+use work.lt16soc_peripherals.all;
+
 ENTITY project_tb IS
 END ENTITY;
 
@@ -19,12 +24,13 @@ ARCHITECTURE sim OF project_tb IS
     signal anodes : std_logic_vector(7 downto 0);
     signal cathodes : std_logic_vector(7 downto 0);
     
-    signal can_rx_i	: std_logic := '1';
+	constant peer_num_inst : integer := 3;
-    signal can_tx_o	: std_logic := '1';
+	signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
+	signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
 
 	COMPONENT lt16soc_top IS
 		generic(
-			programfilename : string := "../../programs/interrupt_test.ram"
+			programfilename : string := "../../programs/project.ram"
 		);
 		port(
 			clk		: in  std_logic;
@@ -38,6 +44,15 @@ ARCHITECTURE sim OF project_tb IS
             can_tx_o : out std_logic
 		);
 	END COMPONENT;
+	
+    component phys_can_sim 
+		generic(
+			peer_num : integer );
+		port(
+			rst : in std_logic;
+			rx_vector : out std_logic_vector(peer_num - 1 downto 0);
+			tx_vector : in std_logic_vector(peer_num - 1 downto 0) );
+	end component phys_can_sim;
 
 BEGIN
 
@@ -49,9 +64,34 @@ BEGIN
 		sw=>sw,
         anodes=>anodes,
         cathodes=>cathodes,
-        can_rx_i=>can_rx_i,
+        can_rx_i=>rx_vector(0),
-        can_tx_o=>can_tx_o
+        can_tx_o=>tx_vector(0)
 	);
+	 
+    can_inst_2 : can_vhdl_top
+    generic map(
+        memaddr=>CFG_BADR_MEM,
+        addrmask=>CFG_MADR_FULL
+    )
+    port map(
+        clk	=> clk,
+        rstn	=> rst,
+        wbs_i	=> wbs_i2,
+        wbs_o	=> wbs_o2,
+        rx_i	=> rx_vector(1),
+        tx_o	=> tx_vector(1),
+        irq_on	=> irq_on2
+    );
+        
+    can_interconnect : phys_can_sim
+    generic map(
+        peer_num => 2
+    )
+    port map(
+        rst => rst,
+        rx_vector => can_rx,
+        tx_vector => can_tx
+    );
 
 	clk_gen: process
 	begin
@@ -64,9 +104,8 @@ BEGIN
 		rst	<= '0';
 		wait for CLK_PERIOD;
 		rst	<= '1';
-		wait for 100us;
+		wait for 300us;
 		assert false report "Simulation terminated!" severity failure;
 	end process stimuli;
 
-
 END ARCHITECTURE;

soc/testbench/project_2top.vhd

@@ -0,0 +1,119 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+use work.wishbone.all;
+use work.config.all;
+use work.lt16soc_memories.all;
+use work.lt16soc_peripherals.all;
+
+ENTITY project_2top_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF project_2top_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+
+	signal led0	: std_logic_vector(7 downto 0);
+    signal led1	: std_logic_vector(7 downto 0);
+    signal btn : std_logic_vector(4 downto 0) := (others => '0');
+    signal sw : std_logic_vector(15 downto 0) := (others => '0');
+    signal anodes0 : std_logic_vector(7 downto 0);
+    signal cathodes0 : std_logic_vector(7 downto 0);
+    signal anodes1 : std_logic_vector(7 downto 0);
+    signal cathodes1 : std_logic_vector(7 downto 0);
+    
+	constant peer_num_inst : integer := 2;
+	signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
+	signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
+
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/project.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0);
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0);
+            can_rx_i : in std_logic;
+            can_tx_o : out std_logic
+		);
+	END COMPONENT;
+	
+    component phys_can_sim 
+		generic(
+			peer_num : integer );
+		port(
+			rst : in std_logic;
+			rx_vector : out std_logic_vector(peer_num - 1 downto 0);
+			tx_vector : in std_logic_vector(peer_num - 1 downto 0) );
+	end component phys_can_sim;
+
+BEGIN
+
+	soc0: lt16soc_top
+    generic map(
+        programfilename => "../../programs/project.ram"
+    )
+    port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led0,
+		btn=>btn,
+		sw=>sw,
+        anodes=>anodes0,
+        cathodes=>cathodes0,
+        can_rx_i=>rx_vector(0),
+        can_tx_o=>tx_vector(0)
+	);
+
+    soc1: lt16soc_top
+    generic map(
+        programfilename => "../../programs/project_init.ram"
+    )
+    port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led1,
+		btn=>btn,
+		sw=>sw,
+        anodes=>anodes1,
+        cathodes=>cathodes1,
+        can_rx_i=>rx_vector(1),
+        can_tx_o=>tx_vector(1)
+	);
+        
+    can_interconnect : phys_can_sim
+    generic map(
+        peer_num => peer_num_inst
+    )
+    port map(
+        rst => not rst,
+        rx_vector => rx_vector,
+        tx_vector => tx_vector
+    );
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '0';
+		wait for CLK_PERIOD;
+		rst	<= '1';
+		wait for 300us;
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+END ARCHITECTURE;

soc/testbench/switches_interrupt_tb.vhd

@@ -0,0 +1,76 @@
+-- See the file "LICENSE" for the full license governing this code. --
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+ENTITY switches_interrupt_tb IS
+END ENTITY;
+
+ARCHITECTURE sim OF switches_interrupt_tb IS
+
+	constant CLK_PERIOD : time := 10 ns;
+
+	signal clk 	: std_logic := '0';
+	signal rst	: std_logic;
+
+	signal led	: std_logic_vector(7 downto 0);
+    signal btn : std_logic_vector(4 downto 0) := (others => '0');
+    signal sw : std_logic_vector(15 downto 0) := (others => '0');
+    signal anodes : std_logic_vector(7 downto 0);
+    signal cathodes : std_logic_vector(7 downto 0);
+    signal can_tx_o : std_logic;
+    signal can_rx_i : std_logic := '0';
+
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/interrupt_test.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0);
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0);
+            can_tx_o : out std_logic;
+            can_rx_i : in std_logic
+		);
+	END COMPONENT;
+
+BEGIN
+
+	dut: lt16soc_top port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw,
+        anodes=>anodes,
+        cathodes=>cathodes,
+        can_rx_i=>can_rx_i,
+        can_tx_o=>can_tx_o
+	);
+
+	clk_gen: process
+	begin
+		clk	<= not clk;
+		wait for CLK_PERIOD/2;
+	end process clk_gen;
+
+	stimuli: process
+	begin
+		rst	<= '0';
+		wait for CLK_PERIOD;
+		rst	<= '1';
+		
+		wait for 1us;
+		sw <= x"ACAB";
+		
+		wait for 1us;
+		
+		assert false report "Simulation terminated!" severity failure;
+	end process stimuli;
+
+
+END ARCHITECTURE;

soc/testbench/warmup4.vhd

@@ -21,7 +21,7 @@ ARCHITECTURE sim OF warmup4_tb IS
 
 	COMPONENT lt16soc_top IS
 		generic(
-			programfilename : string := "../../programs/scrolling.ram"
+			programfilename : string := "../../programs/interrupt_test.ram"
 		);
 		port(
 			clk		: in  std_logic;

soc/top/top.vhd

@@ -183,14 +183,14 @@ begin
 		addrmask=>CFG_MADR_DMEM)
 	port map(clk,rst_gen,slvi(CFG_DMEM),slvo(CFG_DMEM));
 
-    can_inst : component can_vhdl_top
+    can_inst : can_vhdl_top
     generic map(
         memaddr=>CFG_BADR_CAN,
         addrmask=>CFG_MADR_CAN
     )
     port map(
         clk	=> clk,
-        rstn	=> rst,
+        rstn	=> rst_gen,
         wbs_i	=> slvi(CFG_CAN),
         wbs_o	=> slvo(CFG_CAN),
         rx_i	=> can_rx_i,
@@ -216,7 +216,7 @@ begin
 		CFG_BADR_SW,CFG_MADR_SW
 	)
 	port map(
-		clk,rst_gen,slvi(CFG_SW),slvo(CFG_SW), btn, sw
+		clk,rst_gen,slvi(CFG_SW),slvo(CFG_SW), btn, sw, irq_lines(3)
 	);
 	
     timerdev : wb_timer
@@ -228,8 +228,7 @@ begin
 		clk,
         rst_gen,
         slvi(CFG_TIMER),
-        slvo(CFG_TIMER),
+        slvo(CFG_TIMER)
-        irq_lines(3)
 	);
 	
     scrollingdev : wb_scrolling