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Set up testbench with 2 SOCs that communicate with CAN

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This commit is contained in:
Derek Christ
2022-12-11 13:36:13 +01:00
parent 7af2c51d61
commit fb051ccca4
8 changed files with 517 additions and 37 deletions
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53
soc/testbench/project.vhd
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@@ -3,6 +3,11 @@ LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.wishbone.all;
use work.config.all;
use work.lt16soc_memories.all;
use work.lt16soc_peripherals.all;
ENTITY project_tb IS
END ENTITY;
@@ -19,12 +24,13 @@ ARCHITECTURE sim OF project_tb IS
signal anodes : std_logic_vector(7 downto 0);
signal cathodes : std_logic_vector(7 downto 0);
signal can_rx_i : std_logic := '1';
signal can_tx_o : std_logic := '1';
constant peer_num_inst : integer := 3;
signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
COMPONENT lt16soc_top IS
generic(
programfilename : string := "../../programs/interrupt_test.ram"
programfilename : string := "../../programs/project.ram"
);
port(
clk : in std_logic;
@@ -38,6 +44,15 @@ ARCHITECTURE sim OF project_tb IS
can_tx_o : out std_logic
);
END COMPONENT;
component phys_can_sim
generic(
peer_num : integer );
port(
rst : in std_logic;
rx_vector : out std_logic_vector(peer_num - 1 downto 0);
tx_vector : in std_logic_vector(peer_num - 1 downto 0) );
end component phys_can_sim;
BEGIN
@@ -49,9 +64,34 @@ BEGIN
sw=>sw,
anodes=>anodes,
cathodes=>cathodes,
can_rx_i=>can_rx_i,
can_tx_o=>can_tx_o
can_rx_i=>rx_vector(0),
can_tx_o=>tx_vector(0)
);
can_inst_2 : can_vhdl_top
generic map(
memaddr=>CFG_BADR_MEM,
addrmask=>CFG_MADR_FULL
)
port map(
clk => clk,
rstn => rst,
wbs_i => wbs_i2,
wbs_o => wbs_o2,
rx_i => rx_vector(1),
tx_o => tx_vector(1),
irq_on => irq_on2
);
can_interconnect : phys_can_sim
generic map(
peer_num => 2
)
port map(
rst => rst,
rx_vector => can_rx,
tx_vector => can_tx
);
clk_gen: process
begin
@@ -64,9 +104,8 @@ BEGIN
rst <= '0';
wait for CLK_PERIOD;
rst <= '1';
wait for 100us;
wait for 300us;
assert false report "Simulation terminated!" severity failure;
end process stimuli;
END ARCHITECTURE;

119
soc/testbench/project_2top.vhd Normal file
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@@ -0,0 +1,119 @@
-- See the file "LICENSE" for the full license governing this code. --
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.wishbone.all;
use work.config.all;
use work.lt16soc_memories.all;
use work.lt16soc_peripherals.all;
ENTITY project_2top_tb IS
END ENTITY;
ARCHITECTURE sim OF project_2top_tb IS
constant CLK_PERIOD : time := 10 ns;
signal clk : std_logic := '0';
signal rst : std_logic;
signal led0 : std_logic_vector(7 downto 0);
signal led1 : std_logic_vector(7 downto 0);
signal btn : std_logic_vector(4 downto 0) := (others => '0');
signal sw : std_logic_vector(15 downto 0) := (others => '0');
signal anodes0 : std_logic_vector(7 downto 0);
signal cathodes0 : std_logic_vector(7 downto 0);
signal anodes1 : std_logic_vector(7 downto 0);
signal cathodes1 : std_logic_vector(7 downto 0);
constant peer_num_inst : integer := 2;
signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
COMPONENT lt16soc_top IS
generic(
programfilename : string := "../../programs/project.ram"
);
port(
clk : in std_logic;
rst : in std_logic;
led : out std_logic_vector(7 downto 0);
btn : in std_logic_vector(4 downto 0);
sw : in std_logic_vector(15 downto 0);
anodes : out std_logic_vector(7 downto 0);
cathodes : out std_logic_vector(7 downto 0);
can_rx_i : in std_logic;
can_tx_o : out std_logic
);
END COMPONENT;
component phys_can_sim
generic(
peer_num : integer );
port(
rst : in std_logic;
rx_vector : out std_logic_vector(peer_num - 1 downto 0);
tx_vector : in std_logic_vector(peer_num - 1 downto 0) );
end component phys_can_sim;
BEGIN
soc0: lt16soc_top
generic map(
programfilename => "../../programs/project.ram"
)
port map(
clk=>clk,
rst=>rst,
led=>led0,
btn=>btn,
sw=>sw,
anodes=>anodes0,
cathodes=>cathodes0,
can_rx_i=>rx_vector(0),
can_tx_o=>tx_vector(0)
);
soc1: lt16soc_top
generic map(
programfilename => "../../programs/project_init.ram"
)
port map(
clk=>clk,
rst=>rst,
led=>led1,
btn=>btn,
sw=>sw,
anodes=>anodes1,
cathodes=>cathodes1,
can_rx_i=>rx_vector(1),
can_tx_o=>tx_vector(1)
);
can_interconnect : phys_can_sim
generic map(
peer_num => peer_num_inst
)
port map(
rst => not rst,
rx_vector => rx_vector,
tx_vector => tx_vector
);
clk_gen: process
begin
clk <= not clk;
wait for CLK_PERIOD/2;
end process clk_gen;
stimuli: process
begin
rst <= '0';
wait for CLK_PERIOD;
rst <= '1';
wait for 300us;
assert false report "Simulation terminated!" severity failure;
end process stimuli;
END ARCHITECTURE;

76
soc/testbench/switches_interrupt_tb.vhd Normal file
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@@ -0,0 +1,76 @@
-- See the file "LICENSE" for the full license governing this code. --
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY switches_interrupt_tb IS
END ENTITY;
ARCHITECTURE sim OF switches_interrupt_tb IS
constant CLK_PERIOD : time := 10 ns;
signal clk : std_logic := '0';
signal rst : std_logic;
signal led : std_logic_vector(7 downto 0);
signal btn : std_logic_vector(4 downto 0) := (others => '0');
signal sw : std_logic_vector(15 downto 0) := (others => '0');
signal anodes : std_logic_vector(7 downto 0);
signal cathodes : std_logic_vector(7 downto 0);
signal can_tx_o : std_logic;
signal can_rx_i : std_logic := '0';
COMPONENT lt16soc_top IS
generic(
programfilename : string := "../../programs/interrupt_test.ram"
);
port(
clk : in std_logic;
rst : in std_logic;
led : out std_logic_vector(7 downto 0);
btn : in std_logic_vector(4 downto 0);
sw : in std_logic_vector(15 downto 0);
anodes : out std_logic_vector(7 downto 0);
cathodes : out std_logic_vector(7 downto 0);
can_tx_o : out std_logic;
can_rx_i : in std_logic
);
END COMPONENT;
BEGIN
dut: lt16soc_top port map(
clk=>clk,
rst=>rst,
led=>led,
btn=>btn,
sw=>sw,
anodes=>anodes,
cathodes=>cathodes,
can_rx_i=>can_rx_i,
can_tx_o=>can_tx_o
);
clk_gen: process
begin
clk <= not clk;
wait for CLK_PERIOD/2;
end process clk_gen;
stimuli: process
begin
rst <= '0';
wait for CLK_PERIOD;
rst <= '1';
wait for 1us;
sw <= x"ACAB";
wait for 1us;
assert false report "Simulation terminated!" severity failure;
end process stimuli;
END ARCHITECTURE;

2
soc/testbench/warmup4.vhd
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@@ -21,7 +21,7 @@ ARCHITECTURE sim OF warmup4_tb IS
COMPONENT lt16soc_top IS
generic(
programfilename : string := "../../programs/scrolling.ram"
programfilename : string := "../../programs/interrupt_test.ram"
);
port(
clk : in std_logic;

9
soc/top/top.vhd
View File

@@ -183,14 +183,14 @@ begin
addrmask=>CFG_MADR_DMEM)
port map(clk,rst_gen,slvi(CFG_DMEM),slvo(CFG_DMEM));
can_inst : component can_vhdl_top
can_inst : can_vhdl_top
generic map(
memaddr=>CFG_BADR_CAN,
addrmask=>CFG_MADR_CAN
)
port map(
clk => clk,
rstn => rst,
rstn => rst_gen,
wbs_i => slvi(CFG_CAN),
wbs_o => slvo(CFG_CAN),
rx_i => can_rx_i,
@@ -216,7 +216,7 @@ begin
CFG_BADR_SW,CFG_MADR_SW
)
port map(
clk,rst_gen,slvi(CFG_SW),slvo(CFG_SW), btn, sw
clk,rst_gen,slvi(CFG_SW),slvo(CFG_SW), btn, sw, irq_lines(3)
);
timerdev : wb_timer
@@ -228,8 +228,7 @@ begin
clk,
rst_gen,
slvi(CFG_TIMER),
slvo(CFG_TIMER),
irq_lines(3)
slvo(CFG_TIMER)
);
scrollingdev : wb_scrolling