Set up testbench with 2 SOCs that communicate with CAN
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116
programs/project_init.prog
Normal file
116
programs/project_init.prog
Normal file
@@ -0,0 +1,116 @@
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reset:
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br always >main
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nop
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hardfault:
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reti
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nop
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memfault:
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reti
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nop
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switches_interrupt:
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br >switches_interrupt_handler
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nop
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can_interrupt:
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br >can_interrupt_handler
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nop
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.align
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led_addr: .word 0x000F0000
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switches_addr: .word 0x000F0004
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dmem_start_addr: .word 0x00000400
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dmem_end_addr: .word 0x000004FC
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priority_mask: .word 0xFFFFFF03
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// CAN
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can_control_addr: .word 0x000F0100
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can_command_addr: .word 0x000F0101
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can_acceptance_code_addr: .word 0x000F0104
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can_acceptance_mask_addr: .word 0x000F0105
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can_bus_timing0_addr: .word 0x000F0106
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can_bus_timing1_addr: .word 0x000F0107
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can_output_control_addr: .word 0x000F0108
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can_identifier0_addr: .word 0x000F010A
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can_identifier1_addr: .word 0x000F010B
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can_data0_addr: .word 0x000F010C
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can_data1_addr: .word 0x000F010D
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// CAN Constants
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acceptance_code: .word 0x00
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acceptance_mask: .word 0xFF
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// btr0: .word 0x45 Real board
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// btr1: .word 0x16 Real board
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btr0: .word 0x80
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btr1: .word 0x48
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output_control: .word 0x02
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control: .word 0xFE
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id0: .word 0xAA
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id1: .word 0xC2
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main:
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// Initialize stack pointer to the end of the data memory
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ldr r12, >dmem_end_addr
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// Set runtime priority
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ldr r0, >priority_mask
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and r14, r0, r14
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// --- CAN init ---
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ldr r0, >can_acceptance_code_addr
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ldr r3, >acceptance_code
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st08 r0, r3
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ldr r0, >can_acceptance_mask_addr
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ldr r3, >acceptance_mask
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st08 r0, r3
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ldr r0, >can_bus_timing0_addr
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ldr r3, >btr0
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st08 r0, r3
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ldr r0, >can_bus_timing1_addr
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ldr r3, >btr1
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st08 r0, r3
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ldr r0, >can_output_control_addr
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ldr r3, >output_control
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st08 r0, r3
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ldr r0, >can_control_addr
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ldr r3, >control
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st08 r0, r3
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ldr r0, >led_addr
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ldr r1, >switches_addr
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st08 r0, r2
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loop:
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br >loop
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nop
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switches_interrupt_handler:
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ld32 r2, r1
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// Set LED to pattern
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st08 r0, r2
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reti
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nop
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can_interrupt_handler:
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reti
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nop
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wait:
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clr r7
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clr r8
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addi r8, 16
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inc_i:
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cmp neq r7,r8
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br true >inc_i
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addi r7,1
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ret
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nop
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