Fix some bugs for real board warumup4

2022-11-21 12:17:43 +01:00
parent 4666ae9bf8
commit e5879022b7
3 changed files with 64 additions and 36 deletions
--- a/soc/peripheral/seven_segment_display.vhd
+++ b/soc/peripheral/seven_segment_display.vhd
@@ -54,8 +54,8 @@ begin
    );

    timer: simple_timer
-    generic map (timer_start => x"00000008") -- for simulation
-    -- generic map (timer_start => x"00000F00") -- for board
+    -- generic map (timer_start => x"00000008") -- for simulation
+    generic map (timer_start => x"00000F00") -- for board
    port map(
        clk => clk,
        rst => rst,
--- a/soc/top/top.vhd
+++ b/soc/top/top.vhd
@@ -14,7 +14,7 @@ use work.lt16soc_peripherals.all;

 entity lt16soc_top is
 generic(
-	programfilename : string := "../../programs/timer_blinky.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
+	programfilename : string := "../../programs/scrolling.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
 );
 port(
 	-- clock signal