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Fix numerous bugs in the scrolling segment module

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This commit is contained in:
Derek Christ
2022-11-22 20:07:39 +01:00
parent e0369944b4
commit c6b290a5c0
8 changed files with 222 additions and 42 deletions
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19
programs/scrolling.prog
View File

@@ -12,11 +12,11 @@ nop
scrolling_addr: .word 0x000F00A0
scrolling_count_addr: .word 0x000F00A4
scrolling_cnt_value: .word 0x20FC000 // for real board
// scrolling_cnt_value: .word 0x100 // for simulation
// scrolling_cnt_value: .word 0x20FC000 // for real board
scrolling_cnt_value: .word 0x500 // for simulation
w_cnt_top: .word 0x3FC000 // for real board
// w_cnt_top: .word 0x100 //for simulation
// w_cnt_top: .word 0x3FC000 // for real board
w_cnt_top: .word 0x100 //for simulation
pattern_ptr: .word =pattern1
@@ -29,17 +29,16 @@ pattern1:
pattern2:
.word 0x0F0E0E0B
.word 0x100D0A0E
.word 0x0D000000
.word 0x0D101010
pattern3:
.word 0x01101010
pattern4:
.word 0x02100310
.word 0x02031010
pattern5:
.word 0x00100010
.word 0x00100010
.word 0x00000000
.word 0x00101010
write_mask:
@@ -213,7 +212,9 @@ display_loop3:
// --------- 0 0 0 0 0 ---------
clr r7
clr r11
addi r11, 12 // iterations
addi r11, 8
// iterations
display_loop4:
addi r3, 0x01
call >display_char

2
soc/peripheral/scrolling_buffer.vhd
View File

@@ -53,6 +53,8 @@ begin
elsif buffer_clear = '1' then
ptr_last <= -1;
ptr_write <= 0;
elements <= (others => '0');
ring_buffer <= (others => (others => '0'));
end if;
end if;
end if;

61
soc/peripheral/scrolling_controller.vhd
View File

@@ -25,12 +25,12 @@ architecture Behavioral of scrolling_controller is
type state_type is (s_off, s_wait, s_update);
signal state : state_type;
signal sig_seg_data_in : std_logic;
signal sig_seg_shift : std_logic;
signal sig_seg_write : std_logic;
signal sig_seg_clear : std_logic;
signal shift_state : integer range 1 to 16;
signal current_element : integer range 0 to 16;
signal current_resetted : std_logic;
begin
@@ -42,15 +42,17 @@ begin
cnt_start <= '0';
next_char <= '0';
sig_seg_data_in <= '0';
sig_seg_shift <= '0';
sig_seg_write <= '0';
sig_seg_clear <= '0';
else
sig_seg_data_in <= '0';
current_element <= 0;
current_resetted <= '0';
else
case state is
when s_off =>
current_element <= 0;
if on_off = '0' then
state <= s_off;
sig_seg_shift <= '0';
@@ -59,13 +61,12 @@ begin
cnt_start <= '0';
next_char <= '0';
else
state <= s_update;
sig_seg_data_in <= '1';
sig_seg_shift <= '1';
sig_seg_write <= '1';
state <= s_wait;
sig_seg_shift <= '0';
sig_seg_write <= '0';
sig_seg_clear <= '0';
cnt_start <= '1';
next_char <= '1';
next_char <= '0';
end if;
when s_wait =>
if on_off = '1' then
@@ -86,12 +87,22 @@ begin
sig_seg_write <= '0';
sig_seg_clear <= '0';
cnt_start <= '1';
next_char <= '1';
if current_element < unsigned(buffer_elements) then
next_char <= '1';
end if;
current_resetted <= '0';
if current_element = 15 then
current_element <= 0;
current_resetted <= '1';
else
current_element <= current_element + 1;
end if;
end if;
when s_update =>
if on_off = '0' then
state <= s_wait;
sig_seg_data_in <= '1';
sig_seg_shift <= '1';
sig_seg_write <= '1';
sig_seg_clear <= '0';
@@ -117,26 +128,18 @@ begin
seg_shift <= '0';
seg_write <= '0';
seg_clear <= '1';
shift_state <= 16;
else
seg_write <= '0';
if sig_seg_data_in = '1' and shift_state <= unsigned(buffer_elements) then
seg_write <= sig_seg_write;
else
if current_element < unsigned(buffer_elements) and not (current_resetted = '1' and unsigned(buffer_elements) /= 16) then
seg_data <= hex_char(3 downto 0);
seg_off <= hex_char(4);
else
seg_data <= x"0";
seg_off <= '1';
end if;
if sig_seg_shift = '1' then
if shift_state = 16 then
shift_state <= 1;
else
shift_state <= shift_state + 1;
end if;
end if;
seg_data <= hex_char(3 downto 0);
seg_off <= hex_char(4);
seg_shift <= sig_seg_shift;
seg_clear <= sig_seg_clear;
seg_write <= sig_seg_write;
seg_shift <= sig_seg_shift;
end if;
end if;
end process;

8
soc/peripheral/seven_segment_display.vhd
View File

@@ -54,8 +54,8 @@ begin
);
timer: simple_timer
-- generic map (timer_start => x"00000008") -- for simulation
generic map (timer_start => x"00000F00") -- for board
generic map (timer_start => x"00000008") -- for simulation
-- generic map (timer_start => x"00000F00") -- for board
port map(
clk => clk,
rst => rst,
@@ -96,7 +96,9 @@ begin
anodes <= (others => not '0');
overflow_counter <= 0;
else
if timer_overflow = '1' then
if seg_clear = '1' then
overflow_counter <= 0;
elsif timer_overflow = '1' then
if overflow_counter = 7 then
overflow_counter <= 0;
else

56
soc/testbench/scrolling_buffer_tb.vhd
View File

@@ -109,10 +109,66 @@ BEGIN
wait for CLK_PERIOD * 8;
buffer_clear <= '1';
next_char <= '0';
wait for CLK_PERIOD;
buffer_clear <= '0';
buffer_data <= '0' & x"D";
buffer_write <= '1';
wait for CLK_PERIOD;
buffer_data <= '0' & x"E";
wait for CLK_PERIOD;
buffer_data <= '0' & x"A";
wait for CLK_PERIOD;
buffer_data <= '0' & x"D";
wait for CLK_PERIOD;
buffer_data <= '0' & x"B";
wait for CLK_PERIOD;
buffer_data <= '0' & x"E";
wait for CLK_PERIOD;
buffer_data <= '0' & x"E";
wait for CLK_PERIOD;
buffer_data <= '0' & x"F";
wait for CLK_PERIOD;
buffer_data <= (others => '0');
buffer_write <= '0';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
next_char <= '1';
wait for CLK_PERIOD;
assert hex_char = '0' & x"D" severity failure;
wait for CLK_PERIOD;
assert hex_char = '0' & x"E" severity failure;
wait for CLK_PERIOD;
assert hex_char = '0' & x"A" severity failure;
wait for CLK_PERIOD;
assert hex_char = '0' & x"D" severity failure;
wait for CLK_PERIOD;
assert hex_char = '0' & x"B" severity failure;
wait for CLK_PERIOD;
assert hex_char = '0' & x"E" severity failure;
wait for CLK_PERIOD;
assert hex_char = '0' & x"E" severity failure;
wait for CLK_PERIOD;
assert hex_char = '0' & x"F" severity failure;
wait for CLK_PERIOD * 8;
assert false report "Simulation terminated!" severity failure;

52
soc/testbench/scrolling_top_tb.vhd
View File

@@ -98,6 +98,7 @@ BEGIN
data(0) <= '1'; -- on_off
generate_sync_wb_single_write(slvi,slvo,clk,data);
wait for CLK_PERIOD;
data <= (others => '0');
data(0) <= '0'; -- on_off
generate_sync_wb_single_write(slvi,slvo,clk,data);
@@ -202,6 +203,57 @@ BEGIN
generate_sync_wb_single_write(slvi,slvo,clk,data);
wait for CLK_PERIOD;
wait for 100 us;
data <= (others => '0');
data(0) <= '1'; -- on_off
generate_sync_wb_single_write(slvi,slvo,clk,data);
wait for CLK_PERIOD;
data <= (others => '0');
data(8) <= '1'; -- buffer_clear
generate_sync_wb_single_write(slvi,slvo,clk,data);
wait for CLK_PERIOD;
data <= (others => '0');
data(24) <= '1'; -- buffer_write
data(20 downto 16) <= '0' & x"D"; -- buffer_data
generate_sync_wb_single_write(slvi,slvo,clk,data);
wait for CLK_PERIOD;
data(20 downto 16) <= '0' & x"E"; -- buffer_data
generate_sync_wb_single_write(slvi,slvo,clk,data);
wait for CLK_PERIOD;
data(20 downto 16) <= '0' & x"A"; -- buffer_data
generate_sync_wb_single_write(slvi,slvo,clk,data);
wait for CLK_PERIOD;
data(20 downto 16) <= '0' & x"D"; -- buffer_data
generate_sync_wb_single_write(slvi,slvo,clk,data);
wait for CLK_PERIOD;
data(20 downto 16) <= '0' & x"B"; -- buffer_data
generate_sync_wb_single_write(slvi,slvo,clk,data);
wait for CLK_PERIOD;
data(20 downto 16) <= '0' & x"E"; -- buffer_data
generate_sync_wb_single_write(slvi,slvo,clk,data);
wait for CLK_PERIOD;
data(20 downto 16) <= '0' & x"E"; -- buffer_data
generate_sync_wb_single_write(slvi,slvo,clk,data);
wait for CLK_PERIOD;
data(20 downto 16) <= '0' & x"F"; -- buffer_data
generate_sync_wb_single_write(slvi,slvo,clk,data);
wait for CLK_PERIOD;
data <= (others => '0');
data(0) <= '1'; -- on_off
generate_sync_wb_single_write(slvi,slvo,clk,data);
wait for CLK_PERIOD;
wait for 100 us;
assert false report "Simulation terminated!" severity failure;

64
soc/testbench/segment_tb.vhd
View File

@@ -136,6 +136,70 @@ BEGIN
wait for 1 us;
seg_shift <= '1'; -- shift
seg_clear <= '0'; -- clear
seg_write <= '1'; -- write
seg_off <= '0'; -- off
seg_data <= x"D"; -- data
wait for CLK_PERIOD;
seg_shift <= '1'; -- shift
seg_clear <= '0'; -- clear
seg_write <= '1'; -- write
seg_off <= '0'; -- off
seg_data <= x"E"; -- data
wait for CLK_PERIOD;
seg_shift <= '1'; -- shift
seg_clear <= '0'; -- clear
seg_write <= '1'; -- write
seg_off <= '0'; -- off
seg_data <= x"A"; -- data
wait for CLK_PERIOD;
seg_shift <= '1'; -- shift
seg_clear <= '0'; -- clear
seg_write <= '1'; -- write
seg_off <= '0'; -- off
seg_data <= x"D"; -- data
wait for CLK_PERIOD;
seg_shift <= '1'; -- shift
seg_clear <= '0'; -- clear
seg_write <= '1'; -- write
seg_off <= '0'; -- off
seg_data <= x"B"; -- data
wait for CLK_PERIOD;
seg_shift <= '1'; -- shift
seg_clear <= '0'; -- clear
seg_write <= '1'; -- write
seg_off <= '0'; -- off
seg_data <= x"E"; -- data
wait for CLK_PERIOD;
seg_shift <= '1'; -- shift
seg_clear <= '0'; -- clear
seg_write <= '1'; -- write
seg_off <= '0'; -- off
seg_data <= x"E"; -- data
wait for CLK_PERIOD;
seg_shift <= '1'; -- shift
seg_clear <= '0'; -- clear
seg_write <= '1'; -- write
seg_off <= '0'; -- off
seg_data <= x"F"; -- data
wait for CLK_PERIOD;
seg_shift <= '0'; -- shift
seg_clear <= '0'; -- clear
seg_write <= '0'; -- write
seg_off <= '0'; -- off
seg_data <= x"F"; -- data
wait for 1 us;
assert false report "Simulation terminated!" severity failure;
end process stimuli;

2
soc/testbench/warmup4.vhd
View File

@@ -57,7 +57,7 @@ BEGIN
rst <= '0';
wait for CLK_PERIOD;
rst <= '1';
wait for 2ms;
wait for 5ms;
assert false report "Simulation terminated!" severity failure;
end process stimuli;