Add scrolling controller and testbench
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104
soc/peripheral/scrolling_controller.vhd
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104
soc/peripheral/scrolling_controller.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity scrolling_controller is
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port(
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clk : in std_logic;
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rst : in std_logic;
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on_off : in std_logic;
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cnt_start : out std_logic;
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cnt_done : in std_logic;
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next_char : out std_logic;
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hex_char : in std_logic_vector(4 downto 0);
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seg_data : out std_logic_vector(3 downto 0);
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seg_off : out std_logic;
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seg_shift : out std_logic;
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seg_write : out std_logic;
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seg_clear : out std_logic
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);
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end entity scrolling_controller;
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architecture Behavioral of scrolling_controller is
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type state_type is (s_off, s_wait, s_update);
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signal state : state_type;
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begin
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process(clk)
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begin
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if clk'event and clk='1' then
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if rst = '1' then
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state <= s_off;
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seg_clear <= '1';
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cnt_start <= '0';
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next_char <= '0';
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seg_data <= (others => '0');
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seg_off <= '0';
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seg_shift <= '0';
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seg_write <= '0';
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else
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case state is
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when s_off =>
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if on_off = '0' then
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state <= s_off;
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seg_shift <= '0';
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seg_write <= '0';
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seg_clear <= '0';
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cnt_start <= '0';
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next_char <= '0';
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else
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state <= s_update;
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seg_data <= hex_char(3 downto 0);
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seg_shift <= '1';
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seg_write <= '1';
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seg_clear <= '0';
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seg_off <= hex_char(4);
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cnt_start <= '1';
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next_char <= '1';
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end if;
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when s_wait =>
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if on_off = '1' then
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state <= s_off;
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seg_clear <= '1';
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cnt_start <= '0';
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next_char <= '0';
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elsif cnt_done = '0' then
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state <= s_wait;
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seg_shift <= '0';
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seg_write <= '0';
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seg_clear <= '0';
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cnt_start <= '0';
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next_char <= '0';
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else -- cnt_cone = '1'
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state <= s_update;
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seg_shift <= '0';
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seg_write <= '0';
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seg_clear <= '0';
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cnt_start <= '1';
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next_char <= '1';
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end if;
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when s_update =>
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if on_off = '0' then
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state <= s_wait;
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seg_data <= hex_char(3 downto 0);
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seg_shift <= '1';
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seg_write <= '1';
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seg_clear <= '0';
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seg_off <= hex_char(4);
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cnt_start <= '0';
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next_char <= '0';
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else
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state <= s_off;
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seg_clear <= '1';
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cnt_start <= '0';
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next_char <= '0';
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end if;
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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102
soc/testbench/scrolling_controller_tb.vhd
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102
soc/testbench/scrolling_controller_tb.vhd
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-- See the file "LICENSE" for the full license governing this code. --
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY work;
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USE work.lt16soc_peripherals.ALL;
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ENTITY scrolling_controller_tb IS
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END ENTITY;
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ARCHITECTURE sim OF scrolling_controller_tb IS
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constant CLK_PERIOD : time := 10 ns;
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signal rst : std_logic;
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signal clk : std_logic := '0';
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signal on_off : std_logic := '0';
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signal cnt_start : std_logic := '0';
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signal cnt_done : std_logic := '0';
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signal next_char : std_logic := '0';
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signal hex_char : std_logic_vector(4 downto 0) := (others => '0');
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signal seg_data : std_logic_vector(3 downto 0) := (others => '0');
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signal seg_off : std_logic := '0';
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signal seg_shift : std_logic := '0';
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signal seg_write : std_logic := '0';
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signal seg_clear : std_logic := '0';
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component scrolling_controller
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port(
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clk : in std_logic;
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rst : in std_logic;
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on_off : in std_logic;
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cnt_start : out std_logic;
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cnt_done : in std_logic;
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next_char : out std_logic;
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hex_char : in std_logic_vector(4 downto 0);
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seg_data : out std_logic_vector(3 downto 0);
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seg_off : out std_logic;
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seg_shift : out std_logic;
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seg_write : out std_logic;
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seg_clear : out std_logic
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);
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end component;
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BEGIN
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controller: scrolling_controller
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port map(
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clk => clk,
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rst => rst,
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on_off => on_off,
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cnt_start => cnt_start,
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cnt_done => cnt_done,
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next_char => next_char,
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hex_char => hex_char,
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seg_data => seg_data,
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seg_off => seg_off,
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seg_shift => seg_shift,
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seg_write => seg_write,
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seg_clear => seg_clear
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);
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clk_gen: process
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begin
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clk <= not clk;
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wait for CLK_PERIOD/2;
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end process clk_gen;
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stimuli: process
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begin
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rst <= '1';
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wait for CLK_PERIOD;
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rst <= '0';
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wait for CLK_PERIOD;
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hex_char <= "01010";
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wait for CLK_PERIOD * 2;
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on_off <= '1';
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wait for CLK_PERIOD;
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on_off <= '0';
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wait for CLK_PERIOD*3;
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hex_char <= "00101";
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cnt_done <= '1';
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wait for CLK_PERIOD;
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cnt_done <= '0';
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wait for CLK_PERIOD * 3;
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on_off <= '1';
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hex_char <= "01111";
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wait for CLK_PERIOD * 5;
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assert false report "Simulation terminated!" severity failure;
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end process stimuli;
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END ARCHITECTURE;
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